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( [111.196.135.79]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 07 Dec 2022 21:53:53 +0800 (CST) X-QQ-SSF: 01200000002000B0B000B00A0000000 X-QQ-FEAT: znfcQSa1hKahN1m9MXihhlD9H25KcTrmlTsiK+jnZWRL9/KxDfCfAcvhFsc/S H6xwwcByw5o8tyboieoNR+AmVut1u5dwzH1z7kU8wcl95Mbu8Q5d9o585jd++GMqxXex3jm CkZv5G0mO+lxy1HIvqPQgiBjL+Xg/FTbI3XP92dc2IIwtBscteuxqYwu9H8dMfTPR2pi76w XdcDgwtn7ldi7QrfHXzB8kvjGfAzHnmjj/vVARdO1lFukykzUI/F+5Z05FMnzMCP0w6VihL Ij5qHkPkSvQihQ2PzgtxZMIcnd8yQ+naJaNuU5uA8uQjy5YHwcnRNQRB0Q3PWeJGSSWdsg4 lZEa5S3bFSh34fllrOvku39hQehmbNfimeWSEpMnQ1n/6Mvmn1T+aPsOt85ag== X-QQ-GoodBg: 0 From: Bin Meng To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org Cc: Catalin Marinas , Greg Kroah-Hartman , Jiri Slaby , Russell King , Will Deacon , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 1/3] serial: earlycon-arm-semihost: Move smh_putc() variants in respective arch's semihost.h Date: Wed, 7 Dec 2022 21:53:50 +0800 Message-Id: <20221207135352.592556-1-bmeng@tinylab.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:tinylab.org:qybglogicsvr:qybglogicsvr3 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H2, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751564068534363457?= X-GMAIL-MSGID: =?utf-8?q?1751564068534363457?= Move smh_putc() variants in respective arch/*/include/asm/semihost.h, in preparation to add RISC-V support. Signed-off-by: Bin Meng --- Changes in v2: - new patch: "serial: earlycon-arm-semihost: Move smh_putc() variants in respective arch's semihost.h" arch/arm/include/asm/semihost.h | 23 ++++++++++++++++++++ arch/arm64/include/asm/semihost.h | 17 +++++++++++++++ drivers/tty/serial/earlycon-arm-semihost.c | 25 +--------------------- 3 files changed, 41 insertions(+), 24 deletions(-) create mode 100644 arch/arm/include/asm/semihost.h create mode 100644 arch/arm64/include/asm/semihost.h diff --git a/arch/arm/include/asm/semihost.h b/arch/arm/include/asm/semihost.h new file mode 100644 index 000000000000..c33cb5124376 --- /dev/null +++ b/arch/arm/include/asm/semihost.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2012 ARM Ltd. + * Author: Marc Zyngier + * + * Adapted for ARM and earlycon: + * Copyright (C) 2014 Linaro Ltd. + * Author: Rob Herring + */ + +#ifdef CONFIG_THUMB2_KERNEL +#define SEMIHOST_SWI "0xab" +#else +#define SEMIHOST_SWI "0x123456" +#endif + +static inline void smh_putc(struct uart_port *port, unsigned char c) +{ + asm volatile("mov r1, %0\n" + "mov r0, #3\n" + "svc " SEMIHOST_SWI "\n" + : : "r" (&c) : "r0", "r1", "memory"); +} diff --git a/arch/arm64/include/asm/semihost.h b/arch/arm64/include/asm/semihost.h new file mode 100644 index 000000000000..9e56d38fe5fd --- /dev/null +++ b/arch/arm64/include/asm/semihost.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2012 ARM Ltd. + * Author: Marc Zyngier + * + * Adapted for ARM and earlycon: + * Copyright (C) 2014 Linaro Ltd. + * Author: Rob Herring + */ + +static inline void smh_putc(struct uart_port *port, unsigned char c) +{ + asm volatile("mov x1, %0\n" + "mov x0, #3\n" + "hlt 0xf000\n" + : : "r" (&c) : "x0", "x1", "memory"); +} diff --git a/drivers/tty/serial/earlycon-arm-semihost.c b/drivers/tty/serial/earlycon-arm-semihost.c index fcdec5f42376..e4692a8433f9 100644 --- a/drivers/tty/serial/earlycon-arm-semihost.c +++ b/drivers/tty/serial/earlycon-arm-semihost.c @@ -11,30 +11,7 @@ #include #include #include - -#ifdef CONFIG_THUMB2_KERNEL -#define SEMIHOST_SWI "0xab" -#else -#define SEMIHOST_SWI "0x123456" -#endif - -/* - * Semihosting-based debug console - */ -static void smh_putc(struct uart_port *port, unsigned char c) -{ -#ifdef CONFIG_ARM64 - asm volatile("mov x1, %0\n" - "mov x0, #3\n" - "hlt 0xf000\n" - : : "r" (&c) : "x0", "x1", "memory"); -#else - asm volatile("mov r1, %0\n" - "mov r0, #3\n" - "svc " SEMIHOST_SWI "\n" - : : "r" (&c) : "r0", "r1", "memory"); -#endif -} +#include static void smh_write(struct console *con, const char *s, unsigned n) { From patchwork Wed Dec 7 13:53:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 30859 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp197480wrr; Wed, 7 Dec 2022 06:01:27 -0800 (PST) X-Google-Smtp-Source: AA0mqf42V01bGdRP3Ot+7vfDD2GNMJy+cmnZ2Y2Ywg8E5yFNv8C+DXTpMA8NEf6A8kwfSXqsxxc3 X-Received: by 2002:a17:903:50c:b0:189:6de9:deb9 with SMTP id jn12-20020a170903050c00b001896de9deb9mr55368109plb.153.1670421687175; Wed, 07 Dec 2022 06:01:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670421687; cv=none; d=google.com; s=arc-20160816; b=D/MCBIPkzLWM6YJ2ZSZRuI08uSRS/6Lzaf6tEwLGT5eH2jnWdu1kmGogQVYnuQurvT J0GdW9TgHJ5NoXzHYu49AJqlqiqke4MTCtx4ySUWsbyO9p1kzsW5KsppmDdJgsiJVs5X mNQq2dc9qgk7IARQIcWmJNeYlm4FfkFFOQXXM5Awo4j7B5XvPs+jRRaAV6clplwNHHSF 0WUZ7jfEaWD9yYfghgjH/6W7qdrp0NanKUloUATrR4twqv+aCjvRMZTQyA3k6zOtbb9L wyLEfQSj3I04IotEqYKWH4wQcdde8RgBVI1oQBbwQ+N2cQb0saUIZLvnHb/Fg83jj9PW l6tA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:feedback-id:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=y02MrK+zGej3axV3FsF8wu3zeYmNOFZlTihZ+PXyelo=; b=sxyeeD5vzmz3vgKjXxfCeqCTqFb0y8XQTK82b/tS5GnzI7RdcNqI5e0iy+xWf9QWC4 vLwM6t5oMb4AgFwRrK+tVl7iBYXYplAcTuTsA7pkXsDClcnHZzvHIu1UwcYVaHMXZCHO pE9Z+NtTUBwyyg5jrVkonReicjg4WvyU9CmyNaaFuJ4idKr2QrVxyvou15liT6sohOXG OmCqSM5mYxG6rqaYsCELXoH1Q1NotgYSZkHZzfDxdoRenRY3ja9tQ9KBWnvD9vvON+JK fA7yPDm2g5hHFUQrEXvm8KLxisB+YDTb/L9sj1vOUXAyyfDDSOBdZomWGxlAGUcXsmo3 4e1A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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( [111.196.135.79]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 07 Dec 2022 21:53:57 +0800 (CST) X-QQ-SSF: 01200000002000B0B000B00A0000000 X-QQ-FEAT: xwvWJGGFd7MwyO0I/Q6cO3SN87cXTA0Qqfh8HCCQSS6fqMBr/qkBzS+Hb4sLp RIF6DZbbbporXK5SG5F4L4GnHn3cPJgPb5h4J9lKGr5wkCAxIZIeU5807depEIkwOLe/Mvy w0fF2c1Xl1ux4LFQLywy9e9/clKPMiR6ZcYxicJ41cKAl3Xv6ZkiqQ6IruvUZk/stFlQJH8 iJdiwmmZOrFZdI9SL+AxAuRudDrkCSZ1BMsWKQjKaEPDbO972J8msrOerMwffpes+NXzixA M0hzvtwl06PkTeG8l2CIIQ8YzQIf4d5qZW2xX3RNckdIF9+X7lJdOdEAGAlDSChORGQtg0r FGahlUmropJkxzJ1wNuBcRJWrhJuK4yhfdO3fVCeNsWeoQ6Ohn9G58xYSpL8A== X-QQ-GoodBg: 0 From: Bin Meng To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org Cc: Albert Ou , Greg Kroah-Hartman , Jiri Slaby , Palmer Dabbelt , Paul Walmsley Subject: [PATCH v2 2/3] riscv: Implement semihost.h for earlycon semihost driver Date: Wed, 7 Dec 2022 21:53:51 +0800 Message-Id: <20221207135352.592556-2-bmeng@tinylab.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221207135352.592556-1-bmeng@tinylab.org> References: <20221207135352.592556-1-bmeng@tinylab.org> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:tinylab.org:qybglogicsvr:qybglogicsvr3 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H2, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751564090732013859?= X-GMAIL-MSGID: =?utf-8?q?1751564090732013859?= Per RISC-V semihosting spec [1], implement semihost.h for the existing Arm semihosting earlycon driver to work on RISC-V. [1] https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc Signed-off-by: Bin Meng --- Changes in v2: - Move the RISC-V implementation to semihost.h arch/riscv/include/asm/semihost.h | 19 +++++++++++++++++++ drivers/tty/serial/Kconfig | 2 +- 2 files changed, 20 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/include/asm/semihost.h diff --git a/arch/riscv/include/asm/semihost.h b/arch/riscv/include/asm/semihost.h new file mode 100644 index 000000000000..886f21d7a476 --- /dev/null +++ b/arch/riscv/include/asm/semihost.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022 tinylab.org + * Author: Bin Meng + */ + +static inline void smh_putc(struct uart_port *port, unsigned char c) +{ + asm volatile("addi a1, %0, 0\n" + "addi a0, zero, 3\n" + ".balign 16\n" + ".option push\n" + ".option norvc\n" + "slli zero, zero, 0x1f\n" + "ebreak\n" + "srai zero, zero, 0x7\n" + ".option pop\n" + : : "r" (&c) : "a0", "a1", "memory"); +} diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 434f83168546..e94d1265151c 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -75,7 +75,7 @@ config SERIAL_AMBA_PL011_CONSOLE config SERIAL_EARLYCON_ARM_SEMIHOST bool "Early console using ARM semihosting" - depends on ARM64 || ARM + depends on ARM64 || ARM || RISCV select SERIAL_CORE select SERIAL_CORE_CONSOLE select SERIAL_EARLYCON From patchwork Wed Dec 7 13:53:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 30856 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp197218wrr; Wed, 7 Dec 2022 06:01:05 -0800 (PST) X-Google-Smtp-Source: AA0mqf7CBxBUssS1vBUjVbdKvQaiiNWtcvA/hjiO08Xm3CtIEfg/md/Ia1ioOZijmGMpXndSRKN+ X-Received: by 2002:a17:90a:540f:b0:219:e43b:7eed with SMTP id z15-20020a17090a540f00b00219e43b7eedmr12515848pjh.103.1670421664142; Wed, 07 Dec 2022 06:01:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670421664; cv=none; d=google.com; s=arc-20160816; b=Hz1XnVBs7CQUX4WwqjA2D+ElbI1YkD8U9YWCb7ESQAiNi38k8qhYw5mfer5eoT5lBZ r3/QIRdbVXH9iimKRRP8AUGg4o9FhBxThGSv26h3fl/ibERmlgN1byYzr9Aly86nwSP8 daC+EmOorP+66EBO4bK8b0Jt7xcL+Tyiag/iqgdVjVzztXescnTwRcKiSVwMFUVsBOlK 6U+Tw+HV1YwRWd8g/DOB41qDwf4FPipSe54ff8HcwRfFERK3DyI91feDib+IqTM1CrSN szwccRiDO4ZKhw2YGebhNhMD0Z8EXC2KPU+7OiodHk97CGjspYAcOWL163RTXruhaX+1 B0HA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:feedback-id:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=s6ALYND/IPX0ndZNPugEnkt+c8H7XD+usIJXgCmz6HQ=; b=cPPq93wek1P/MA4/VzNP7VjqEKVAn5ExaIYVRZoBSHaCv/EDHExV83O1TSnKZlZnpJ Fv2gl9gE3TY864lH6RlEcPJYKlEl7aBo3r3vfh+OmD9S2+hkgNNbFkTu6kysBkz5eEL1 tYB4IAntKryKCFK71EfCEIVZS6Cm+VuEeYSIi39U2xp9vNM0msKsnHYWEaa/UUuWdZet D53PQ7cGgvz1djhAlmQutTb1sS1yiwIylPpDV3JyI+zy6wlnPJLpNZvgeiJ+bADYXBMr s4OY/6OK7TQVWH+stejOSemSg1dUcH1EAxBHddeXTaYmtEU/pn/wOguMlAMjik4z0dQv MqNQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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( [111.196.135.79]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 07 Dec 2022 21:53:59 +0800 (CST) X-QQ-SSF: 01200000002000B0B000B00A0000000 X-QQ-FEAT: WfQrrMZtGtFaBhCIjFkwlouFogiRdBICx5npfjqOayIRbX/Flh8LzJ93MYCFh 36X35vAPGzUK6kjShIP7otSDF0ZW6nd1bkmmFzHHzjDrZYl2OsqoTk0Zz7hFXdq3Dw19JIB kKjISittyAUaHDPTnXlZtLYNZgmDRE6fon+hkNT/Lp8E/T09fUcoErU3Js7KONhTPwYzOWQ ai7k+ZIRsSQgaurOY1zU3WIdrNIbh2qgEigV/9325z9PywKyNrTwOmUq+E80jl/rpsoEzwo nfnv+NSCaYIX8vdLu8G7yMR/sMKJb7f9Ka/F5NyWt9vgcsc1uaHibUBnFqzNQr8yob5P7FB 30Z9Ilrkk8MZVXrBeZCLIGbhzumN94YTX34evrXQ6lxCwHpwnM= X-QQ-GoodBg: 0 From: Bin Meng To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org Cc: Greg Kroah-Hartman , Jiri Slaby Subject: [PATCH v2 3/3] serial: Rename earlycon semihost driver Date: Wed, 7 Dec 2022 21:53:52 +0800 Message-Id: <20221207135352.592556-3-bmeng@tinylab.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221207135352.592556-1-bmeng@tinylab.org> References: <20221207135352.592556-1-bmeng@tinylab.org> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:tinylab.org:qybglogicsvr:qybglogicsvr3 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H2, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751564066705026375?= X-GMAIL-MSGID: =?utf-8?q?1751564066705026375?= Now that earlycon semihost driver works on RISC-V too, let's use a much more generic name for the driver. Signed-off-by: Bin Meng --- (no changes since v1) drivers/tty/serial/Kconfig | 12 ++++++------ drivers/tty/serial/Makefile | 2 +- .../{earlycon-arm-semihost.c => earlycon-semihost.c} | 0 3 files changed, 7 insertions(+), 7 deletions(-) rename drivers/tty/serial/{earlycon-arm-semihost.c => earlycon-semihost.c} (100%) diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index e94d1265151c..a3779472edf6 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -73,17 +73,17 @@ config SERIAL_AMBA_PL011_CONSOLE your boot loader (lilo or loadlin) about how to pass options to the kernel at boot time.) -config SERIAL_EARLYCON_ARM_SEMIHOST - bool "Early console using ARM semihosting" +config SERIAL_EARLYCON_SEMIHOST + bool "Early console using Arm compatible semihosting" depends on ARM64 || ARM || RISCV select SERIAL_CORE select SERIAL_CORE_CONSOLE select SERIAL_EARLYCON help - Support for early debug console using ARM semihosting. This enables - the console before standard serial driver is probed. This is enabled - with "earlycon=smh" on the kernel command line. The console is - enabled when early_param is processed. + Support for early debug console using Arm compatible semihosting. + This enables the console before standard serial driver is probed. + This is enabled with "earlycon=smh" on the kernel command line. + The console is enabled when early_param is processed. config SERIAL_EARLYCON_RISCV_SBI bool "Early console using RISC-V SBI" diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index 238a9557b487..cd9afd9e3018 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -6,7 +6,7 @@ obj-$(CONFIG_SERIAL_CORE) += serial_core.o obj-$(CONFIG_SERIAL_EARLYCON) += earlycon.o -obj-$(CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST) += earlycon-arm-semihost.o +obj-$(CONFIG_SERIAL_EARLYCON_SEMIHOST) += earlycon-semihost.o obj-$(CONFIG_SERIAL_EARLYCON_RISCV_SBI) += earlycon-riscv-sbi.o # These Sparc drivers have to appear before others such as 8250 diff --git a/drivers/tty/serial/earlycon-arm-semihost.c b/drivers/tty/serial/earlycon-semihost.c similarity index 100% rename from drivers/tty/serial/earlycon-arm-semihost.c rename to drivers/tty/serial/earlycon-semihost.c