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Signed-off-by: Abel Vesa Reviewed-by: Krzysztof Kozlowski --- include/dt-bindings/clock/qcom,rpmh.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/qcom,rpmh.h b/include/dt-bindings/clock/qcom,rpmh.h index 0a7d1be0d124..f3e0288420ce 100644 --- a/include/dt-bindings/clock/qcom,rpmh.h +++ b/include/dt-bindings/clock/qcom,rpmh.h @@ -33,5 +33,7 @@ #define RPMH_HWKM_CLK 24 #define RPMH_QLINK_CLK 25 #define RPMH_QLINK_CLK_A 26 +#define RPMH_CXO_PAD_CLK 27 +#define RPMH_CXO_PAD_CLK_A 28 #endif From patchwork Tue Dec 6 22:45:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 30525 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp3087539wrr; Tue, 6 Dec 2022 14:47:54 -0800 (PST) X-Google-Smtp-Source: AA0mqf4CGOWYbtDGEFui1puFCfTK1STnxHsmFCyIr7mrfKjrxKd4YI/1Fl+cnXt9u9sum9ZTwB11 X-Received: by 2002:a65:4688:0:b0:477:7aee:a464 with SMTP id h8-20020a654688000000b004777aeea464mr67404020pgr.595.1670366874304; Tue, 06 Dec 2022 14:47:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670366874; cv=none; d=google.com; s=arc-20160816; b=AuVW2i3iYaA/fEmUFWYpFmPGNTzPr4huvsUk6fx60ePxSODgY5Ul4ejgU+BeEC6z1A YOUAPGeqw115VYM64G8GyPDyhmmYtuMK1vk7uxMLusl08/caENsRtYPDeX1l9LOHfL/8 FRlq0bHBpU7IqbThMfKswhvER7W6W1s470+59hoOO9gr2CErLG+flwLVt3dQ/ye1QjZm 2h5n6GhFj2PqRDbYkwihOmMRjLeavzaA4d7sPMNmaav2seOWIN7qzlC1VUassOmEGbqf OZMa8swAHbd1q6mUc8j3/bDrRgBZkWyBcDRd152qICTsIH7yFdp4DY79mcVhu5ewMm09 YbXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tNI2i3/QTr9mwnzcqdEPuyaMkTpSlzmqI4PslyM1ul8=; b=IReaPy5LfkHovIgyu0Rh2SERLZaJeOus4nCHHLak8sOg09N5rS7bnS9vBrULVGS5uL hhxkMBtTudDUzWCZfkgZnBMhZvuJchAQuAhbivGnzRVGw71xJhKGBX7ei0BsgswScBO2 NRf+wCA+HY2qaJfs3DPFUnKtIrqHaaCJdwAoD/LHmPuNTigByLfa430HqVTnLm6nDwQT yj2gc6b7DdeV+tCAl3F00iVglTbePO755VPLpuLJ3nLzj9dNFBWfAYsfLyhR0pQnSwqN Rnh1zDbgQILi3o++5EizRuYtM4UDXdbrm5YzaZaMoxVsfgg2EtU5ZY17Hf38q3v6EKTd 2M0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iTwAOWgL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Abel Vesa Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,sm8550-tcsr.yaml | 55 +++++++++++++++++++ include/dt-bindings/clock/qcom,sm8550-tcsr.h | 18 ++++++ 2 files changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml create mode 100644 include/dt-bindings/clock/qcom,sm8550-tcsr.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml new file mode 100644 index 000000000000..2b72ab82041a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8550-tcsr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm TCSR Clock Controller on SM8550 + +maintainers: + - Bjorn Andersson + +description: | + Qualcomm TCSR clock control module provides the clocks, resets and + power domains on SM8550 + + See also:: include/dt-bindings/clock/qcom,sm8550-tcsr.h + +properties: + compatible: + items: + - const: qcom,sm8550-tcsr + - const: syscon + + clocks: + items: + - description: TCXO pad clock + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | + #include + + clock-controller@1fc0000 { + compatible = "qcom,sm8550-tcsr", "syscon"; + reg = <0x1fc0000 0x30000>; + clocks = <&rpmhcc RPMH_CXO_PAD_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +... diff --git a/include/dt-bindings/clock/qcom,sm8550-tcsr.h b/include/dt-bindings/clock/qcom,sm8550-tcsr.h new file mode 100644 index 000000000000..091cb76f953a --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8550-tcsr.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8550_H +#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8550_H + +/* TCSR CC clocks */ +#define TCSR_PCIE_0_CLKREF_EN 0 +#define TCSR_PCIE_1_CLKREF_EN 1 +#define TCSR_UFS_CLKREF_EN 2 +#define TCSR_UFS_PAD_CLKREF_EN 3 +#define TCSR_USB2_CLKREF_EN 4 +#define TCSR_USB3_CLKREF_EN 5 + +#endif From patchwork Tue Dec 6 22:45:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 30528 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp3087997wrr; Tue, 6 Dec 2022 14:49:20 -0800 (PST) X-Google-Smtp-Source: AA0mqf5LgWgIR03IwQ5bFeZxzT2xrTP84pcs4lT82mSAV7p+LzqX2yj/OAndDuj83GQTHmL+JyYh X-Received: by 2002:a63:f453:0:b0:478:d3a8:6ba5 with SMTP id p19-20020a63f453000000b00478d3a86ba5mr6761944pgk.619.1670366959642; Tue, 06 Dec 2022 14:49:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670366959; cv=none; d=google.com; s=arc-20160816; b=Y6+7RZlQYGke/GEacspM30nPghEi3oF/tYrOeekvqKPOHElpteisJ8qAyTQil1HuSR QEzQhlr6C0A/Y6WfJdGLzYvGVqV/d+D3Y9xuUTtGW3O3ec3wAl58xubb58vGigkodoo9 CZA9481Tu1n2etqIQsf+iUYdZikXLWp3cnNtCM5l4vVfqjDI/tJCq1+MWUsCFF5NQcEA 2jGL0E7EDmsBAJ+l6KaRRL8AZIGABF+LRUobM+VsaOWIyqqn0xDdFf6mL4GscDjvKjqE Klew0Ua9GzDzaLyAhUw0Yhl8C8KroLLTwIrK+GpPn3gZ0q3NwFOsVcH8iYtv5GNQJXVb fqQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=BhLdyy64MSy62j2GfoCPYL31V7FQmGy5yzQrHHdIKxE=; b=CJkc1HsFYxQpNTyr/m0Q5U1RL7N2G6yslefUlVFSnapfSYM5X8/X7A02Ght0VQzZ/U IO8hH0MpZuW2jHtrEenAvwkDWeM+gXHgdUEPj3qFKJsfeEB3+nzZaUeRjsL4Dy+o4RFt esYsam40bg5bm4M9yiWE0Qw7sVyFQzL5h64DLI0N46uxC1Cv3MXDxONL4wuBKRa5KHY2 xY9EJ9wSAWevefqa7RdDB8x7jqKSxijJI+oua7ZMDwOa9ehL2pfVkch9ndiwUmVhsPNI wmblVZTFYg/KRIrk9ReeYZH8nzTLri11tDmMhJpWivtKGFddPaQY6hAnSL/mychDWgYq bjFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lBCtzop+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Abel Vesa Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml index fccb91e78e49..b405da7700be 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -31,6 +31,7 @@ properties: - qcom,sm8250-rpmh-clk - qcom,sm8350-rpmh-clk - qcom,sm8450-rpmh-clk + - qcom,sm8550-rpmh-clk clocks: maxItems: 1 From patchwork Tue Dec 6 22:45:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 30526 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp3087682wrr; Tue, 6 Dec 2022 14:48:25 -0800 (PST) X-Google-Smtp-Source: AA0mqf4Qi2NUi4crrqE1MyozcuZfLukv/rWGQa2k532ta+mbXCdTktLp2c2SP36keEpal4sEvbHf X-Received: by 2002:a63:ae01:0:b0:478:936:3380 with SMTP id q1-20020a63ae01000000b0047809363380mr42797688pgf.266.1670366905070; Tue, 06 Dec 2022 14:48:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670366905; cv=none; d=google.com; s=arc-20160816; b=qmXHPzZ8bM0nPfD3xjXLPdNzRmrWEV36WGOL9QUrBEG8O0Y/N/jEhIRHkRt3+oHyWz b1MZN6PaGa4AU7Ko63jJ0QBBrFvgCAc1qVMf5eMtPdvAQcIBGnGjvWGv5ntlA/6IyTX+ 58wvSImQ1MR8JmSuMyWTXYQJPyjN0d5keZyCL4Stigoqlgurs5PBngFQU6VX73+ABsWw 0P0BzM3NEJGtueWHiCR/RM9qHguZkWSNBPWuPfwZppFxmjNKaW8aeRh3ngKPQWxG3UO4 dXB7kXnR6hRiv6iui4JL/B0KmycquugaqdcxB1HPyLI5RW3hbD2ayQo1dzKXTwG3xeok KMKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=xGLwUiqnWNNCSh7SfaJVMgmwcN3tXBqQdd3/EujPmbQ=; b=xqMCfOLZVchKv6lPsJCakyitkKkjFjtU9xbmFfXGT0Fv45aPWuOFkMoIQNMkFZG2XK XBU6g10iwd7V60lL8/9pzBboUwQWPhntQyrIP07AtgoRMby3iZ6vrS+EmbTjnc3QiO6o z/+2Xqdo6FgXXgPrcQrAFZzv6IiKj/v/jr0uszwftMUJXiKumuRUDZmcTZIk9qLamLre nN9BRG2V5CCuLXNfnU6lGKnMNn4MScVHYKce1Q/QnEFemj6NEya25JylNYeK8+fil41n og6ZncYWXqqztCFEh5Cl6Z3c7hVg0hajDpHHOqezQMKTVXk/AiepZ62GFIY/luZxcZd2 ab1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=USNBxSGK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id p1-20020a635b01000000b00477b64d8e5csi19011076pgb.160.2022.12.06.14.48.11; Tue, 06 Dec 2022 14:48:25 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=USNBxSGK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229536AbiLFWpk (ORCPT + 99 others); Tue, 6 Dec 2022 17:45:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37950 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229774AbiLFWp2 (ORCPT ); Tue, 6 Dec 2022 17:45:28 -0500 Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 933B61C121 for ; Tue, 6 Dec 2022 14:45:26 -0800 (PST) Received: by mail-ed1-x533.google.com with SMTP id s5so22424769edc.12 for ; Tue, 06 Dec 2022 14:45:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xGLwUiqnWNNCSh7SfaJVMgmwcN3tXBqQdd3/EujPmbQ=; b=USNBxSGKBn5FbHuXELI8G7fD4ra27dG0EDBfWENVl3aOtZ1V29g1iNZttBlLKDi7yB k57VcrNQNxkQPSou/PO+x5oUExqj+06Ga7LoyFo/UqT2BxkV8O832Gco9Ms9K9Rm8kRn DMy5hc7uX44oQC22yYVKkIhI4XKLmxiJh7tXCOus4TTKlTwygrCCwyFUlXAj/zHSD/JR qa2rNeRyglgUeBcXFzVxZ+RFbxJzSpaXYdYCn2/e4qbXUkvk8YpfXA4JBwektxcAcYIH V8pdn6t2RO+gqO8ZaWn/SrJJwIhBFyL3vQCAKiqXM6pP7AgDuwmno/MFeBr8bBSUq/td WgTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xGLwUiqnWNNCSh7SfaJVMgmwcN3tXBqQdd3/EujPmbQ=; b=1sgg25qg/cSW0RFt0G+f4ohXbUeiJO72XNipGTk35/yQk+aD822F8QxyUSN3mklhTM vcG059ng30OV1L59QQ+cF5udF2PaejDp9qk9PYR4aJkuNFuvuS97y6KkDmB/0c7Oog5g r9RG1B1hBw+5rPk9T5dzph9rsortu3Bk4abzkqt6B4TdyrNOU2R1/52SzAxTyiOvZJzw ipRh4WwJmrGwnErmjaPf/I/GA7OtCWuMIhge54gPTthP74VF5nbwfbdUUVJbHu4tQVpv ys28W6vFhClWnYs34dwomJivuLpio0Nd8MksyUClo43KuWZbdaN+TAn/UYeehPB4TOFS OZKA== X-Gm-Message-State: ANoB5pkefc5Iu55lPsl8RrFhrHF2klcu2EUAmmfCwMFT8L/H5OFggR2a tifQ88G5uX44gv99TK2Y9cQfvA== X-Received: by 2002:a05:6402:3c1:b0:46b:2d74:d970 with SMTP id t1-20020a05640203c100b0046b2d74d970mr36829012edw.138.1670366725127; Tue, 06 Dec 2022 14:45:25 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id r17-20020a1709061bb100b007c0985aa6b0sm7820772ejg.191.2022.12.06.14.45.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Dec 2022 14:45:24 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Mike Turquette , Stephen Boyd , Dmitry Baryshkov , Rob Herring , Krzysztof Kozlowski Cc: Linux Kernel Mailing List , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v6 4/5] clk: qcom: rpmh: Add support for SM8550 rpmh clocks Date: Wed, 7 Dec 2022 00:45:14 +0200 Message-Id: <20221206224515.1495457-5-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221206224515.1495457-1-abel.vesa@linaro.org> References: <20221206224515.1495457-1-abel.vesa@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751506648042019207?= X-GMAIL-MSGID: =?utf-8?q?1751506648042019207?= Adds the RPMH clocks present in SM8550 SoC. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/clk-rpmh.c | 110 +++++++++++++++++++++++++++++------- 1 file changed, 90 insertions(+), 20 deletions(-) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 2c2ef4b6d130..ce81c76ed0fd 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -130,6 +130,34 @@ static DEFINE_MUTEX(rpmh_clk_lock); }, \ } +#define DEFINE_CLK_FIXED_FACTOR(_name, _parent_name, _div) \ + static struct clk_fixed_factor clk_fixed_factor##_##_name = { \ + .mult = 1, \ + .div = _div, \ + .hw.init = &(struct clk_init_data){ \ + .ops = &clk_fixed_factor_ops, \ + .name = #_name, \ + .parent_data = &(const struct clk_parent_data){ \ + .fw_name = #_parent_name, \ + .name = #_parent_name, \ + }, \ + .num_parents = 1, \ + }, \ + }; \ + static struct clk_fixed_factor clk_fixed_factor##_##_name##_ao = { \ + .mult = 1, \ + .div = _div, \ + .hw.init = &(struct clk_init_data){ \ + .ops = &clk_fixed_factor_ops, \ + .name = #_name "_ao", \ + .parent_data = &(const struct clk_parent_data){ \ + .fw_name = #_parent_name "_ao", \ + .name = #_parent_name "_ao", \ + }, \ + .num_parents = 1, \ + }, \ + } + static inline struct clk_rpmh *to_clk_rpmh(struct clk_hw *_hw) { return container_of(_hw, struct clk_rpmh, hw); @@ -345,6 +373,8 @@ DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 2); DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 4); DEFINE_CLK_RPMH_ARC(qlink, "qphy.lvl", 0x1, 4); +DEFINE_CLK_FIXED_FACTOR(bi_tcxo_div2, bi_tcxo, 2); + DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a2, "lnbclka1", 2); DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a2, "lnbclka2", 2); DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a2, "lnbclka3", 2); @@ -366,6 +396,16 @@ DEFINE_CLK_RPMH_VRM(rf_clk2, _d, "rfclkd2", 1); DEFINE_CLK_RPMH_VRM(rf_clk3, _d, "rfclkd3", 1); DEFINE_CLK_RPMH_VRM(rf_clk4, _d, "rfclkd4", 1); +DEFINE_CLK_RPMH_VRM(clk1, _a1, "clka1", 1); +DEFINE_CLK_RPMH_VRM(clk2, _a1, "clka2", 1); +DEFINE_CLK_RPMH_VRM(clk3, _a1, "clka3", 1); +DEFINE_CLK_RPMH_VRM(clk4, _a1, "clka4", 1); +DEFINE_CLK_RPMH_VRM(clk5, _a1, "clka5", 1); + +DEFINE_CLK_RPMH_VRM(clk6, _a2, "clka6", 2); +DEFINE_CLK_RPMH_VRM(clk7, _a2, "clka7", 2); +DEFINE_CLK_RPMH_VRM(clk8, _a2, "clka8", 2); + DEFINE_CLK_RPMH_VRM(div_clk1, _div2, "divclka1", 2); DEFINE_CLK_RPMH_BCM(ce, "CE0"); @@ -576,6 +616,33 @@ static const struct clk_rpmh_desc clk_rpmh_sm8450 = { .num_clks = ARRAY_SIZE(sm8450_rpmh_clocks), }; +static struct clk_hw *sm8550_rpmh_clocks[] = { + [RPMH_CXO_PAD_CLK] = &clk_rpmh_bi_tcxo_div2.hw, + [RPMH_CXO_PAD_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, + [RPMH_CXO_CLK] = &clk_fixed_factor_bi_tcxo_div2.hw, + [RPMH_CXO_CLK_A] = &clk_fixed_factor_bi_tcxo_div2_ao.hw, + [RPMH_LN_BB_CLK1] = &clk_rpmh_clk6_a2.hw, + [RPMH_LN_BB_CLK1_A] = &clk_rpmh_clk6_a2_ao.hw, + [RPMH_LN_BB_CLK2] = &clk_rpmh_clk7_a2.hw, + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_clk7_a2_ao.hw, + [RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a2.hw, + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a2_ao.hw, + [RPMH_RF_CLK1] = &clk_rpmh_clk1_a1.hw, + [RPMH_RF_CLK1_A] = &clk_rpmh_clk1_a1_ao.hw, + [RPMH_RF_CLK2] = &clk_rpmh_clk2_a1.hw, + [RPMH_RF_CLK2_A] = &clk_rpmh_clk2_a1_ao.hw, + [RPMH_RF_CLK3] = &clk_rpmh_clk3_a1.hw, + [RPMH_RF_CLK3_A] = &clk_rpmh_clk3_a1_ao.hw, + [RPMH_RF_CLK4] = &clk_rpmh_clk4_a1.hw, + [RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a1_ao.hw, + [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_sm8550 = { + .clks = sm8550_rpmh_clocks, + .num_clks = ARRAY_SIZE(sm8550_rpmh_clocks), +}; + static struct clk_hw *sc7280_rpmh_clocks[] = { [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, @@ -683,29 +750,31 @@ static int clk_rpmh_probe(struct platform_device *pdev) name = hw_clks[i]->init->name; - rpmh_clk = to_clk_rpmh(hw_clks[i]); - res_addr = cmd_db_read_addr(rpmh_clk->res_name); - if (!res_addr) { - dev_err(&pdev->dev, "missing RPMh resource address for %s\n", - rpmh_clk->res_name); - return -ENODEV; - } + if (hw_clks[i]->init->ops != &clk_fixed_factor_ops) { + rpmh_clk = to_clk_rpmh(hw_clks[i]); + res_addr = cmd_db_read_addr(rpmh_clk->res_name); + if (!res_addr) { + dev_err(&pdev->dev, "missing RPMh resource address for %s\n", + rpmh_clk->res_name); + return -ENODEV; + } - data = cmd_db_read_aux_data(rpmh_clk->res_name, &aux_data_len); - if (IS_ERR(data)) { - ret = PTR_ERR(data); - dev_err(&pdev->dev, - "error reading RPMh aux data for %s (%d)\n", - rpmh_clk->res_name, ret); - return ret; - } + data = cmd_db_read_aux_data(rpmh_clk->res_name, &aux_data_len); + if (IS_ERR(data)) { + ret = PTR_ERR(data); + dev_err(&pdev->dev, + "error reading RPMh aux data for %s (%d)\n", + rpmh_clk->res_name, ret); + return ret; + } - /* Convert unit from Khz to Hz */ - if (aux_data_len == sizeof(*data)) - rpmh_clk->unit = le32_to_cpu(data->unit) * 1000ULL; + /* Convert unit from Khz to Hz */ + if (aux_data_len == sizeof(*data)) + rpmh_clk->unit = le32_to_cpu(data->unit) * 1000ULL; - rpmh_clk->res_addr += res_addr; - rpmh_clk->dev = &pdev->dev; + rpmh_clk->res_addr += res_addr; + rpmh_clk->dev = &pdev->dev; + } ret = devm_clk_hw_register(&pdev->dev, hw_clks[i]); if (ret) { @@ -741,6 +810,7 @@ static const struct of_device_id clk_rpmh_match_table[] = { { .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250}, { .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350}, { .compatible = "qcom,sm8450-rpmh-clk", .data = &clk_rpmh_sm8450}, + { .compatible = "qcom,sm8550-rpmh-clk", .data = &clk_rpmh_sm8550}, { .compatible = "qcom,sc7280-rpmh-clk", .data = &clk_rpmh_sc7280}, { } }; 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Add clock driver for it. This patch is based on initial code downstream. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/Kconfig | 7 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/tcsrcc-sm8550.c | 192 +++++++++++++++++++++++++++++++ 3 files changed, 200 insertions(+) create mode 100644 drivers/clk/qcom/tcsrcc-sm8550.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 70d43f0a8919..b9f5505d68f0 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -797,6 +797,13 @@ config SM_GPUCC_8350 Say Y if you want to support graphics controller devices and functionality such as 3D graphics. +config SM_TCSRCC_8550 + tristate "SM8550 TCSR Clock Controller" + select QCOM_GDSC + help + Support for the TCSR clock controller on SM8550 devices. + Say Y if you want to use peripheral devices such as SD/UFS. + config SM_VIDEOCC_8150 tristate "SM8150 Video Clock Controller" select SM_GCC_8150 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index f18c446a97ea..f5ce429c724c 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -112,6 +112,7 @@ obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o +obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o diff --git a/drivers/clk/qcom/tcsrcc-sm8550.c b/drivers/clk/qcom/tcsrcc-sm8550.c new file mode 100644 index 000000000000..2c67ee71c196 --- /dev/null +++ b/drivers/clk/qcom/tcsrcc-sm8550.c @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "reset.h" + +enum { + DT_BI_TCXO_PAD, +}; + +static struct clk_branch tcsr_pcie_0_clkref_en = { + .halt_reg = 0x15100, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x15100, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_pcie_0_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_pcie_1_clkref_en = { + .halt_reg = 0x15114, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x15114, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_pcie_1_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_ufs_clkref_en = { + .halt_reg = 0x15110, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x15110, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_ufs_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_ufs_pad_clkref_en = { + .halt_reg = 0x15104, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x15104, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_ufs_pad_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb2_clkref_en = { + .halt_reg = 0x15118, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x15118, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_usb2_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb3_clkref_en = { + .halt_reg = 0x15108, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x15108, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_usb3_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *tcsr_cc_sm8550_clocks[] = { + [TCSR_PCIE_0_CLKREF_EN] = &tcsr_pcie_0_clkref_en.clkr, + [TCSR_PCIE_1_CLKREF_EN] = &tcsr_pcie_1_clkref_en.clkr, + [TCSR_UFS_CLKREF_EN] = &tcsr_ufs_clkref_en.clkr, + [TCSR_UFS_PAD_CLKREF_EN] = &tcsr_ufs_pad_clkref_en.clkr, + [TCSR_USB2_CLKREF_EN] = &tcsr_usb2_clkref_en.clkr, + [TCSR_USB3_CLKREF_EN] = &tcsr_usb3_clkref_en.clkr, +}; + +static const struct regmap_config tcsr_cc_sm8550_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x2f000, + .fast_io = true, +}; + +static const struct qcom_cc_desc tcsr_cc_sm8550_desc = { + .config = &tcsr_cc_sm8550_regmap_config, + .clks = tcsr_cc_sm8550_clocks, + .num_clks = ARRAY_SIZE(tcsr_cc_sm8550_clocks), +}; + +static const struct of_device_id tcsr_cc_sm8550_match_table[] = { + { .compatible = "qcom,sm8550-tcsr" }, + { } +}; +MODULE_DEVICE_TABLE(of, tcsr_cc_sm8550_match_table); + +static int tcsr_cc_sm8550_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &tcsr_cc_sm8550_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return qcom_cc_really_probe(pdev, &tcsr_cc_sm8550_desc, regmap); +} + +static struct platform_driver tcsr_cc_sm8550_driver = { + .probe = tcsr_cc_sm8550_probe, + .driver = { + .name = "tcsr_cc-sm8550", + .of_match_table = tcsr_cc_sm8550_match_table, + }, +}; + +static int __init tcsr_cc_sm8550_init(void) +{ + return platform_driver_register(&tcsr_cc_sm8550_driver); +} +subsys_initcall(tcsr_cc_sm8550_init); + +static void __exit tcsr_cc_sm8550_exit(void) +{ + platform_driver_unregister(&tcsr_cc_sm8550_driver); +} +module_exit(tcsr_cc_sm8550_exit); + +MODULE_DESCRIPTION("QTI TCSRCC SM8550 Driver"); +MODULE_LICENSE("GPL");