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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT059.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR08MB7802 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tamar Christina via Gcc-patches From: Tamar Christina Reply-To: Tamar Christina Cc: nd@arm.com, rguenther@suse.de Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1744760635683005487?= X-GMAIL-MSGID: =?utf-8?q?1744760635683005487?= Hi All, This adds a match.pd rule that can fold right shifts and bit_field_refs of integers into just a bit_field_ref by adjusting the offset and the size of the extract and adds an extend to the previous size. Concretely turns: #include unsigned int foor (uint32x4_t x) { return x[1] >> 16; } which used to generate: _1 = BIT_FIELD_REF ; _3 = _1 >> 16; into _4 = BIT_FIELD_REF ; _2 = (unsigned int) _4; I currently limit the rewrite to only doing it if the resulting extract is in a mode the target supports. i.e. it won't rewrite it to extract say 13-bits because I worry that for targets that won't have a bitfield extract instruction this may be a de-optimization. Bootstrapped Regtested on aarch64-none-linux-gnu, x86_64-pc-linux-gnu and no issues. Testcase are added in patch 2/2. Ok for master? Thanks, Tamar gcc/ChangeLog: * match.pd: Add bitfield and shift folding. --- inline copy of patch -- diff --git a/gcc/match.pd b/gcc/match.pd index 1d407414bee278c64c00d425d9f025c1c58d853d..b225d36dc758f1581502c8d03761544bfd499c01 100644 Signed-off-by: Andrew Pinski --- diff --git a/gcc/match.pd b/gcc/match.pd index 1d407414bee278c64c00d425d9f025c1c58d853d..b225d36dc758f1581502c8d03761544bfd499c01 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -7245,6 +7245,23 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) && ANY_INTEGRAL_TYPE_P (type) && ANY_INTEGRAL_TYPE_P (TREE_TYPE(@0))) (IFN_REDUC_PLUS_WIDEN @0))) +/* Canonicalize BIT_FIELD_REFS and shifts to BIT_FIELD_REFS. */ +(for shift (rshift) + op (plus) + (simplify + (shift (BIT_FIELD_REF @0 @1 @2) integer_pow2p@3) + (if (INTEGRAL_TYPE_P (type)) + (with { /* Can't use wide-int here as the precision differs between + @1 and @3. */ + unsigned HOST_WIDE_INT size = tree_to_uhwi (@1); + unsigned HOST_WIDE_INT shiftc = tree_to_uhwi (@3); + unsigned HOST_WIDE_INT newsize = size - shiftc; + tree nsize = wide_int_to_tree (bitsizetype, newsize); + tree ntype + = build_nonstandard_integer_type (newsize, 1); } + (if (ntype) + (convert:type (BIT_FIELD_REF:ntype @0 { nsize; } (op @2 @3)))))))) + (simplify (BIT_FIELD_REF (BIT_FIELD_REF @0 @1 @2) @3 @4) (BIT_FIELD_REF @0 @3 { const_binop (PLUS_EXPR, bitsizetype, @2, @4); })) --- a/gcc/match.pd +++ b/gcc/match.pd @@ -7245,6 +7245,23 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) && ANY_INTEGRAL_TYPE_P (type) && ANY_INTEGRAL_TYPE_P (TREE_TYPE(@0))) (IFN_REDUC_PLUS_WIDEN @0))) +/* Canonicalize BIT_FIELD_REFS and shifts to BIT_FIELD_REFS. */ +(for shift (rshift) + op (plus) + (simplify + (shift (BIT_FIELD_REF @0 @1 @2) integer_pow2p@3) + (if (INTEGRAL_TYPE_P (type)) + (with { /* Can't use wide-int here as the precision differs between + @1 and @3. */ + unsigned HOST_WIDE_INT size = tree_to_uhwi (@1); + unsigned HOST_WIDE_INT shiftc = tree_to_uhwi (@3); + unsigned HOST_WIDE_INT newsize = size - shiftc; + tree nsize = wide_int_to_tree (bitsizetype, newsize); + tree ntype + = build_nonstandard_integer_type (newsize, 1); } + (if (ntype) + (convert:type (BIT_FIELD_REF:ntype @0 { nsize; } (op @2 @3)))))))) + (simplify (BIT_FIELD_REF (BIT_FIELD_REF @0 @1 @2) @3 @4) (BIT_FIELD_REF @0 @3 { const_binop (PLUS_EXPR, bitsizetype, @2, @4); })) From patchwork Fri Sep 23 11:43:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tamar Christina X-Patchwork-Id: 1414 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5044:0:0:0:0:0 with SMTP id h4csp172196wrt; Fri, 23 Sep 2022 04:44:26 -0700 (PDT) X-Google-Smtp-Source: AMsMyM40Zg75VdqsordFByRCswbVW+pYpkTORLeaJiEhnQiBPKkPuUUzjn8tT+s2nPtKzDPfsphQ X-Received: by 2002:aa7:c458:0:b0:44e:9078:5712 with SMTP id n24-20020aa7c458000000b0044e90785712mr8186755edr.25.1663933466737; Fri, 23 Sep 2022 04:44:26 -0700 (PDT) Received: from sourceware.org (ip-8-43-85-97.sourceware.org. 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT018.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB4PR08MB9863 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_LOTSOFHASH, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tamar Christina via Gcc-patches From: Tamar Christina Reply-To: Tamar Christina Cc: Richard.Earnshaw@arm.com, nd@arm.com, richard.sandiford@arm.com, Marcus.Shawcroft@arm.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1744760698916619059?= X-GMAIL-MSGID: =?utf-8?q?1744760698916619059?= Hi All, Similar to the 1/2 patch but adds additional back-end specific folding for if the register sequence was created as a result of RTL optimizations. Concretely: #include unsigned int foor (uint32x4_t x) { return x[1] >> 16; } generates: foor: umov w0, v0.h[3] ret instead of foor: umov w0, v0.s[1] lsr w0, w0, 16 ret Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? Thanks, Tamar gcc/ChangeLog: * config/aarch64/aarch64.md (*si3_insn_uxtw): Split SHIFT into left and right ones. * config/aarch64/constraints.md (Usl): New. * config/aarch64/iterators.md (SHIFT_NL, LSHIFTRT): New. gcc/testsuite/ChangeLog: * gcc.target/aarch64/shift-read.c: New test. --- inline copy of patch -- diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index c333fb1f72725992bb304c560f1245a242d5192d..6aa1fb4be003f2027d63ac69fd314c2bbc876258 100644 --- diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index c333fb1f72725992bb304c560f1245a242d5192d..6aa1fb4be003f2027d63ac69fd314c2bbc876258 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -5493,7 +5493,7 @@ (define_insn "*rol3_insn" ;; zero_extend version of shifts (define_insn "*si3_insn_uxtw" [(set (match_operand:DI 0 "register_operand" "=r,r") - (zero_extend:DI (SHIFT_no_rotate:SI + (zero_extend:DI (SHIFT_arith:SI (match_operand:SI 1 "register_operand" "r,r") (match_operand:QI 2 "aarch64_reg_or_shift_imm_si" "Uss,r"))))] "" @@ -5528,6 +5528,60 @@ (define_insn "*rolsi3_insn_uxtw" [(set_attr "type" "rotate_imm")] ) +(define_insn "*si3_insn2_uxtw" + [(set (match_operand:DI 0 "register_operand" "=r,?r,r") + (zero_extend:DI (LSHIFTRT:SI + (match_operand:SI 1 "register_operand" "w,r,r") + (match_operand:QI 2 "aarch64_reg_or_shift_imm_si" "Usl,Uss,r"))))] + "" + { + switch (which_alternative) + { + case 0: + { + machine_mode dest, vec_mode; + int val = INTVAL (operands[2]); + int size = 32 - val; + if (size == 16) + dest = HImode; + else if (size == 8) + dest = QImode; + else + gcc_unreachable (); + + /* Get nearest 64-bit vector mode. */ + int nunits = 64 / size; + auto vector_mode + = mode_for_vector (as_a (dest), nunits); + if (!vector_mode.exists (&vec_mode)) + gcc_unreachable (); + operands[1] = gen_rtx_REG (vec_mode, REGNO (operands[1])); + operands[2] = gen_int_mode (val / size, SImode); + + /* Ideally we just call aarch64_get_lane_zero_extend but reload gets + into a weird loop due to a mov of w -> r being present most time + this instruction applies. */ + switch (dest) + { + case QImode: + return "umov\\t%w0, %1.b[%2]"; + case HImode: + return "umov\\t%w0, %1.h[%2]"; + default: + gcc_unreachable (); + } + } + case 1: + return "\\t%w0, %w1, %2"; + case 2: + return "\\t%w0, %w1, %w2"; + default: + gcc_unreachable (); + } + } + [(set_attr "type" "neon_to_gp,bfx,shift_reg")] +) + (define_insn "*3_insn" [(set (match_operand:SHORT 0 "register_operand" "=r") (ASHIFT:SHORT (match_operand:SHORT 1 "register_operand" "r") diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md index ee7587cca1673208e2bfd6b503a21d0c8b69bf75..470510d691ee8589aec9b0a71034677534641bea 100644 --- a/gcc/config/aarch64/constraints.md +++ b/gcc/config/aarch64/constraints.md @@ -166,6 +166,14 @@ (define_constraint "Uss" (and (match_code "const_int") (match_test "(unsigned HOST_WIDE_INT) ival < 32"))) +(define_constraint "Usl" + "@internal + A constraint that matches an immediate shift constant in SImode that has an + exact mode available to use." + (and (match_code "const_int") + (and (match_test "satisfies_constraint_Uss (op)") + (match_test "(32 - ival == 8) || (32 - ival == 16)")))) + (define_constraint "Usn" "A constant that can be used with a CCMN operation (once negated)." (and (match_code "const_int") diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index e904407b2169e589b7007ff966b2d9347a6d0fd2..bf16207225e3a4f1f20ed6f54321bccbbf15d73f 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -2149,8 +2149,11 @@ (define_mode_attr sve_lane_pair_con [(VNx8HF "y") (VNx4SF "x")]) ;; This code iterator allows the various shifts supported on the core (define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert rotate]) -;; This code iterator allows all shifts except for rotates. -(define_code_iterator SHIFT_no_rotate [ashift ashiftrt lshiftrt]) +;; This code iterator allows arithmetic shifts +(define_code_iterator SHIFT_arith [ashift ashiftrt]) + +;; Singleton code iterator for only logical right shift. +(define_code_iterator LSHIFTRT [lshiftrt]) ;; This code iterator allows the shifts supported in arithmetic instructions (define_code_iterator ASHIFT [ashift ashiftrt lshiftrt]) diff --git a/gcc/testsuite/gcc.target/aarch64/shift-read.c b/gcc/testsuite/gcc.target/aarch64/shift-read.c new file mode 100644 index 0000000000000000000000000000000000000000..e6e355224c96344fe1cdabd6b0d3d5d609cd95bd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/shift-read.c @@ -0,0 +1,85 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" "" { target { le } } } } */ + +#include + +/* +** foor: +** umov w0, v0.h\[3\] +** ret +*/ +unsigned int foor (uint32x4_t x) +{ + return x[1] >> 16; +} + +/* +** fool: +** umov w0, v0.s\[1\] +** lsl w0, w0, 16 +** ret +*/ +unsigned int fool (uint32x4_t x) +{ + return x[1] << 16; +} + +/* +** foor2: +** umov w0, v0.h\[7\] +** ret +*/ +unsigned short foor2 (uint32x4_t x) +{ + return x[3] >> 16; +} + +/* +** fool2: +** fmov w0, s0 +** lsl w0, w0, 16 +** ret +*/ +unsigned int fool2 (uint32x4_t x) +{ + return x[0] << 16; +} + +typedef int v4si __attribute__ ((vector_size (16))); + +/* +** bar: +** addv s0, v0.4s +** fmov w0, s0 +** lsr w1, w0, 16 +** add w0, w1, w0, uxth +** ret +*/ +int bar (v4si x) +{ + unsigned int sum = vaddvq_s32 (x); + return (((uint16_t)(sum & 0xffff)) + ((uint32_t)sum >> 16)); +} + +/* +** foo: +** lsr w0, w0, 16 +** ret +*/ +unsigned short foo (unsigned x) +{ + return x >> 16; +} + +/* +** foo2: +** ... +** umov w0, v[0-8]+.h\[1\] +** ret +*/ +unsigned short foo2 (v4si x) +{ + int y = x[0] + x[1]; + return y >> 16; +} --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -5493,7 +5493,7 @@ (define_insn "*rol3_insn" ;; zero_extend version of shifts (define_insn "*si3_insn_uxtw" [(set (match_operand:DI 0 "register_operand" "=r,r") - (zero_extend:DI (SHIFT_no_rotate:SI + (zero_extend:DI (SHIFT_arith:SI (match_operand:SI 1 "register_operand" "r,r") (match_operand:QI 2 "aarch64_reg_or_shift_imm_si" "Uss,r"))))] "" @@ -5528,6 +5528,60 @@ (define_insn "*rolsi3_insn_uxtw" [(set_attr "type" "rotate_imm")] ) +(define_insn "*si3_insn2_uxtw" + [(set (match_operand:DI 0 "register_operand" "=r,?r,r") + (zero_extend:DI (LSHIFTRT:SI + (match_operand:SI 1 "register_operand" "w,r,r") + (match_operand:QI 2 "aarch64_reg_or_shift_imm_si" "Usl,Uss,r"))))] + "" + { + switch (which_alternative) + { + case 0: + { + machine_mode dest, vec_mode; + int val = INTVAL (operands[2]); + int size = 32 - val; + if (size == 16) + dest = HImode; + else if (size == 8) + dest = QImode; + else + gcc_unreachable (); + + /* Get nearest 64-bit vector mode. */ + int nunits = 64 / size; + auto vector_mode + = mode_for_vector (as_a (dest), nunits); + if (!vector_mode.exists (&vec_mode)) + gcc_unreachable (); + operands[1] = gen_rtx_REG (vec_mode, REGNO (operands[1])); + operands[2] = gen_int_mode (val / size, SImode); + + /* Ideally we just call aarch64_get_lane_zero_extend but reload gets + into a weird loop due to a mov of w -> r being present most time + this instruction applies. */ + switch (dest) + { + case QImode: + return "umov\\t%w0, %1.b[%2]"; + case HImode: + return "umov\\t%w0, %1.h[%2]"; + default: + gcc_unreachable (); + } + } + case 1: + return "\\t%w0, %w1, %2"; + case 2: + return "\\t%w0, %w1, %w2"; + default: + gcc_unreachable (); + } + } + [(set_attr "type" "neon_to_gp,bfx,shift_reg")] +) + (define_insn "*3_insn" [(set (match_operand:SHORT 0 "register_operand" "=r") (ASHIFT:SHORT (match_operand:SHORT 1 "register_operand" "r") diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md index ee7587cca1673208e2bfd6b503a21d0c8b69bf75..470510d691ee8589aec9b0a71034677534641bea 100644 --- a/gcc/config/aarch64/constraints.md +++ b/gcc/config/aarch64/constraints.md @@ -166,6 +166,14 @@ (define_constraint "Uss" (and (match_code "const_int") (match_test "(unsigned HOST_WIDE_INT) ival < 32"))) +(define_constraint "Usl" + "@internal + A constraint that matches an immediate shift constant in SImode that has an + exact mode available to use." + (and (match_code "const_int") + (and (match_test "satisfies_constraint_Uss (op)") + (match_test "(32 - ival == 8) || (32 - ival == 16)")))) + (define_constraint "Usn" "A constant that can be used with a CCMN operation (once negated)." (and (match_code "const_int") diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index e904407b2169e589b7007ff966b2d9347a6d0fd2..bf16207225e3a4f1f20ed6f54321bccbbf15d73f 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -2149,8 +2149,11 @@ (define_mode_attr sve_lane_pair_con [(VNx8HF "y") (VNx4SF "x")]) ;; This code iterator allows the various shifts supported on the core (define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert rotate]) -;; This code iterator allows all shifts except for rotates. -(define_code_iterator SHIFT_no_rotate [ashift ashiftrt lshiftrt]) +;; This code iterator allows arithmetic shifts +(define_code_iterator SHIFT_arith [ashift ashiftrt]) + +;; Singleton code iterator for only logical right shift. +(define_code_iterator LSHIFTRT [lshiftrt]) ;; This code iterator allows the shifts supported in arithmetic instructions (define_code_iterator ASHIFT [ashift ashiftrt lshiftrt]) diff --git a/gcc/testsuite/gcc.target/aarch64/shift-read.c b/gcc/testsuite/gcc.target/aarch64/shift-read.c new file mode 100644 index 0000000000000000000000000000000000000000..e6e355224c96344fe1cdabd6b0d3d5d609cd95bd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/shift-read.c @@ -0,0 +1,85 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" "" { target { le } } } } */ + +#include + +/* +** foor: +** umov w0, v0.h\[3\] +** ret +*/ +unsigned int foor (uint32x4_t x) +{ + return x[1] >> 16; +} + +/* +** fool: +** umov w0, v0.s\[1\] +** lsl w0, w0, 16 +** ret +*/ +unsigned int fool (uint32x4_t x) +{ + return x[1] << 16; +} + +/* +** foor2: +** umov w0, v0.h\[7\] +** ret +*/ +unsigned short foor2 (uint32x4_t x) +{ + return x[3] >> 16; +} + +/* +** fool2: +** fmov w0, s0 +** lsl w0, w0, 16 +** ret +*/ +unsigned int fool2 (uint32x4_t x) +{ + return x[0] << 16; +} + +typedef int v4si __attribute__ ((vector_size (16))); + +/* +** bar: +** addv s0, v0.4s +** fmov w0, s0 +** lsr w1, w0, 16 +** add w0, w1, w0, uxth +** ret +*/ +int bar (v4si x) +{ + unsigned int sum = vaddvq_s32 (x); + return (((uint16_t)(sum & 0xffff)) + ((uint32_t)sum >> 16)); +} + +/* +** foo: +** lsr w0, w0, 16 +** ret +*/ +unsigned short foo (unsigned x) +{ + return x >> 16; +} + +/* +** foo2: +** ... +** umov w0, v[0-8]+.h\[1\] +** ret +*/ +unsigned short foo2 (v4si x) +{ + int y = x[0] + x[1]; + return y >> 16; +}