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Signed-off-by: Abel Vesa Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,sm8550-tcsr.yaml | 53 +++++++++++++++++++ include/dt-bindings/clock/qcom,sm8550-tcsr.h | 18 +++++++ 2 files changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml create mode 100644 include/dt-bindings/clock/qcom,sm8550-tcsr.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml new file mode 100644 index 000000000000..15176b0457d1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8550-tcsr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm TCSR Clock Controller on SM8550 + +maintainers: + - Bjorn Andersson + +description: | + Qualcomm TCSR clock control module provides the clocks, resets and + power domains on SM8550 + + See also:: include/dt-bindings/clock/qcom,sm8550-tcsr.h + +properties: + compatible: + const: qcom,sm8550-tcsr + + clocks: + items: + - description: Board XO source + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | + #include + + clock-controller@1fc0000 { + compatible = "qcom,sm8550-tcsr"; + reg = <0x1fc0000 0x30000>; + clocks = <&rpmhcc RPMH_CXO_PAD_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +... diff --git a/include/dt-bindings/clock/qcom,sm8550-tcsr.h b/include/dt-bindings/clock/qcom,sm8550-tcsr.h new file mode 100644 index 000000000000..091cb76f953a --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8550-tcsr.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8550_H +#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8550_H + +/* TCSR CC clocks */ +#define TCSR_PCIE_0_CLKREF_EN 0 +#define TCSR_PCIE_1_CLKREF_EN 1 +#define TCSR_UFS_CLKREF_EN 2 +#define TCSR_UFS_PAD_CLKREF_EN 3 +#define TCSR_USB2_CLKREF_EN 4 +#define TCSR_USB3_CLKREF_EN 5 + +#endif From patchwork Tue Dec 6 12:56:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 30276 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2802742wrr; Tue, 6 Dec 2022 04:57:39 -0800 (PST) X-Google-Smtp-Source: AA0mqf4HxBIZaNjFxwVwAvD04rnHXf7Qk3noX37L+MbXO8Kors36BcAb9zPSL+9uXJ+VZALNCu2k X-Received: by 2002:a05:6a00:1310:b0:561:a494:b299 with SMTP id j16-20020a056a00131000b00561a494b299mr67222029pfu.34.1670331458892; Tue, 06 Dec 2022 04:57:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670331458; cv=none; d=google.com; s=arc-20160816; b=lkFJPn4RKUw8pcIOCLn4NxWJB8XAvSyUTVzWmeLY5KVEz68zWvjUXhYC848gmLzSfZ jde/cZV1ZYHoNJwZBKjS1rn9ns9TtckP3diadSA41m+8wGFX0TP/SwTwv0ryY+alDk0M En8jgJTKh0ICK2Pw98R/zXGSl/i/KAn240rNC6Q1+NL7vPD5Ui/tbWzIe4M1Mri3TSge lFV7B+HnZgY1PcAOIfwTMuoC0NTO/TOhHK/gwA6kLMqZxbEbvd5Z3u85A7PQX21EGRyu GSTiA4sCkukUpTKcUy7iyHLqRkyBc9cOaE5/gMWBD1JrPRNKgvVRtIq6C/clwuctTN6i eEhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=BhLdyy64MSy62j2GfoCPYL31V7FQmGy5yzQrHHdIKxE=; b=kCR3SezObVtOcceaELl8WUpmvTtbcmxr9U3LvQhJQXeekwIoolz2AQPIGMGDW3Vasb 5Y2qNqOLrQ8nr90XTcZT1kJPjBItbkxgy+ALAdoH+0TnKI7ReNLCqAjX+2vYyBCzxh1g Ibc3+FRnTzfFyrFfdwOKRtSasiv4n8e93ydRDTcewnu/83qFBQX63vHNiK9AAHakQnMt d0uP5oiYqywS9WiWJ2xEJUCixzbSXenIzR1ZVuTMQVKo5tMnGEJ1iq/MGkd6Lu+MIBPL 9Arn/j0Wx3hVOd/IMt48sKDmdR/yZhhznNFtrKOYKLBXomCe44xSuQwWcKY3/DhZFttv jyaw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=g6HBJJPs; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Abel Vesa Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml index fccb91e78e49..b405da7700be 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -31,6 +31,7 @@ properties: - qcom,sm8250-rpmh-clk - qcom,sm8350-rpmh-clk - qcom,sm8450-rpmh-clk + - qcom,sm8550-rpmh-clk clocks: maxItems: 1 From patchwork Tue Dec 6 12:56:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 30279 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2803093wrr; Tue, 6 Dec 2022 04:58:34 -0800 (PST) X-Google-Smtp-Source: AA0mqf5q1F1vYK/k1ctmu9IGGrxaZvTxqjYfjFEPOWgm04xzeAbjDudd4lBSMTjFM9zJxqw0vUrE X-Received: by 2002:a05:6a00:348b:b0:575:d693:3882 with SMTP id cp11-20020a056a00348b00b00575d6933882mr27668634pfb.45.1670331514310; Tue, 06 Dec 2022 04:58:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670331514; cv=none; d=google.com; s=arc-20160816; b=CGmwoQMPJQX/+YcyKgHat6SEvqACC5A1ndsZQQxCUfHIcqYJnWsBA53sH1zmcdxSMi P6v4KMvHCVV06ohuNxH4mTWVHfBZG90SU7M31n7iD+hhr55B5XBc53NS0WRvoINQGE8l Jjcq16WGvY3NRGC6Mdk+iCJUtyBHoom38eXaWjaT5N/LSx13ABNjsxa5MRjfiAwng+vQ TztA2fnQLLS9EvGXo1PM6pAQrGz6+OLoN+ALVGMEk0gEIrJRq1+PfSWWmqQPG5336TJ1 1N6ZxO1/9JFmhInrR6J2duqFqtVjSVku1+7OIIT8HMLjM3TC5QnKDrytmswgTjy1RkmQ N9YQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=quL6WPeERZYedqB/nklThp0WUV+KiBC4sy50mhyRH+A=; b=nB0rgBe/NjGtoSqlMUiAK7n8kPkgnhfbJkK06mZy8i4Oe425RkMBmP67GRG8xYWWvK IRYBgtPEPMBoQb/UY5MyasmaWdGE293LJzOYqoYfEgmHTGVlwPxX5SBVc/fn1uwMADjx uEqFSPiZUdIq/D/d3jJKZJxVAuctVGxfWCrm3gXXoFVp4ZUxF7euMlaPr2SLt9/113nd kZw7gMhWtHnElVz/E8t0rTwzTu34YkEZaSEfVLgWhHV9CccFW1jFVfxM0DkNSkptkev2 SYGVxLW2yGD3qEC61LB1OPBerNzkpvEWDAa1sDfMjm0iIWHwOa057Itee5S+N39j3fZo QJ0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZidEHgzT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Abel Vesa Reviewed-by: Krzysztof Kozlowski --- include/dt-bindings/clock/qcom,rpmh.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/qcom,rpmh.h b/include/dt-bindings/clock/qcom,rpmh.h index 0a7d1be0d124..f3e0288420ce 100644 --- a/include/dt-bindings/clock/qcom,rpmh.h +++ b/include/dt-bindings/clock/qcom,rpmh.h @@ -33,5 +33,7 @@ #define RPMH_HWKM_CLK 24 #define RPMH_QLINK_CLK 25 #define RPMH_QLINK_CLK_A 26 +#define RPMH_CXO_PAD_CLK 27 +#define RPMH_CXO_PAD_CLK_A 28 #endif From patchwork Tue Dec 6 12:56:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 30277 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2802860wrr; Tue, 6 Dec 2022 04:58:00 -0800 (PST) X-Google-Smtp-Source: AA0mqf5WQuuLvlZjzkWj9j8fvRc5n+0V5f3XrmNH5t+A5ZQSUnsGNeWZhvl661QcD92AswzCWFZM X-Received: by 2002:a17:90a:d3ce:b0:218:7a66:64b9 with SMTP id d14-20020a17090ad3ce00b002187a6664b9mr89977360pjw.85.1670331480216; Tue, 06 Dec 2022 04:58:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670331480; cv=none; d=google.com; s=arc-20160816; b=zqZDVDxnzPvwpwGANj8Igs7MLKJmJU6wlM8eoyZCIiwNJszrsY8l0OlrYuPrCpxanK 37YbLVrlMW5Ei/u7rugupWM0ovZJZnVw9mP3uNZxsDFybpmVYgYIYrxXfwP8LUT1dNo0 j1cABH0lBFX6pL6IpUhGedBZ/9DUGUf4/EdajIMlGbiB/M8G4zAX+JBt96nZYjTyKHj2 1kUVyRl5t1eqfWdcXiVaIo0Vj+RFGgdz65TLkiUnRxvrkWl6GFBbVwvM49g8Gh6JAPVy 5tnB5ybr/S43oEBWnL9R/Cm/TWLQ2SZN/yb9/X9oA4Lop+RgOqt5uIVPODIKhnkl1yHm UPng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=xGLwUiqnWNNCSh7SfaJVMgmwcN3tXBqQdd3/EujPmbQ=; b=SnJD8UwRxokifKt6bFlQc5fwzyqMjlMD+9y6ApkseVWsb4+WqB72VwwP3b2FP4L8HC wIhyvPb72C6XAiCnasRc07rWVUgfirbk21zFV+1o5W9dZIy8eBtQwTO/BEjUoPde3nFY iLCFARRZ3xlLLmoLoH57FfZnpzfsSbvJxxBeCSs4uIDCEfxki9B52LkQeoEtC7o5mrZx zqIDWjHk7DslIcdR8b9GZ6oKqAMHW4UdeIfFUw+mJZErdrVQaxnWeOLfLQARDoj8JWOE 0pB4ecEV/JHDi14gO3teXbyj8iu82+3qXhJHIQbjs94wZa+FwiVh9kYjxTuhfm0T9Qhy qlvg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BLvjAc5q; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/clk-rpmh.c | 110 +++++++++++++++++++++++++++++------- 1 file changed, 90 insertions(+), 20 deletions(-) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 2c2ef4b6d130..ce81c76ed0fd 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -130,6 +130,34 @@ static DEFINE_MUTEX(rpmh_clk_lock); }, \ } +#define DEFINE_CLK_FIXED_FACTOR(_name, _parent_name, _div) \ + static struct clk_fixed_factor clk_fixed_factor##_##_name = { \ + .mult = 1, \ + .div = _div, \ + .hw.init = &(struct clk_init_data){ \ + .ops = &clk_fixed_factor_ops, \ + .name = #_name, \ + .parent_data = &(const struct clk_parent_data){ \ + .fw_name = #_parent_name, \ + .name = #_parent_name, \ + }, \ + .num_parents = 1, \ + }, \ + }; \ + static struct clk_fixed_factor clk_fixed_factor##_##_name##_ao = { \ + .mult = 1, \ + .div = _div, \ + .hw.init = &(struct clk_init_data){ \ + .ops = &clk_fixed_factor_ops, \ + .name = #_name "_ao", \ + .parent_data = &(const struct clk_parent_data){ \ + .fw_name = #_parent_name "_ao", \ + .name = #_parent_name "_ao", \ + }, \ + .num_parents = 1, \ + }, \ + } + static inline struct clk_rpmh *to_clk_rpmh(struct clk_hw *_hw) { return container_of(_hw, struct clk_rpmh, hw); @@ -345,6 +373,8 @@ DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 2); DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 4); DEFINE_CLK_RPMH_ARC(qlink, "qphy.lvl", 0x1, 4); +DEFINE_CLK_FIXED_FACTOR(bi_tcxo_div2, bi_tcxo, 2); + DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a2, "lnbclka1", 2); DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a2, "lnbclka2", 2); DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a2, "lnbclka3", 2); @@ -366,6 +396,16 @@ DEFINE_CLK_RPMH_VRM(rf_clk2, _d, "rfclkd2", 1); DEFINE_CLK_RPMH_VRM(rf_clk3, _d, "rfclkd3", 1); DEFINE_CLK_RPMH_VRM(rf_clk4, _d, "rfclkd4", 1); +DEFINE_CLK_RPMH_VRM(clk1, _a1, "clka1", 1); +DEFINE_CLK_RPMH_VRM(clk2, _a1, "clka2", 1); +DEFINE_CLK_RPMH_VRM(clk3, _a1, "clka3", 1); +DEFINE_CLK_RPMH_VRM(clk4, _a1, "clka4", 1); +DEFINE_CLK_RPMH_VRM(clk5, _a1, "clka5", 1); + +DEFINE_CLK_RPMH_VRM(clk6, _a2, "clka6", 2); +DEFINE_CLK_RPMH_VRM(clk7, _a2, "clka7", 2); +DEFINE_CLK_RPMH_VRM(clk8, _a2, "clka8", 2); + DEFINE_CLK_RPMH_VRM(div_clk1, _div2, "divclka1", 2); DEFINE_CLK_RPMH_BCM(ce, "CE0"); @@ -576,6 +616,33 @@ static const struct clk_rpmh_desc clk_rpmh_sm8450 = { .num_clks = ARRAY_SIZE(sm8450_rpmh_clocks), }; +static struct clk_hw *sm8550_rpmh_clocks[] = { + [RPMH_CXO_PAD_CLK] = &clk_rpmh_bi_tcxo_div2.hw, + [RPMH_CXO_PAD_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, + [RPMH_CXO_CLK] = &clk_fixed_factor_bi_tcxo_div2.hw, + [RPMH_CXO_CLK_A] = &clk_fixed_factor_bi_tcxo_div2_ao.hw, + [RPMH_LN_BB_CLK1] = &clk_rpmh_clk6_a2.hw, + [RPMH_LN_BB_CLK1_A] = &clk_rpmh_clk6_a2_ao.hw, + [RPMH_LN_BB_CLK2] = &clk_rpmh_clk7_a2.hw, + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_clk7_a2_ao.hw, + [RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a2.hw, + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a2_ao.hw, + [RPMH_RF_CLK1] = &clk_rpmh_clk1_a1.hw, + [RPMH_RF_CLK1_A] = &clk_rpmh_clk1_a1_ao.hw, + [RPMH_RF_CLK2] = &clk_rpmh_clk2_a1.hw, + [RPMH_RF_CLK2_A] = &clk_rpmh_clk2_a1_ao.hw, + [RPMH_RF_CLK3] = &clk_rpmh_clk3_a1.hw, + [RPMH_RF_CLK3_A] = &clk_rpmh_clk3_a1_ao.hw, + [RPMH_RF_CLK4] = &clk_rpmh_clk4_a1.hw, + [RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a1_ao.hw, + [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_sm8550 = { + .clks = sm8550_rpmh_clocks, + .num_clks = ARRAY_SIZE(sm8550_rpmh_clocks), +}; + static struct clk_hw *sc7280_rpmh_clocks[] = { [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, @@ -683,29 +750,31 @@ static int clk_rpmh_probe(struct platform_device *pdev) name = hw_clks[i]->init->name; - rpmh_clk = to_clk_rpmh(hw_clks[i]); - res_addr = cmd_db_read_addr(rpmh_clk->res_name); - if (!res_addr) { - dev_err(&pdev->dev, "missing RPMh resource address for %s\n", - rpmh_clk->res_name); - return -ENODEV; - } + if (hw_clks[i]->init->ops != &clk_fixed_factor_ops) { + rpmh_clk = to_clk_rpmh(hw_clks[i]); + res_addr = cmd_db_read_addr(rpmh_clk->res_name); + if (!res_addr) { + dev_err(&pdev->dev, "missing RPMh resource address for %s\n", + rpmh_clk->res_name); + return -ENODEV; + } - data = cmd_db_read_aux_data(rpmh_clk->res_name, &aux_data_len); - if (IS_ERR(data)) { - ret = PTR_ERR(data); - dev_err(&pdev->dev, - "error reading RPMh aux data for %s (%d)\n", - rpmh_clk->res_name, ret); - return ret; - } + data = cmd_db_read_aux_data(rpmh_clk->res_name, &aux_data_len); + if (IS_ERR(data)) { + ret = PTR_ERR(data); + dev_err(&pdev->dev, + "error reading RPMh aux data for %s (%d)\n", + rpmh_clk->res_name, ret); + return ret; + } - /* Convert unit from Khz to Hz */ - if (aux_data_len == sizeof(*data)) - rpmh_clk->unit = le32_to_cpu(data->unit) * 1000ULL; + /* Convert unit from Khz to Hz */ + if (aux_data_len == sizeof(*data)) + rpmh_clk->unit = le32_to_cpu(data->unit) * 1000ULL; - rpmh_clk->res_addr += res_addr; - rpmh_clk->dev = &pdev->dev; + rpmh_clk->res_addr += res_addr; + rpmh_clk->dev = &pdev->dev; + } ret = devm_clk_hw_register(&pdev->dev, hw_clks[i]); if (ret) { @@ -741,6 +810,7 @@ static const struct of_device_id clk_rpmh_match_table[] = { { .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250}, { .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350}, { .compatible = "qcom,sm8450-rpmh-clk", .data = &clk_rpmh_sm8450}, + { .compatible = "qcom,sm8550-rpmh-clk", .data = &clk_rpmh_sm8550}, { .compatible = "qcom,sc7280-rpmh-clk", .data = &clk_rpmh_sc7280}, { } }; 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Add clock driver for it. This patch is based on initial code downstream. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/Kconfig | 7 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/tcsrcc-sm8550.c | 192 +++++++++++++++++++++++++++++++ 3 files changed, 200 insertions(+) create mode 100644 drivers/clk/qcom/tcsrcc-sm8550.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 70d43f0a8919..b9f5505d68f0 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -797,6 +797,13 @@ config SM_GPUCC_8350 Say Y if you want to support graphics controller devices and functionality such as 3D graphics. +config SM_TCSRCC_8550 + tristate "SM8550 TCSR Clock Controller" + select QCOM_GDSC + help + Support for the TCSR clock controller on SM8550 devices. + Say Y if you want to use peripheral devices such as SD/UFS. + config SM_VIDEOCC_8150 tristate "SM8150 Video Clock Controller" select SM_GCC_8150 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index f18c446a97ea..f5ce429c724c 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -112,6 +112,7 @@ obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o +obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o diff --git a/drivers/clk/qcom/tcsrcc-sm8550.c b/drivers/clk/qcom/tcsrcc-sm8550.c new file mode 100644 index 000000000000..2c67ee71c196 --- /dev/null +++ b/drivers/clk/qcom/tcsrcc-sm8550.c @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "reset.h" + +enum { + DT_BI_TCXO_PAD, +}; + +static struct clk_branch tcsr_pcie_0_clkref_en = { + .halt_reg = 0x15100, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x15100, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_pcie_0_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_pcie_1_clkref_en = { + .halt_reg = 0x15114, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x15114, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_pcie_1_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_ufs_clkref_en = { + .halt_reg = 0x15110, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x15110, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_ufs_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_ufs_pad_clkref_en = { + .halt_reg = 0x15104, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x15104, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_ufs_pad_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb2_clkref_en = { + .halt_reg = 0x15118, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x15118, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_usb2_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb3_clkref_en = { + .halt_reg = 0x15108, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x15108, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_usb3_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *tcsr_cc_sm8550_clocks[] = { + [TCSR_PCIE_0_CLKREF_EN] = &tcsr_pcie_0_clkref_en.clkr, + [TCSR_PCIE_1_CLKREF_EN] = &tcsr_pcie_1_clkref_en.clkr, + [TCSR_UFS_CLKREF_EN] = &tcsr_ufs_clkref_en.clkr, + [TCSR_UFS_PAD_CLKREF_EN] = &tcsr_ufs_pad_clkref_en.clkr, + [TCSR_USB2_CLKREF_EN] = &tcsr_usb2_clkref_en.clkr, + [TCSR_USB3_CLKREF_EN] = &tcsr_usb3_clkref_en.clkr, +}; + +static const struct regmap_config tcsr_cc_sm8550_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x2f000, + .fast_io = true, +}; + +static const struct qcom_cc_desc tcsr_cc_sm8550_desc = { + .config = &tcsr_cc_sm8550_regmap_config, + .clks = tcsr_cc_sm8550_clocks, + .num_clks = ARRAY_SIZE(tcsr_cc_sm8550_clocks), +}; + +static const struct of_device_id tcsr_cc_sm8550_match_table[] = { + { .compatible = "qcom,sm8550-tcsr" }, + { } +}; +MODULE_DEVICE_TABLE(of, tcsr_cc_sm8550_match_table); + +static int tcsr_cc_sm8550_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &tcsr_cc_sm8550_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return qcom_cc_really_probe(pdev, &tcsr_cc_sm8550_desc, regmap); +} + +static struct platform_driver tcsr_cc_sm8550_driver = { + .probe = tcsr_cc_sm8550_probe, + .driver = { + .name = "tcsr_cc-sm8550", + .of_match_table = tcsr_cc_sm8550_match_table, + }, +}; + +static int __init tcsr_cc_sm8550_init(void) +{ + return platform_driver_register(&tcsr_cc_sm8550_driver); +} +subsys_initcall(tcsr_cc_sm8550_init); + +static void __exit tcsr_cc_sm8550_exit(void) +{ + platform_driver_unregister(&tcsr_cc_sm8550_driver); +} +module_exit(tcsr_cc_sm8550_exit); + +MODULE_DESCRIPTION("QTI TCSRCC SM8550 Driver"); +MODULE_LICENSE("GPL");