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[2620:137:e000::1:20]) by mx.google.com with ESMTP id h11-20020a170902f54b00b00186c3afbd25si12449676plf.349.2022.12.05.22.54.44; Mon, 05 Dec 2022 22:54:57 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b="PM/5qZLR"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234046AbiLFGpx (ORCPT + 99 others); Tue, 6 Dec 2022 01:45:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231349AbiLFGps (ORCPT ); Tue, 6 Dec 2022 01:45:48 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 501EA20984; Mon, 5 Dec 2022 22:45:47 -0800 (PST) X-UUID: 33a02a8c2439498cbef0682cc4ede9d8-20221206 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=Lj5CWXIGuLtBuhK0tZMR3SP8BZ3ZoFXyfgCI59Jl6HI=; b=PM/5qZLRt8SroTSQD6VzBBaC6NPWtuIZJzk1293H3v5sfkWwTI/uDLgL034X2SJIY2wazguHINeCwgrRuMbHVh1cqKxzqSbbzWA6JNxUl4kxDz5v0zUCKlUcyY2FfU30pKeU3Z3NKD9FExhoQfk1qmXHPhfL9hHfwVLblKT/7vY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:17e8255a-ace4-4201-a749-487109e1933d,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:90 X-CID-INFO: VERSION:1.1.14,REQID:17e8255a-ace4-4201-a749-487109e1933d,IP:0,URL :0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:90 X-CID-META: VersionHash:dcaaed0,CLOUDID:6dacaa16-b863-49f8-8228-cbdfeedd1fa4,B ulkID:221206144542LV0V17IK,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 33a02a8c2439498cbef0682cc4ede9d8-20221206 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1970936509; Tue, 06 Dec 2022 14:45:41 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Tue, 6 Dec 2022 14:45:38 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 6 Dec 2022 14:45:37 +0800 From: Yunfei Dong To: Yunfei Dong , Rob Herring , Chen-Yu Tsai , Hans Verkuil , AngeloGioacchino Del Regno , Benjamin Gaignard CC: Mauro Carvalho Chehab , Matthias Brugger , Hsin-Yi Wang , Daniel Vetter , Steve Cho , , , , , , Subject: [PATCH v5,1/3] media: dt-bindings: media: mediatek: vcodec: adapt to the 'clock-names' of different platforms Date: Tue, 6 Dec 2022 14:45:34 +0800 Message-ID: <20221206064536.16592-1-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751073003157181605?= X-GMAIL-MSGID: =?utf-8?q?1751446661226676630?= mt8195 and mt8192 have different clock numbers, separate 'clock-names' according to compatible name. Signed-off-by: Yunfei Dong Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rob Herring --- compared with v4: - change min clocks and clock-names from 1 to 4 compared with v3: - rewrite clock-names according to different platforms. Reference series: [1]: v5 of this series is presend by Allen-KH Cheng. message-id: 20221128143832.25584-4-allen-kh.cheng@mediatek.com --- .../media/mediatek,vcodec-subdev-decoder.yaml | 41 ++++++++++++++++--- 1 file changed, 35 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml index 7c5b4a91c59b..c56af1c1d9db 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml @@ -110,15 +110,12 @@ patternProperties: Refer to bindings/iommu/mediatek,iommu.yaml. clocks: + minItems: 4 maxItems: 5 clock-names: - items: - - const: sel - - const: soc-vdec - - const: soc-lat - - const: vdec - - const: top + minItems: 4 + maxItems: 5 assigned-clocks: maxItems: 1 @@ -159,6 +156,38 @@ then: required: - interrupts +allOf: + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8192-vcodec-dec + then: + properties: + clock-names: + items: + - const: sel + - const: soc-vdec + - const: soc-lat + - const: vdec + - const: top + + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8195-vcodec-dec + then: + properties: + clock-names: + items: + - const: sel + - const: vdec + - const: lat + - const: top + additionalProperties: false examples: From patchwork Tue Dec 6 06:45:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?WXVuZmVpIERvbmcgKOiRo+S6kemjnik=?= X-Patchwork-Id: 30104 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2666643wrr; Mon, 5 Dec 2022 22:53:32 -0800 (PST) X-Google-Smtp-Source: AA0mqf5a1/wJjhKswljLFIiVCaQq89qD9oYPCI3rP2uqg7thTwcJ5Z3gjb5y6XXGatiuuwDuC26D X-Received: by 2002:a17:90a:5998:b0:219:d33d:4689 with SMTP id l24-20020a17090a599800b00219d33d4689mr9168309pji.233.1670309611792; Mon, 05 Dec 2022 22:53:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670309611; cv=none; d=google.com; s=arc-20160816; b=ev0sYC4EG9DfVZ2goUUkUw3jAn3B29SfWDWaYUhn1Npx2HwEL49bGjDSMi8Yn0iWB3 40LAByxT3z83XRyfOwqM4lF/fJ4EbvIcnE3wtOO3RJQUhDLN9e6hhU1TEcz7WIaGIrsJ d7K6bCWkygrmLnywm2j/+aAk2xZrpdyoMfQUN1H2jTet1ZtN71Mv60dtIsbje6HQyLSt Nof8HdPSYiDVnUvDZVXE0KWVUo+ARw1B0W9fCBIEbkuyESFaY4P7Qdvl+hwIMzXwXWGR lNr9CLwN5OQExleyWs4lIvm9GGNd2r7RyGk1j9Ib3mS/Asw9aArBreuZXW5Nel4g5hdl ws6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=cr5Zs5cBIaAVrlM9snlYaXPA25Y+7yTCHfuXSnNyyIU=; b=HMnkByKe3QvWAeyhX704b0v63akS43VWhsBvuyEUXn6w9RmbdabG2VMOw5x1PRok5O 4kl2Hk/S8cbd4BqM19tGr5qXyC7TwiudlfmZots+GVRxeyLzc+k+wBbqKB3HejqFCW96 TrxtCQh+2K1eGA46xa5LqkQAH7tXuIEbjNmlWbuadVA6jusVeFbdmVI7FRHlFnX6pfFq vkGevl16yhKI9YCJlDPksz46UxHduGngsLO7vAPq27Pz504AgxHCByxoZ8yuJ0SaurhO XrxeuJLOhPCY1L5zq2+628zfz4xCIrLhC2t/dNPQashUoVRDuF99fzpkf4NeTg4uXFJm IXsQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=KvJLwr76; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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Changing the max reg value from 1 to 2. Adding the description for VDEC_SYS and VDEC_MISC. Signed-off-by: Yunfei Dong Acked-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno --- .../bindings/media/mediatek,vcodec-subdev-decoder.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml index c56af1c1d9db..30917b66d62d 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml @@ -61,7 +61,10 @@ properties: - mediatek,mt8195-vcodec-dec reg: - maxItems: 1 + minItems: 1 + items: + - description: VDEC_SYS register space + - description: VDEC_RACING_CTRL register space iommus: minItems: 1 @@ -98,6 +101,7 @@ patternProperties: reg: maxItems: 1 + description: VDEC_MISC register space interrupts: maxItems: 1 From patchwork Tue Dec 6 06:45:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?WXVuZmVpIERvbmcgKOiRo+S6kemjnik=?= X-Patchwork-Id: 30106 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2667126wrr; Mon, 5 Dec 2022 22:55:18 -0800 (PST) X-Google-Smtp-Source: AA0mqf7Ns6JQNQGS28gHPRvZLh0KwwITafkmkwwb1h6bpXxctw5pSHQdooLakH3aiW3+SToyWkGs X-Received: by 2002:a17:902:820b:b0:188:9ae7:bb7d with SMTP id x11-20020a170902820b00b001889ae7bb7dmr72324149pln.113.1670309718378; Mon, 05 Dec 2022 22:55:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670309718; cv=none; d=google.com; s=arc-20160816; b=AZhyPcFQ6tjvczvVBfWBL6zt/by/xWn8OK9rJviNmHoaFZ40rcyM4EUTXS4rQHhM7t Q0gjVry9/UoUA1lXA5IkxRhseARnRz/xXWgTiyua+SRIdKt0nXOAAbGr/4kwYT82SxqU xRhvsK/aJ/rmwxcgKvtq70ZgyZKbEUTF1N9NOfxQiZASk+x35S/em3nk9ZMb5AnJGDfD hE3zrJAvCWMfJsdM1GlZRi2XAacfjKG0JKZ137gGVCtfOd/mA7s4EEXv0Soz32aOkgGH mfeCSiT47TNkFTUiTNKaGQ3QtY2bvXInUDuOc8tAICAL2c05nyM8xh06b3rLT0STF5yo QbAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=VCzoXxASQ6qGnA6F6VYifoo4ULC7Kk/0LQh8ibSLUMk=; b=zaosNvgRVHbZUm7+bAqANxsPslB4v+Cjx89EfWbed05esHqfDCC6+vYKUq0t2f50bF ZkAbMcnF4jVACgo6f+Ty52nH46xZhzjP5DH6Hz8P+SolCKQxTHhvLB5rbgpgemEZLoFc tJz730N59cQBUhtLMll+a9KpZpJGcc4WTUoRg5lkXlNQoao6qwlxL5KZ90dKY+btHkcJ n7UJX4eAnQVgtnZwQOhdpgu30ujVH6AZ+BNCGHnchFtUkqGEjQNkgfvjrzkbdsRaJBz3 Uls1u0H869jTOORJzI/ANRkuOPBTXI5ZK/EqjcSzqacA22nmy02YglITPvBab+JOIorY qt5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=hABQrCZd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id s27-20020a63ff5b000000b004789808c39bsi8681684pgk.554.2022.12.05.22.55.05; Mon, 05 Dec 2022 22:55:18 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=hABQrCZd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234083AbiLFGp4 (ORCPT + 99 others); Tue, 6 Dec 2022 01:45:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234014AbiLFGpt (ORCPT ); Tue, 6 Dec 2022 01:45:49 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0BD0D20BDE; Mon, 5 Dec 2022 22:45:47 -0800 (PST) X-UUID: 63a77caabd9145178ebe40aef3a0d960-20221206 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=VCzoXxASQ6qGnA6F6VYifoo4ULC7Kk/0LQh8ibSLUMk=; b=hABQrCZdwNhpyLQjen+m0NiJnt//QIeYyKua9HZk2BBYc0rjRur77akeRCSqH6h7jgNYRNGT13y8JySFvmHb4z/0/0iSxZX3U90eX5inDQ/JyVV9gVuX8c4OQBkMv0kLPBgF/BWBvBgJUEdiRf+a3/K6pbQf/PqcaIajMtZd0f0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:7e3c5fa3-d27a-4ead-8064-f284a9386c81,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:70 X-CID-INFO: VERSION:1.1.14,REQID:7e3c5fa3-d27a-4ead-8064-f284a9386c81,IP:0,URL :0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTI ON:quarantine,TS:70 X-CID-META: VersionHash:dcaaed0,CLOUDID:a87dc4d1-652d-43fd-a13a-a5dd3c69a43d,B ulkID:221206144545SOC5IAOJ,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 63a77caabd9145178ebe40aef3a0d960-20221206 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1129545587; Tue, 06 Dec 2022 14:45:43 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Tue, 6 Dec 2022 14:45:41 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 6 Dec 2022 14:45:40 +0800 From: Yunfei Dong To: Yunfei Dong , Rob Herring , Chen-Yu Tsai , Hans Verkuil , AngeloGioacchino Del Regno , Benjamin Gaignard CC: Mauro Carvalho Chehab , Matthias Brugger , Hsin-Yi Wang , Daniel Vetter , Steve Cho , , , , , , Subject: [PATCH v5,3/3] arm64: dts: mt8195: Add video decoder node Date: Tue, 6 Dec 2022 14:45:36 +0800 Message-ID: <20221206064536.16592-3-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221206064536.16592-1-yunfei.dong@mediatek.com> References: <20221206064536.16592-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751446683344978125?= X-GMAIL-MSGID: =?utf-8?q?1751446683344978125?= Add video decoder node to mt8195 device tree. Signed-off-by: Yunfei Dong Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 70 ++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 905d1a90b406..6829aa0dcf4c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1874,6 +1874,76 @@ power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; }; + video-codec@18000000 { + compatible = "mediatek,mt8195-vcodec-dec"; + mediatek,scp = <&scp>; + iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>; + #address-cells = <2>; + #size-cells = <2>; + reg = <0 0x18000000 0 0x1000>, + <0 0x18004000 0 0x1000>; + ranges = <0 0 0 0x18000000 0 0x26000>; + + video-codec@2000 { + compatible = "mediatek,mtk-vcodec-lat-soc"; + reg = <0 0x2000 0 0x800>; + iommus = <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>, + <&iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT>; + clocks = <&topckgen CLK_TOP_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D4>; + clock-names = "sel", "vdec", "lat", "top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; + }; + + video-codec@10000 { + compatible = "mediatek,mtk-vcodec-lat"; + reg = <0 0x10000 0 0x800>; + interrupts = ; + iommus = <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>; + clocks = <&topckgen CLK_TOP_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D4>; + clock-names = "sel", "vdec", "lat", "top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; + }; + + video-codec@25000 { + compatible = "mediatek,mtk-vcodec-core"; + reg = <0 0x25000 0 0x1000>; /* VDEC_CORE_MISC */ + interrupts = ; + iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_UFO_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PP_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PRED_RD_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PRED_WR_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PPWRAP_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_TILE_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_VLD_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_VLD2_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_AVC_MV_EXT>; + clocks = <&topckgen CLK_TOP_VDEC>, + <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D4>; + clock-names = "sel", "vdec", "lat", "top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; + }; + }; + larb24: larb@1800d000 { compatible = "mediatek,mt8195-smi-larb"; reg = <0 0x1800d000 0 0x1000>;