From patchwork Mon Dec 5 14:45:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 29701 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2298651wrr; Mon, 5 Dec 2022 06:53:30 -0800 (PST) X-Google-Smtp-Source: AA0mqf6YUEdxQHL395qXW4accd92TvVLDg+V2OHsU6F+hS7wb6Csl1zusMZVpzeGKsZEucHq0coA X-Received: by 2002:a17:906:bf2:b0:7ac:a2b7:6c97 with SMTP id z18-20020a1709060bf200b007aca2b76c97mr67537616ejg.497.1670252009763; Mon, 05 Dec 2022 06:53:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670252009; cv=none; d=google.com; s=arc-20160816; b=0MD0vZU79SAVdUZHF/J+mt/umM9Lwqb2bMAdiQmP3ognotNvBI0bOmUwOOZ+j97Tbn 4tt6Wv/Te2gW8T3967V68PTzwoUn7zoFB7hvF5TzzTczZ1fJ3O3jvNxKJW2v+MO51tD7 l4ZSrG5VPLJ0hC2mm4iH8LCsCKx/Z5bltSodvCXhGD4CRCoFv0z4/dMDIAyfCxdKvkVh N1C8NqhcmF9Q9dCekaeNOuOgdlBXQSEgPDHjiOjQZe3FcTfkTpDTn4jVgKunjomFvInP nyoaBKVYRkRxBhcxPKHC5I/BvARcncaAvAgnzMhDL7hfkMj8ovFGx6y4mcPX3tGBmnZP c31A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=8wZueZhS3ooNREifS2ajqp6RU4R+sncaosBhEXeof08=; b=kDS9MhdjwyHgWyxLcaYgp1cd6TyHe5IS47CVggBR33i+gIXR8vLlH6u5Qxb5YMH83R ifyaVZN0ZQEv3HJetifpEg9V0imECezld8Mw9MV5BPCBNUqXCAu4YB4cLVKOC8Mqz/ci 9CIzu7YZ2lt6eOq3SWJ6K2unJHYG5r7jIf5O6XL6rmWAsUJbo/n5II3HxXHrocHdN6ol zCxymS2ACKyQarpt5w8AoElzJd9JiQ6RKwYDd4fMq2hCoZxkAxZBEVVHlrl1FpJaQ8wh vqEVMbyaGHEkInPDmGSbzoOxokV7m042Fj42hSDxqsmM0MJ0vGVaE9LIogIa9NuPV2oN otyQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=YlOznsoe; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ht17-20020a170907609100b0079ed0a585c2si1184753ejc.261.2022.12.05.06.53.05; Mon, 05 Dec 2022 06:53:29 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=YlOznsoe; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232149AbiLEOqV (ORCPT + 99 others); Mon, 5 Dec 2022 09:46:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49704 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231969AbiLEOqR (ORCPT ); Mon, 5 Dec 2022 09:46:17 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4CCC41B1FE; Mon, 5 Dec 2022 06:46:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1670251576; x=1701787576; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/A732PXUzOa5QEDZseaW4QKYJ4f5uZaINwwbpO826ps=; b=YlOznsoeWfXvfw00ixYArB5bTZOboFkNqaRL97SW3/kf76ms/zr5XKhk qxehEX10fyl2082DgWmGXwQgG6oA61rOsJbkXFFjXRay2hkepBRvXN+DI kyptBhMNij1iHcIxlz79pEjAfcqBuSsGH9mYDUlQOVSuFzwftyCrc2aMD 8TZMnCJfXnW/UvFC/l3BFOubilIgSPMSNv6r2jerEzX3GAemOsEqcnxS/ CK+5/wyPChp3EgBsLlrzxhCo886yMaVp7XyKsSJvvR1w3r4WeRzlfrPxx NdwpmLMioozarvU1Ye00pXHXSqt3Qw7bOTPUW5b1TYA68M0xT+NxJhJLK w==; X-IronPort-AV: E=Sophos;i="5.96,219,1665471600"; d="scan'208";a="202640917" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 05 Dec 2022 07:46:15 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 5 Dec 2022 07:46:14 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 5 Dec 2022 07:46:12 -0700 From: Conor Dooley To: , Palmer Dabbelt CC: Conor Dooley , , , , , , , , , Subject: [PATCH v2 1/3] RISC-V: clarify ISA string ordering rules in cpu.c Date: Mon, 5 Dec 2022 14:45:24 +0000 Message-ID: <20221205144525.2148448-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221205144525.2148448-1-conor.dooley@microchip.com> References: <20221205144525.2148448-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751386171617291317?= X-GMAIL-MSGID: =?utf-8?q?1751386171617291317?= While the current list of rules may have been accurate when created it now lacks some clarity in the face of isa-manual updates. Instead of trying to continuously align this rule-set with the one in the specifications, change the role of this comment. This particular comment is important, as the array it "decorates" defines the order in which the ISA string appears to userspace in /proc/cpuinfo. Re-jig and strengthen the wording to provide contributors with a set order in which to add entries & note why this particular struct needs more attention than others. While in the area, add some whitespace and tweak some wording for readability's sake. Suggested-by: Andrew Jones Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- arch/riscv/kernel/cpu.c | 49 ++++++++++++++++++++++++++++++----------- 1 file changed, 36 insertions(+), 13 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 1b9a5a66e55a..db8b16ad9342 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -144,22 +144,45 @@ arch_initcall(riscv_cpuinfo_init); .uprop = #UPROP, \ .isa_ext_id = EXTID, \ } + /* - * Here are the ordering rules of extension naming defined by RISC-V - * specification : - * 1. All extensions should be separated from other multi-letter extensions - * by an underscore. - * 2. The first letter following the 'Z' conventionally indicates the most + * The canonical order of ISA extension names in the ISA string is defined in + * chapter 27 of the unprivileged specification. + * + * Ordinarily, for in-kernel data structures, this order is unimportant but + * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo. + * + * The specification uses vague wording, such as should, when it comes to + * ordering, so for our purposes the following rules apply: + * + * 1. All multi-letter extensions must be separated from other extensions by an + * underscore. + * + * 2. Additional standard extensions (starting with 'Z') must be sorted after + * single-letter extensions and before any higher-privileged extensions. + + * 3. The first letter following the 'Z' conventionally indicates the most * closely related alphabetical extension category, IMAFDQLCBKJTPVH. - * If multiple 'Z' extensions are named, they should be ordered first - * by category, then alphabetically within a category. - * 3. Standard supervisor-level extensions (starts with 'S') should be - * listed after standard unprivileged extensions. If multiple - * supervisor-level extensions are listed, they should be ordered + * If multiple 'Z' extensions are named, they must be ordered first by + * category, then alphabetically within a category. + * + * 3. Standard supervisor-level extensions (starting with 'S') must be listed + * after standard unprivileged extensions. If multiple supervisor-level + * extensions are listed, they must be ordered alphabetically. + * + * 4. Standard machine-level extensions (starting with 'Zxm') must be listed + * after any lower-privileged, standard extensions. If multiple + * machine-level extensions are listed, they must be ordered * alphabetically. - * 4. Non-standard extensions (starts with 'X') must be listed after all - * standard extensions. They must be separated from other multi-letter - * extensions by an underscore. + * + * 5. Non-standard extensions (starting with 'X') must be listed after all + * standard extensions. If multiple non-standard extensions are listed, they + * must be ordered alphabetically. + * + * An example string following the order is: + * rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux + * + * New entries to this struct should follow the ordering rules described above. */ static struct riscv_isa_ext_data isa_ext_arr[] = { __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), From patchwork Mon Dec 5 14:45:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 29703 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2299984wrr; Mon, 5 Dec 2022 06:56:07 -0800 (PST) X-Google-Smtp-Source: AA0mqf7UQVnvXP2lEN92txNEZptu4XZoImD4bBCaq53cIP76KTtz6PO36z+1KuBx735Jj7xwLtL/ X-Received: by 2002:a17:906:3a85:b0:7ab:afd4:d7ed with SMTP id y5-20020a1709063a8500b007abafd4d7edmr2527312ejd.228.1670252167301; Mon, 05 Dec 2022 06:56:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670252167; cv=none; d=google.com; s=arc-20160816; b=YoYbcS69Er9DGKN+u+Vo52c1/AriEP4ktyPR/9GMLorp/uk5Z5pkxVNNDuZcA5JoWt 70QT44Iv+gNStD2KJCy6SReszmOLi8gkS5rYORcvGUWiOux0ufR8VZeeo0L1pkV6GxBv kcfs8/RLOlji8Gnv6WoDVWcdlTpLpOtXKLw7kzY37B06rQv73iduJcECMUf+FxrUo3qT JKZYZNbtzYcOHQOooCA12trSayUaGYEG7GqNdGe1cYy6csL/CHY5nSkq6Ct6dWEFqTxd pDB8IKixdfatAwQVw6Yfe8847sUni1GNuEYWR9WlAM5ZF7t/CXC7U9bMJzuLGkXWs7w9 40Aw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ppCcCHhoK8voR3csy0G9caxQ6PlwRkkTugN1ccYly2I=; b=rRzY5+8Pf1/oBslksp/w07R/uJ0wGwQIw+gCIjhgUGQakIDRtyrtXWZvu/J2fmnwgA 1WTUqfbY3wMxxMrPLw8x3327415eUwUVgWaQBnrYwEEd1HJ4coSs8R2RIKSwuK0JB2i4 BjvrRPZdga8XOQHIBhn3zK2rvcNL73N5rc80dxmgZPv1rgtu47kCEI+DaeM+cfMlc6es LQilbg7n0Dpx6JV9a04XS9V5oP5+sCwvl99XS1mNXK1TV7GvXqKgyl5R/AHqTk/y5ygm RJnpGSIGece8h84XgbPYwdlBmdC+dUouDBy5ToNsMJWBe8zVNSD9ZCMyH0zOS4HfJjnr kptg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=aruAvhGt; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id hq14-20020a1709073f0e00b007bf22d4e679si13276993ejc.63.2022.12.05.06.55.43; Mon, 05 Dec 2022 06:56:07 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=aruAvhGt; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232218AbiLEOq2 (ORCPT + 99 others); Mon, 5 Dec 2022 09:46:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49704 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231516AbiLEOqS (ORCPT ); Mon, 5 Dec 2022 09:46:18 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 178EE1B7A6; Mon, 5 Dec 2022 06:46:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1670251577; x=1701787577; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mR+tA9ajFYArrwEF7cxAJbYpdeZOV3FQATUmv3J86uc=; b=aruAvhGt7EqTGWKdM/2zUIIl+sJFymUrbb4HWMcHNrHkVoZ+Y9+fCGr+ R2w2T1dsGqyGO+koi9JuwUsmz2HcppbTAsUWO/4wBYQtjvb8Xmss+VyuD 2r6af/92C4++HSh6/t+rcSDMMBS/yVzU22ax4CfezOyGK9lbrRoYwJvvm pmriiPjl/LtyxCFyV+wDRYjZe+Ondgi/xK32v32JdFGN1K41GhedO5W++ BXhkZqQZ9X6hjP99E2NCTAxt1doY58+moMQr10945nslgGA02Fc0PfthT mepohx+HEobaS3f7R8MaluOpRKA/Hk6DH1uUS/rWyiyKZiLhWrODi2ihx g==; X-IronPort-AV: E=Sophos;i="5.96,219,1665471600"; d="scan'208";a="202640935" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 05 Dec 2022 07:46:17 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 5 Dec 2022 07:46:17 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 5 Dec 2022 07:46:15 -0700 From: Conor Dooley To: , Palmer Dabbelt CC: Conor Dooley , , , , , , , , , , Heiko Stuebner Subject: [PATCH v2 2/3] RISC-V: resort all extensions in consistent orders Date: Mon, 5 Dec 2022 14:45:25 +0000 Message-ID: <20221205144525.2148448-3-conor.dooley@microchip.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221205144525.2148448-1-conor.dooley@microchip.com> References: <20221205144525.2148448-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751386336595414903?= X-GMAIL-MSGID: =?utf-8?q?1751386336595414903?= Ordering between each and every list of extensions is wildly inconsistent. Per discussion on the lists pick the following policy: - The array defining order in /proc/cpuinfo follows a narrow interpretation of the ISA specifications, described in a comment immediately presiding it. - All other lists of extensions are sorted alphabetically. This will hopefully allow for easier review & future additions, and reduce conflicts between patchsets as the number of extensions grows. Link: https://lore.kernel.org/all/20221129144742.2935581-2-conor.dooley@microchip.com/ Suggested-by: Andrew Jones Reviewed-by: Andrew Jones Reviewed-by: Heiko Stuebner Signed-off-by: Conor Dooley --- arch/riscv/include/asm/hwcap.h | 12 +++++++----- arch/riscv/kernel/cpu.c | 4 ++-- arch/riscv/kernel/cpufeature.c | 6 ++++-- 3 files changed, 13 insertions(+), 9 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index b22525290073..ce522aad641a 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -51,14 +51,15 @@ extern unsigned long elf_hwcap; * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter * extensions while all the multi-letter extensions should define the next * available logical extension id. + * Entries are sorted alphabetically. */ enum riscv_isa_ext_id { RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, + RISCV_ISA_EXT_SSTC, + RISCV_ISA_EXT_SVINVAL, RISCV_ISA_EXT_SVPBMT, RISCV_ISA_EXT_ZICBOM, RISCV_ISA_EXT_ZIHINTPAUSE, - RISCV_ISA_EXT_SSTC, - RISCV_ISA_EXT_SVINVAL, RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, }; @@ -66,11 +67,12 @@ enum riscv_isa_ext_id { * This enum represents the logical ID for each RISC-V ISA extension static * keys. We can use static key to optimize code path if some ISA extensions * are available. + * Entries are sorted alphabetically. */ enum riscv_isa_ext_key { RISCV_ISA_EXT_KEY_FPU, /* For 'F' and 'D' */ - RISCV_ISA_EXT_KEY_ZIHINTPAUSE, RISCV_ISA_EXT_KEY_SVINVAL, + RISCV_ISA_EXT_KEY_ZIHINTPAUSE, RISCV_ISA_EXT_KEY_MAX, }; @@ -90,10 +92,10 @@ static __always_inline int riscv_isa_ext2key(int num) return RISCV_ISA_EXT_KEY_FPU; case RISCV_ISA_EXT_d: return RISCV_ISA_EXT_KEY_FPU; - case RISCV_ISA_EXT_ZIHINTPAUSE: - return RISCV_ISA_EXT_KEY_ZIHINTPAUSE; case RISCV_ISA_EXT_SVINVAL: return RISCV_ISA_EXT_KEY_SVINVAL; + case RISCV_ISA_EXT_ZIHINTPAUSE: + return RISCV_ISA_EXT_KEY_ZIHINTPAUSE; default: return -EINVAL; } diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index db8b16ad9342..0bf1c7f663fc 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -185,12 +185,12 @@ arch_initcall(riscv_cpuinfo_init); * New entries to this struct should follow the ordering rules described above. */ static struct riscv_isa_ext_data isa_ext_arr[] = { + __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), + __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), - __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), - __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), }; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 694267d1fe81..8a76a6ce70cf 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -199,12 +199,13 @@ void __init riscv_fill_hwcap(void) this_hwcap |= isa2hwcap[(unsigned char)(*ext)]; set_bit(*ext - 'a', this_isa); } else { + /* sorted alphabetically */ SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); + SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); + SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL); SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM); SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); - SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); - SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL); } #undef SET_ISA_EXT_MAP } @@ -284,6 +285,7 @@ static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage) * This code may also be executed before kernel relocation, so we cannot use * addresses generated by the address-of operator as they won't be valid in * this context. + * Tests, unless otherwise required, are to be added in alphabetical order. */ static u32 __init_or_module cpufeature_probe(unsigned int stage) { From patchwork Mon Dec 5 14:45:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 29702 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2299076wrr; Mon, 5 Dec 2022 06:54:15 -0800 (PST) X-Google-Smtp-Source: AA0mqf7PZyiP9dxpyqtjpM2UglAb0gWOLpSD6wScSgDJWJfmQIVn9K9wm4I2wO4mwY2wl2v9otH1 X-Received: by 2002:a05:6402:381b:b0:456:ee32:799b with SMTP id es27-20020a056402381b00b00456ee32799bmr27976600edb.2.1670252055614; Mon, 05 Dec 2022 06:54:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670252055; cv=none; d=google.com; s=arc-20160816; b=nhybLrUuF6ysbvpE4zW14Li1vPVoROdtjMdYEeCE2dE1ad0RcuIIlMZTQwQqG9E+uP 1dJxh0fjhKPfTH0ECVAN/DGGVGC+kNvwxrPYdpWxosl28GPzuBoA4uSir3twcy8r+JRl WWBto66CI8slxplgs83XEny4dW5BGiJ17XXXUMIE4zzCaoKWsZ33sCoXLS3508V7yeYQ kL9y+1PYb9wo5FaFvukILitUlpNsVSAPDeG9YTrf6zUZQCXAq1RMvjFlHABWuNr9GTSu vGdR9LtsG05yF5If3YHoC+TbP4cVOsL8fWnkzx7Vps/fgp2GbYgpTWyntGEITBDwqiv1 JUfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=NWZbETjdFs7uf791dRux30jwriT5G3vuL2KI/QpsIKc=; b=M6h0QRwkgAbndBqSn45Koxxil8bT48iB8sww/fYva4iyXE2inBu8SdFUoRQvQqZxIR FxsZZvdaUbD9hc6pezWhhUfdDRtu3U3keS+PPAru+AUcmXJ/xMu8+hFjVNa84RXalNj3 Mr4tpBkj7xHEkVV2qjeoF0Cnq+0s/ajlQYVK2tzw2/8CRvpfdLbwC8u1ebjdiwi/3Jh6 VTfiAy4n6vS5WAiyI2e3DalHTTSgFMWjgw71k3U6422SjEqCZel4bSSyx5wMLbHVOYUo HGL5E4wNcMkznoW6tRzeqXurSotXjwaw/wDr8sb3jJpzUI0ypK3xYyxEGkLuKKJDihq0 /asg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=mshFdZZv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id l14-20020a056402254e00b0046cf61af9fbsi577018edb.525.2022.12.05.06.53.49; Mon, 05 Dec 2022 06:54:15 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=mshFdZZv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232233AbiLEOqb (ORCPT + 99 others); Mon, 5 Dec 2022 09:46:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49854 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232179AbiLEOqY (ORCPT ); Mon, 5 Dec 2022 09:46:24 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B1F51B788; Mon, 5 Dec 2022 06:46:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1670251584; x=1701787584; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xa3lQ5br274pHlzqKFXObTMHjy86GvzTLCwrJSJFAKA=; b=mshFdZZvsdpyH+TXzhniEQuHZl2sUUW1EBmLfZxio/WcDoVpwNqAUGpl Pl+KNrO+7DWQ2m98pEbs+V4H+NJCaXLbOFQWqfbbHUH5c1qh5BmdduxAs F/Z8BSpanbtH/w/rU1qAzjVrOXJ4ssvT2Hf0UwfVYS9e6Mhl87gX3gQ8s Zx7t8xLQrtH+PcIeclo+6yzQPi/CCPTnU1ED0n5lRBsDa4MVU1Sd18IDW 9GK3n+scoFQh3Ohv1GR8YggehZx+5COOxf1jrUnjt+WI0S8FZDrNVykev PiqiCXL14IGa95xQdYtgXyrCYLpLOb4IEaAYPl3065nac/CC7/9PgtsuQ Q==; X-IronPort-AV: E=Sophos;i="5.96,219,1665471600"; d="scan'208";a="202640941" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 05 Dec 2022 07:46:20 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 5 Dec 2022 07:46:19 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 5 Dec 2022 07:46:17 -0700 From: Conor Dooley To: , Palmer Dabbelt CC: Conor Dooley , , , , , , , , , Subject: [PATCH v2 3/3] Documentation: riscv: add a section about ISA string ordering in /proc/cpuinfo Date: Mon, 5 Dec 2022 14:45:26 +0000 Message-ID: <20221205144525.2148448-4-conor.dooley@microchip.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221205144525.2148448-1-conor.dooley@microchip.com> References: <20221205144525.2148448-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751386219858050747?= X-GMAIL-MSGID: =?utf-8?q?1751386219858050747?= The RISC-V specs are permissive in what they allow as the ISA string, but how we output this to userspace in /proc/cpuinfo is quasi uABI. Formalise this as part of the uABI, by documenting the list of rules we use at this point in time. Signed-off-by: Conor Dooley --- Documentation/riscv/uabi.rst | 42 ++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/Documentation/riscv/uabi.rst b/Documentation/riscv/uabi.rst index 21a82cfb6c4d..2ebec4c52230 100644 --- a/Documentation/riscv/uabi.rst +++ b/Documentation/riscv/uabi.rst @@ -3,4 +3,46 @@ RISC-V Linux User ABI ===================== +ISA string ordering in /proc/cpuinfo +------------------------------------ + +The canonical order of ISA extension names in the ISA string is defined in +chapter 27 of the unprivileged specification. +The specification uses vague wording, such as should, when it comes to ordering, +so for our purposes the following rules apply: + +#. Single-letter extensions come first, in canonical order. + The canonical order is "IMAFDQLCBKJTPVH". + +#. All multi-letter extensions will be separated from other extensions by an + underscore. + +#. Additional standard extensions (starting with 'Z') will be sorted after + single-letter extensions and before any higher-privileged extensions. + +#. For additional standard extensions, the first letter following the 'Z' + conventionally indicates the most closely related alphabetical + extension category. If multiple 'Z' extensions are named, they will be ordered + first by category, in canonical order, as listed above, then alphabetically + within a category. + +#. Standard supervisor-level extensions (starting with 'S') will be listed + after standard unprivileged extensions. If multiple supervisor-level + extensions are listed, they will be ordered alphabetically. + +#. Standard machine-level extensions (starting with 'Zxm') will be listed + after any lower-privileged, standard extensions. If multiple machine-level + extensions are listed, they will be ordered alphabetically. + +#. Non-standard extensions (starting with 'X') will be listed after all standard + extensions. If multiple non-standard extensions are listed, they will be + ordered alphabetically. + +An example string following the order is:: + + rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux + +Misaligned accesses +------------------- + Misaligned accesses are supported in userspace, but they may perform poorly.