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Peter Anvin" Subject: [PATCH 1/2] x86/pat: fix TDX guest PAT initialization Date: Mon, 5 Dec 2022 09:04:32 +0100 Message-Id: <20221205080433.16643-2-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221205080433.16643-1-jgross@suse.com> References: <20221205080433.16643-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751360695610179118?= X-GMAIL-MSGID: =?utf-8?q?1751360695610179118?= With the decoupling of PAT and MTRR initialization, PAT will be used even with MTRRs disabled. This seems to break booting up as TDX guest, as the recommended sequence to set the PAT MSR across CPUs can't work in TDX guests due to disabling caches via setting CR0.CD isn't allowed in TDX mode. This is an inconsistency in the Intel documentation between the SDM and the TDX specification. For now handle TDX mode the same way as Xen PV guest mode by just accepting the current PAT MSR setting without trying to modify it. Signed-off-by: Juergen Gross Acked-by: Kirill A. Shutemov --- arch/x86/mm/pat/memtype.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/x86/mm/pat/memtype.c b/arch/x86/mm/pat/memtype.c index 9aab17d660cd..4e50add760ad 100644 --- a/arch/x86/mm/pat/memtype.c +++ b/arch/x86/mm/pat/memtype.c @@ -296,8 +296,12 @@ void __init pat_bp_init(void) /* * Xen PV doesn't allow to set PAT MSR, but all cache modes are * supported. + * When running as TDX guest setting the PAT MSR won't work either + * due to the requirement to set CR0.CD when doing so. Rely on + * firmware to have set the PAT MSR correctly. */ - if (pat_disabled || cpu_feature_enabled(X86_FEATURE_XENPV)) { + if (pat_disabled || cpu_feature_enabled(X86_FEATURE_XENPV) || + cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) { init_cache_modes(pat_msr_val); return; } From patchwork Mon Dec 5 08:04:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 29583 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2122005wrr; Mon, 5 Dec 2022 00:08:37 -0800 (PST) X-Google-Smtp-Source: AA0mqf7IBf1HHOOMX7gqSsbL5lE5KebuBUDTBhp/CSG4R5ZAHaDLoEA2iXWiRtHAml2UpGvDSQC8 X-Received: by 2002:a17:907:a801:b0:7c0:e060:e819 with SMTP id vo1-20020a170907a80100b007c0e060e819mr5949604ejc.763.1670227716996; Mon, 05 Dec 2022 00:08:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670227716; cv=none; d=google.com; s=arc-20160816; b=hXjAxGtUjxXlyV6HQnh3+sY2vxGTpQwguHnXlpK0hLPIBbwQw/R96qTHTzva72b0uN bx1NQFsT6Rat3TQBu6RBCEJzsC+OcMP9tqDVv2h8pBL1hOq0I6m8aHb8oKZHkc5/2cSA pBp8YDj/czi8dwJpo8JJCiqcsrRsHXUQ2uGsoFsDoeMXUN+m/8L7oNeDLbEcv4bprn+F scQJwuh07aT+GthlYss60uMO2xE0jONTOhulfAMH2rkrSQxs+WdPLgqiwr3s3f/tceWL AuI4VylhRQFZLxhC69Bnc3JzZqiQCQEG2Xxdg2+uZZKuNuX6YYuPQRz1l0kRHDSrXJCf CcvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=yMianIWALJeEq31IWXfqs8+ymd+X0ZqlQ5HivhuglU8=; b=dXN6nl322kWeYGB0e6FGTJzaeDvzSovhgbG0qX3/KtnpoCSWrwIYkCvDu8pTBa5E2G zJStoQ6QGnMYaJhUObYfCJN28O/HGf0DwUohkff1Q4be34qSpmHX9eBImAWTGPijxR8p M/phmKzTn54gVfOiymsmPWdHYSpFusfZqjEmDgZrIMhXSqinsbQGbKDru9MyFMX3x85r NvVf7w67yBzFJykkRd3udWCJtZu4s09A3tfC80oq7XnwyEwUyU4ANxLXYPZkLtZK5PKb 98sBoW8JUR5VP1DJqJ1rSgjbRx4/ulNWRiQhNlOgP/mdkKl5YdPe4VaQ2E1xS2chRoLo TBYA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b=O0TiN9vK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=suse.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" Subject: [PATCH 2/2] x86/mtrr: make message for disabled MTRRs more descriptive Date: Mon, 5 Dec 2022 09:04:33 +0100 Message-Id: <20221205080433.16643-3-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221205080433.16643-1-jgross@suse.com> References: <20221205080433.16643-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751360698472546887?= X-GMAIL-MSGID: =?utf-8?q?1751360698472546887?= Instead of just saying "Disabled" when MTRRs are disabled for any reason, tell what is disabled and why. Signed-off-by: Juergen Gross Acked-by: Kirill A. Shutemov --- arch/x86/kernel/cpu/mtrr/mtrr.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtrr.c index 6432abccbf56..94d5739758ba 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -630,6 +630,7 @@ int __initdata changed_by_mtrr_cleanup; void __init mtrr_bp_init(void) { u32 phys_addr; + const char *why = "(not available)"; phys_addr = 32; @@ -705,12 +706,13 @@ void __init mtrr_bp_init(void) changed_by_mtrr_cleanup = mtrr_cleanup(phys_addr); } else { mtrr_if = NULL; + why = "by BIOS"; } } } if (!mtrr_enabled()) - pr_info("Disabled\n"); + pr_info("MTRRs disabled %s\n", why); } /**