From patchwork Fri Dec 2 15:12:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 28936 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp916202wrr; Fri, 2 Dec 2022 07:16:33 -0800 (PST) X-Google-Smtp-Source: AA0mqf5G8twZqBLm55rMwmB4xAe3rZFG9QNMIju2kk0tsoePC+9YMOyfTTCs1H1aXDiGd3CY+JIp X-Received: by 2002:a05:6402:35cf:b0:469:5ee9:4a76 with SMTP id z15-20020a05640235cf00b004695ee94a76mr46023479edc.405.1669994193444; Fri, 02 Dec 2022 07:16:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669994193; cv=none; d=google.com; s=arc-20160816; b=oW9nVacnnod4j8a1QOHPw1/2LwZ2VoxQoa8EYX8daGE75XigZU659UYdMhU+1HoizJ NfeWuwo8Sc+H0RGaVxuSF1uNUGE34UPdicnLOeJy2km04RCaLiizg6PJHr+xcDWMIN3f SMtFBLBW/E5TkvuB5EiWyafnIv4z9d2wGZBCCPWBTQb32ZdyHi3G62rmzgAKscrQvGSi SlpdWq1cegMGsiqKFbTRq6OjiT7LIPOgWi92UIkQP71nEfEePlwCcrsmU9g97Nv9l6/O dUMy76guw/BLajIGlX8Fyc93oxQyvRJw34gmD38wMiCZaX/eJzW43B7v/r/v+EXfA97C sipA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=qG7sQTY2fpVZirjAuGQmiko+Gx7p3pYVJOqz3hGWL/g=; b=lWturfH6claUqd9kqrhuqd+GtNNr40CC9ggWJR+Sq9VR6/qXN8C9Km6k5o7/NEPdI9 jJQdpRSJ34RJtsMQRKbj1Apgla9bJN/bMIUtvqzWahj58u2+Ppc4PKUyybcijT8cXcUA 7pWx/fGrCh4q4+qDhsFWi78aLuUuAnrIYewbYQ/RRS6Y1UJa8mKbaemNGpuu26ya0Otu +rMAxtcj02HaWYZizD1jFGpPiWiHrH/n5fqYO/fZZQ8+0Ybt2Lb69mX9tWP3/d6k4zQ3 ii/MlqHZ04CT9WW1WKZedTTVaAzWcsiLuSUNuo8c7SF7v+HYUvVq2h6Qi/Nqlqihag8k htnw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@walle.cc header.s=mail2022082101 header.b=nWhpormn; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=walle.cc Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id e9-20020aa7d7c9000000b004617bf36c3csi5833687eds.308.2022.12.02.07.16.06; Fri, 02 Dec 2022 07:16:33 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@walle.cc header.s=mail2022082101 header.b=nWhpormn; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=walle.cc Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233730AbiLBPMR (ORCPT + 99 others); Fri, 2 Dec 2022 10:12:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42466 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233567AbiLBPMN (ORCPT ); Fri, 2 Dec 2022 10:12:13 -0500 Received: from mail.3ffe.de (0001.3ffe.de [159.69.201.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D01F9B78A; Fri, 2 Dec 2022 07:12:12 -0800 (PST) Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail.3ffe.de (Postfix) with ESMTPSA id 7E361124C; Fri, 2 Dec 2022 16:12:10 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2022082101; t=1669993930; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qG7sQTY2fpVZirjAuGQmiko+Gx7p3pYVJOqz3hGWL/g=; b=nWhpormn9zVgFEJfIKZJprMMn+T+ky0Z81lsWbdoAr95O34jB+Lr/iKBZEfvSCHuKgBKhu rIeoVyu6bImhacHkBc5OLXdekRkkp3Mipm+r24gENkBP5Ijn+G9tMD0kGwy87Nansih6xv DSQuf0O+tmQ3OlYRJUpKSRwJxd8YyxBWaizLkXyDyl3tEdv4VYGAtvAZXj2GlNIUmxMrwc +6/mQ70cKrU7dHfunXJAQepu3FuUm5sGGt6EXKIMqHkUD4dNcUCFL+bYq0+L08elcluJbU kOMMrW+doHYPg3xWoCpv8k+s4gX1Klf3aYlWXZDf6ZyIgyropyYOQbmZ5tvhrg== From: Michael Walle To: Xu Liang , Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Michael Walle Subject: [PATCH net-next v1 1/4] net: phy: mxl-gpy: add MDINT workaround Date: Fri, 2 Dec 2022 16:12:01 +0100 Message-Id: <20221202151204.3318592-2-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221202151204.3318592-1-michael@walle.cc> References: <20221202151204.3318592-1-michael@walle.cc> MIME-Version: 1.0 X-Spam: Yes X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751115831756595995?= X-GMAIL-MSGID: =?utf-8?q?1751115831756595995?= At least the GPY215B and GPY215C has a bug where it is still driving the interrupt line (MDINT) even after the interrupt status register is read and its bits are cleared. This will cause an interrupt storm. Although the MDINT is multiplexed with a GPIO pin and theoretically we could switch the pinmux to GPIO input mode, this isn't possible because the access to this register will stall exactly as long as the interrupt line is asserted. We exploit this very fact and just read a random internal register in our interrupt handler. This way, it will be delayed until the external interrupt line is released and an interrupt storm is avoided. The internal register access via the mailbox was deduced by looking at the downstream PHY API because the datasheet doesn't mention any of this. Signed-off-by: Michael Walle --- drivers/net/phy/mxl-gpy.c | 83 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/drivers/net/phy/mxl-gpy.c b/drivers/net/phy/mxl-gpy.c index 0ff7ef076072..20e610dda891 100644 --- a/drivers/net/phy/mxl-gpy.c +++ b/drivers/net/phy/mxl-gpy.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -81,6 +82,14 @@ #define VSPEC1_TEMP_STA 0x0E #define VSPEC1_TEMP_STA_DATA GENMASK(9, 0) +/* Mailbox */ +#define VSPEC1_MBOX_DATA 0x5 +#define VSPEC1_MBOX_ADDRLO 0x6 +#define VSPEC1_MBOX_CMD 0x7 +#define VSPEC1_MBOX_CMD_ADDRHI GENMASK(7, 0) +#define VSPEC1_MBOX_CMD_RD (0 << 8) +#define VSPEC1_MBOX_CMD_READY BIT(15) + /* WoL */ #define VPSPEC2_WOL_CTL 0x0E06 #define VPSPEC2_WOL_AD01 0x0E08 @@ -88,7 +97,15 @@ #define VPSPEC2_WOL_AD45 0x0E0A #define WOL_EN BIT(0) +/* Internal registers, access via mbox */ +#define REG_GPIO0_OUT 0xd3ce00 + struct gpy_priv { + struct phy_device *phydev; + + /* serialize mailbox acesses */ + struct mutex mbox_lock; + u8 fw_major; u8 fw_minor; }; @@ -198,6 +215,40 @@ static int gpy_hwmon_register(struct phy_device *phydev) } #endif +static int gpy_mbox_read(struct phy_device *phydev, u32 addr) +{ + struct gpy_priv *priv = phydev->priv; + int val, ret; + u16 cmd; + + mutex_lock(&priv->mbox_lock); + + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_ADDRLO, + addr); + if (ret) + goto out; + + cmd = VSPEC1_MBOX_CMD_RD; + cmd |= FIELD_PREP(VSPEC1_MBOX_CMD_ADDRHI, addr >> 16); + + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_CMD, cmd); + if (ret) + goto out; + + ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, + VSPEC1_MBOX_CMD, val, + (val & VSPEC1_MBOX_CMD_READY), + 500, 10000, false); + if (ret) + goto out; + + ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_DATA); + +out: + mutex_unlock(&priv->mbox_lock); + return ret; +} + static int gpy_config_init(struct phy_device *phydev) { int ret; @@ -212,6 +263,13 @@ static int gpy_config_init(struct phy_device *phydev) return ret < 0 ? ret : 0; } +static bool gpy_has_broken_mdint(struct phy_device *phydev) +{ + /* At least these PHYs are known to have broken interrupt handling */ + return phydev->drv->phy_id == PHY_ID_GPY215B || + phydev->drv->phy_id == PHY_ID_GPY215C; +} + static int gpy_probe(struct phy_device *phydev) { struct device *dev = &phydev->mdio.dev; @@ -228,7 +286,9 @@ static int gpy_probe(struct phy_device *phydev) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; + priv->phydev = phydev; phydev->priv = priv; + mutex_init(&priv->mbox_lock); fw_version = phy_read(phydev, PHY_FWV); if (fw_version < 0) @@ -574,6 +634,29 @@ static irqreturn_t gpy_handle_interrupt(struct phy_device *phydev) if (!(reg & PHY_IMASK_MASK)) return IRQ_NONE; + /* The PHY might leave the interrupt line asserted even after PHY_ISTAT + * is read. To avoid interrupt storms, delay the interrupt handling as + * long as the PHY drives the interrupt line. An internal bus read will + * stall as long as the interrupt line is asserted, thus just read a + * random register here. + * Because we cannot access the internal bus at all while the interrupt + * is driven by the PHY, there is no way to make the interrupt line + * unstuck (e.g. by changing the pinmux to GPIO input) during that time + * frame. Therefore, polling is the best we can do and won't do any more + * harm. + * It was observed that this bug happens on link state and link speed + * changes on a GPY215B and GYP215C independent of the firmware version + * (which doesn't mean that this list is exhaustive). + */ + if (gpy_has_broken_mdint(phydev) && + (reg & (PHY_IMASK_LSTC | PHY_IMASK_LSPC))) { + reg = gpy_mbox_read(phydev, REG_GPIO0_OUT); + if (reg < 0) { + phy_error(phydev); + return IRQ_NONE; + } + } + phy_trigger_machine(phydev); return IRQ_HANDLED; From patchwork Fri Dec 2 15:12:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 28937 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp916252wrr; Fri, 2 Dec 2022 07:16:39 -0800 (PST) X-Google-Smtp-Source: AA0mqf7GljtZR3PpECS4ThBwjI8xwqp2AEFccAnLRcDXh80mqBq2Xeh/fhaCQzd3KUi0MxgYBeZc X-Received: by 2002:a17:907:c242:b0:7c0:b44d:92b2 with SMTP id tj2-20020a170907c24200b007c0b44d92b2mr6242921ejc.754.1669994199214; Fri, 02 Dec 2022 07:16:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669994199; cv=none; d=google.com; s=arc-20160816; b=llrcoyYaR6gUuyoMQPFyfdKKxbqH/ksaevrWUGkk+sCa0zgZ8Vq9qBY7OqkMYLQw2a w8PKD1czpa+nQUA0JBia4ajq4WiALGcSs/daThtT6nETvR3tt/jZD5OwjnRhkN82eCAy k8drtrWATKNejlrX2XIPlwhUZpJmjNZoEFzVXrLUCdCXGiODGN7TybOMo3SOZkEZdwe+ l5nzUtsF/Irf1VBSqcnbbW/7ZrgammDDlCT20rI8AL+5yxPIQu4o0pVCxeSWGky3Wgyi bJHSDDuBeZN53TMBO9Eyy+pZ2qOrEwoUfATboXG6ZjzKEhYEN0Rw54CwCX/9wQaFw0sk B9PA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Ryyz8/ynnKevChebtMryHbd9slV8Kyps8Up1I1RJ+G4=; b=oZ2poj0w0HMJ+884XYI7izu3xRVNKOJldCpvC7NV+f4k0B1giOhBKhKrF6zPxm3zvS k/yVUFLZu3MZ26yNbVZSllOu9+1beU28LuunhB/iMME+4nsdeDYsYoyKBRu8uz0DvdBW lMfw21STFRvzt7pRGNzew+Ey4t1PtgnJvzKNgyHdSk1SIZaX/VWg53LF1eOgx5d6iAoB WK9WQMti8uEwjBC0cyKQDBlYCKMSk7oXpVJlZfGVp92spGRqwCQAmfy1TJRQ+QrhPPo4 CuBz5slBBO/FJR0wZvvI7kLoMhy4vVXJ/6nSh9pV1eUacTDmF1MujLH534mrqJ0mcgSs Xp5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@walle.cc header.s=mail2022082101 header.b=cacZUseS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=walle.cc Received: from out1.vger.email (out1.vger.email. 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(unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail.3ffe.de (Postfix) with ESMTPSA id 2182715CC; Fri, 2 Dec 2022 16:12:11 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2022082101; t=1669993931; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Ryyz8/ynnKevChebtMryHbd9slV8Kyps8Up1I1RJ+G4=; b=cacZUseSbJSKJzQHS7+s92sPKYQWE/4BXysE46NM5BH0FOfFA6l+DDJPqfR0xtPg2nFvkr ezpavx1GTaB2krxRTtMe/1sQQouvQtl1QGFAejN13A4QG8gyVuRoqMIzJDnTTtWYw99yih Ol2EaQNN21HadhqoMe1igvlQnglaSufCZiUHXJsD/BWoI2P+ZJJq2JFvdJAPU3eTZFmCMp 5tlLiKRAcny7BpGn7z1RUWhPF+x+jQ8aqKSsVz5uAxun08LotDrzViXyJYni+KIciIYrwj GfL02MZMMgNk8DbzKk7cMK9C1UUTfuPFHD0Tk7aGHyAbQ5k4v6+lOJZU09okzg== From: Michael Walle To: Xu Liang , Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Michael Walle Subject: [PATCH net-next v1 2/4] dt-bindings: vendor-prefixes: add MaxLinear Date: Fri, 2 Dec 2022 16:12:02 +0100 Message-Id: <20221202151204.3318592-3-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221202151204.3318592-1-michael@walle.cc> References: <20221202151204.3318592-1-michael@walle.cc> MIME-Version: 1.0 X-Spam: Yes X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751115837702786116?= X-GMAIL-MSGID: =?utf-8?q?1751115837702786116?= MaxLinear is a manufacturer of integrated circuits. https://www.maxlinear.com Signed-off-by: Michael Walle Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 10c178d97b02..ae13a8776364 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -773,6 +773,8 @@ patternProperties: description: MaxBotix Inc. "^maxim,.*": description: Maxim Integrated Products + "^maxlinear,.*": + description: MaxLinear Inc. "^mbvl,.*": description: Mobiveil Inc. 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Michael Walle Subject: [PATCH net-next v1 3/4] dt-bindings: net: phy: add MaxLinear GPY2xx bindings Date: Fri, 2 Dec 2022 16:12:03 +0100 Message-Id: <20221202151204.3318592-4-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221202151204.3318592-1-michael@walle.cc> References: <20221202151204.3318592-1-michael@walle.cc> MIME-Version: 1.0 X-Spam: Yes X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751115856962267767?= X-GMAIL-MSGID: =?utf-8?q?1751115856962267767?= Add the device tree bindings for the MaxLinear GPY2xx PHYs. Signed-off-by: Michael Walle --- Is the filename ok? I was unsure because that flag is only for the GPY215 for now. But it might also apply to others. Also there is no compatible string, so.. .../bindings/net/maxlinear,gpy2xx.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/maxlinear,gpy2xx.yaml diff --git a/Documentation/devicetree/bindings/net/maxlinear,gpy2xx.yaml b/Documentation/devicetree/bindings/net/maxlinear,gpy2xx.yaml new file mode 100644 index 000000000000..d71fa9de2b64 --- /dev/null +++ b/Documentation/devicetree/bindings/net/maxlinear,gpy2xx.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/maxlinear,gpy2xx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MaxLinear GPY2xx PHY + +maintainers: + - Andrew Lunn + - Michael Walle + +allOf: + - $ref: ethernet-phy.yaml# + +properties: + maxlinear,use-broken-interrupts: + description: | + Interrupts are broken on some GPY2xx PHYs in that they keep the + interrupt line asserted even after the interrupt status register is + cleared. Thus it is blocking the interrupt line which is usually bad + for shared lines. By default interrupts are disabled for this PHY and + polling mode is used. If one can live with the consequences, this + property can be used to enable interrupt handling. + + Affected PHYs (as far as known) are GPY215B and GPY215C. + type: boolean + +dependencies: + maxlinear,use-broken-interrupts: [ interrupts ] + +unevaluatedProperties: false + +examples: + - | + ethernet { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&intc 0>; + maxlinear,use-broken-interrupts; + }; + }; + +... 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(unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail.3ffe.de (Postfix) with ESMTPSA id BC8662008; Fri, 2 Dec 2022 16:12:12 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2022082101; t=1669993932; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9N5iGN9naDmEHyePTLp/VNDqNAqfYj5SwKQDYp+5n08=; b=ukgDRQFSLv9COkH21ixYjveituhMhPvZ2feOojDvvWOAcpBbwvbMfJ5GanDphDxuiX4MNN e1wKUbMydRsnmvjpgJlWEkEIIKpYntMtawxyOLpesfv7wpKcstyAj7Q5+PTK91rTEhE2pc qQRRQNVk59seNeC6/8zXqYF1jvN0BLMh66VRNbyBJ2wRMHm2dFYzARIWO/E1bm0SipIOt4 agiwA2bA2reTHb80H+vUaZ9ynVC0Ci5jaCMRX30CVx4QD0dsMmc7HvX2bFn3lzWXJN4Bfu 13j7fBYlterynoHWa+2kGIyR1ZiI0a0hikVoJiBljEiQQsgY6Hs4Rn6K6vYbmg== From: Michael Walle To: Xu Liang , Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Michael Walle Subject: [PATCH net-next v1 4/4] net: phy: mxl-gpy: disable interrupts on GPY215 by default Date: Fri, 2 Dec 2022 16:12:04 +0100 Message-Id: <20221202151204.3318592-5-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221202151204.3318592-1-michael@walle.cc> References: <20221202151204.3318592-1-michael@walle.cc> MIME-Version: 1.0 X-Spam: Yes X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751115872250528257?= X-GMAIL-MSGID: =?utf-8?q?1751115872250528257?= The interrupts on the GPY215B and GPY215C are broken and the only viable fix is to disable them altogether. There is still the possibilty to opt-in via the device tree. Signed-off-by: Michael Walle --- drivers/net/phy/mxl-gpy.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/phy/mxl-gpy.c b/drivers/net/phy/mxl-gpy.c index 20e610dda891..edb8cd8313b0 100644 --- a/drivers/net/phy/mxl-gpy.c +++ b/drivers/net/phy/mxl-gpy.c @@ -12,6 +12,7 @@ #include #include #include +#include #include /* PHY ID */ @@ -290,6 +291,10 @@ static int gpy_probe(struct phy_device *phydev) phydev->priv = priv; mutex_init(&priv->mbox_lock); + if (gpy_has_broken_mdint(phydev) && + !device_property_present(dev, "maxlinear,use-broken-interrupts")) + phydev->irq = PHY_POLL; + fw_version = phy_read(phydev, PHY_FWV); if (fw_version < 0) return fw_version;