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Fri, 2 Dec 2022 01:50:24 -0600 From: Perry Yuan To: , , , CC: , , , , , , , , Subject: [PATCH v6 01/11] ACPI: CPPC: Add AMD pstate energy performance preference cppc control Date: Fri, 2 Dec 2022 15:47:09 +0800 Message-ID: <20221202074719.623673-2-perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202074719.623673-1-perry.yuan@amd.com> References: <20221202074719.623673-1-perry.yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT025:EE_|CY5PR12MB6249:EE_ X-MS-Office365-Filtering-Correlation-Id: cbcde4cd-d8c4-4a5c-89b3-08dad439e191 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sr4Ehlko3rcc1iJmaaEgublliActrU9pJXDkaqFj7GEfKGIidGma5RnhSlr1HEaa8k0Ld1BFEPW3h8cvPbtZe1krAIuoqnfNKjEKjDSisdOxGQARsA9mcnGiass7joZYfC2GNp8IVPFaoFru4cb1D1WI2ILhnHtXMXKwStFjLBbeTRu/G1EJjjEVcdRlvHau4prg9x4fVg+Z6vSSPgrAZ40fGxAxXyMX4OwGT8WFvjKp7e0TIjroRRAK8nIAbuPBxQMRzLO33avHH8yAaouVpveQP57M+INP5eds1iTXX/3WD3CtcdK5xA9xsqNgoyNLhXY1N3uJ6UnIrlx0mXKpGNplgJz9WgaKvPm5oFNDXhqRqL7UzmC1LKL9YCbSrWRGw1tRUt9uHSTeTsxBS0A69U/flCjn7yN+VQ39ai3yP5sKixFYkvCz6v21+HwY5jn5skC6dywrzX6W/H+tMtx7/7DqZdlNTj59Sq43c6UiZQ+kZHdFrktwNSivyHGLxxIyaVnC8ynNO7XGsj7rjVpLsowyz/AxglY4yh+RnVP6fH4PBah8nhPkGffvv0bdRmW9OjK7VJRHslR0E/Z/A0eTl7AI7k/FExju+PBR485Z3Gyp17MyvUjW4CjBnKAZlKnaFsiDHr5lSKaA7Vobv39wgSLxE6Ke9WLj0M3Wus9dcblC91W1pvYSXLUV47YiadgmhaYo6luPOF7v+Fr2oUQflJxdjnd0yWXkh67M5NMhNJw= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(39860400002)(376002)(346002)(396003)(451199015)(36840700001)(46966006)(40470700004)(8936002)(2906002)(44832011)(81166007)(36860700001)(40480700001)(40460700003)(86362001)(41300700001)(36756003)(186003)(426003)(82310400005)(54906003)(478600001)(336012)(356005)(82740400003)(16526019)(70206006)(1076003)(26005)(5660300002)(83380400001)(2616005)(316002)(8676002)(6666004)(47076005)(4326008)(7696005)(70586007)(110136005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Dec 2022 07:50:28.8201 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cbcde4cd-d8c4-4a5c-89b3-08dad439e191 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT025.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6249 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751087900820483626?= X-GMAIL-MSGID: =?utf-8?q?1751087900820483626?= From: Perry Yuan Add support for setting and querying EPP preferences to the generic CPPC driver. This enables downstream drivers such as amd-pstate to discover and use these values In order to get EPP worked, cppc_get_epp_caps() will query EPP preference value and cppc_set_epp_perf() will set EPP new value. Before the EPP works, pstate driver will use cppc_set_auto_epp() to enable EPP function from firmware firstly. Signed-off-by: Perry Yuan --- drivers/acpi/cppc_acpi.c | 114 +++++++++++++++++++++++++++++++++++++-- include/acpi/cppc_acpi.h | 12 +++++ 2 files changed, 121 insertions(+), 5 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 093675b1a1ff..37fa75f25f62 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1093,6 +1093,9 @@ static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf) { struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); struct cpc_register_resource *reg; + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); + struct cppc_pcc_data *pcc_ss_data = NULL; + int ret = -EINVAL; if (!cpc_desc) { pr_debug("No CPC descriptor for CPU:%d\n", cpunum); @@ -1102,10 +1105,6 @@ static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf) reg = &cpc_desc->cpc_regs[reg_idx]; if (CPC_IN_PCC(reg)) { - int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); - struct cppc_pcc_data *pcc_ss_data = NULL; - int ret = 0; - if (pcc_ss_id < 0) return -EIO; @@ -1125,7 +1124,7 @@ static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf) cpc_read(cpunum, reg, perf); - return 0; + return ret; } /** @@ -1365,6 +1364,111 @@ int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) } EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs); +/** + * cppc_get_epp_caps - Get the energy preference register value. + * @cpunum: CPU from which to get epp preference level. + * @perf_caps: Return address. + * + * Return: 0 for success, -EIO otherwise. + */ +int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps) +{ + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); + struct cpc_register_resource *energy_perf_reg; + u64 energy_perf; + + if (!cpc_desc) { + pr_debug("No CPC descriptor for CPU:%d\n", cpunum); + return -ENODEV; + } + + energy_perf_reg = &cpc_desc->cpc_regs[ENERGY_PERF]; + + if (!CPC_SUPPORTED(energy_perf_reg)) + pr_warn_once("energy perf reg update is unsupported!\n"); + + if (CPC_IN_PCC(energy_perf_reg)) { + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); + struct cppc_pcc_data *pcc_ss_data = NULL; + int ret = 0; + + if (pcc_ss_id < 0) + return -ENODEV; + + pcc_ss_data = pcc_data[pcc_ss_id]; + + down_write(&pcc_ss_data->pcc_lock); + + if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) { + cpc_read(cpunum, energy_perf_reg, &energy_perf); + perf_caps->energy_perf = energy_perf; + } else { + ret = -EIO; + } + + up_write(&pcc_ss_data->pcc_lock); + + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(cppc_get_epp_caps); + +/* + * Set Energy Performance Preference Register value through + * Performance Controls Interface + */ +int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable) +{ + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); + struct cpc_register_resource *epp_set_reg; + struct cpc_register_resource *auto_sel_reg; + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); + struct cppc_pcc_data *pcc_ss_data = NULL; + int ret = -EINVAL; + + if (!cpc_desc) { + pr_debug("No CPC descriptor for CPU:%d\n", cpu); + return -ENODEV; + } + + auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; + epp_set_reg = &cpc_desc->cpc_regs[ENERGY_PERF]; + + if (CPC_IN_PCC(epp_set_reg) || CPC_IN_PCC(auto_sel_reg)) { + if (pcc_ss_id < 0) { + pr_debug("Invalid pcc_ss_id\n"); + return -ENODEV; + } + + if (CPC_SUPPORTED(auto_sel_reg)) { + ret = cpc_write(cpu, auto_sel_reg, enable); + if (ret) + return ret; + } + + if (CPC_SUPPORTED(epp_set_reg)) { + ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf); + if (ret) + return ret; + } + + pcc_ss_data = pcc_data[pcc_ss_id]; + + down_write(&pcc_ss_data->pcc_lock); + /* after writing CPC, transfer the ownership of PCC to platform */ + ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE); + up_write(&pcc_ss_data->pcc_lock); + } else { + ret = -ENOTSUPP; + pr_debug("_CPC in PCC is not supported\n"); + } + + return ret; +} +EXPORT_SYMBOL_GPL(cppc_set_epp_perf); + /** * cppc_set_enable - Set to enable CPPC on the processor by writing the * Continuous Performance Control package EnableRegister field. diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index c5614444031f..a45bb876a19c 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -108,12 +108,14 @@ struct cppc_perf_caps { u32 lowest_nonlinear_perf; u32 lowest_freq; u32 nominal_freq; + u32 energy_perf; }; struct cppc_perf_ctrls { u32 max_perf; u32 min_perf; u32 desired_perf; + u32 energy_perf; }; struct cppc_perf_fb_ctrs { @@ -149,6 +151,8 @@ extern bool cpc_ffh_supported(void); extern bool cpc_supported_by_cpu(void); extern int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val); extern int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val); +extern int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps); +extern int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable); #else /* !CONFIG_ACPI_CPPC_LIB */ static inline int cppc_get_desired_perf(int cpunum, u64 *desired_perf) { @@ -202,6 +206,14 @@ static inline int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val) { return -ENOTSUPP; } +static inline int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable) +{ + return -ENOTSUPP; +} +static inline int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps) +{ + return -ENOTSUPP; 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Fri, 2 Dec 2022 01:50:28 -0600 From: Perry Yuan To: , , , CC: , , , , , , , , Subject: [PATCH v6 02/11] Documentation: amd-pstate: add EPP profiles introduction Date: Fri, 2 Dec 2022 15:47:10 +0800 Message-ID: <20221202074719.623673-3-perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202074719.623673-1-perry.yuan@amd.com> References: <20221202074719.623673-1-perry.yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT065:EE_|DM6PR12MB4911:EE_ X-MS-Office365-Filtering-Correlation-Id: 3a73cf73-2b3c-4731-9b24-08dad439e525 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: W1lJuE/DxaemZlGl7Jq0QKGAedRxKiOJ/Q3G9eHCucPAVBs6PUT1DtHhxlzivXXm/bkTOI0CNxh8B3YP6fAncOhmZYGvLeyxC9WMxHENu5Ez9anBXrg7cpS+AXNoCKVB8A8bI9WItHHN1OSGsNEuue+uPArOwaNNPlmhSsyuPrpswjtQmR4CyP5vftZG3vYRy98wcPZKU5Kt3oOF3RY6vyPlPu3X11VcYrXcRMbUepW5qPEfVTC+T4Ik4uVw4fdr1CGi8xSJ1iaUjmvO2zpccypQQWP3F7Y7GwaIbJqu6I0NzsJR3oe8HinRz4CIEBbU9M7hm6yIk1TeRYfh4hYiLeaCnqMN3Wu3a1wR5wymqnogZdWK+u6G7itTVSAfJeqhmnDqwtMqVVIcrPIQR5+NraX0/dHm77le1gObYlyX16hVL1GVzI5ZfMlg6FLPMHAvfDDDxxoS7kPUf5egLPS9OLwgbV/t2bybK0lQihPdL1GUAh3JW3KuGSA2GJj0yHv65xcLkYJ3qMPwmL90Kp4P/EwSKeMwFQhw28fbezQNkFKY3NIQr9hpcALBxSFsj/12mySL4KTm+uCMGlBK1PUwNkGDi9X8OS2kWp/PNkV8fwrtUrnuwz3pwfbXswy2fxWJWzPqUmg4dK1ddRlVRErCMDslUhLbE9FUbtEBQUOoFZAOKJh4ZIQfZ+7AGbcGdUHAATWc0o84u+Gjjabj+gQIEkD/82Tya5AOf4a+ngSYVuM= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(346002)(39860400002)(136003)(376002)(451199015)(46966006)(36840700001)(40470700004)(336012)(2616005)(16526019)(1076003)(2906002)(40460700003)(54906003)(316002)(110136005)(81166007)(36756003)(478600001)(356005)(86362001)(40480700001)(7696005)(6666004)(82740400003)(83380400001)(26005)(82310400005)(47076005)(426003)(186003)(44832011)(5660300002)(36860700001)(8936002)(41300700001)(8676002)(70586007)(4326008)(70206006)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Dec 2022 07:50:34.8236 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3a73cf73-2b3c-4731-9b24-08dad439e525 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT065.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4911 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751087902815968869?= X-GMAIL-MSGID: =?utf-8?q?1751087902815968869?= From: Perry Yuan The patch add AMD pstate EPP feature introduction and what EPP preference supported for AMD processors. User can get supported list from energy_performance_available_preferences attribute file, or update current profile to energy_performance_preference file 1) See all EPP profiles $ sudo cat /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_available_preferences default performance balance_performance balance_power power 2) Check current EPP profile $ sudo cat /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_preference performance 3) Set new EPP profile $ sudo bash -c "echo power > /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_preference" Signed-off-by: Perry Yuan --- Documentation/admin-guide/pm/amd-pstate.rst | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index 06e23538f79c..33ab8ec8fc2f 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -262,6 +262,25 @@ lowest non-linear performance in `AMD CPPC Performance Capability `_.) This attribute is read-only. +``energy_performance_available_preferences`` + +A list of all the supported EPP preferences that could be used for +``energy_performance_preference`` on this system. +These profiles represent different hints that are provided +to the low-level firmware about the user's desired energy vs efficiency +tradeoff. ``default`` represents the epp value is set by platform +firmware. This attribute is read-only. + +``energy_performance_preference`` + +The current energy performance preference can be read from this attribute. +and user can change current preference according to energy or performance needs +Please get all support profiles list from +``energy_performance_available_preferences`` attribute, all the profiles are +integer values defined between 0 to 255 when EPP feature is enabled by platform +firmware, if EPP feature is disabled, driver will ignore the written value +This attribute is read-write. + Other performance and frequency values can be read back from ``/sys/devices/system/cpu/cpuX/acpi_cppc/``, see :ref:`cppc_sysfs`. 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Fri, 2 Dec 2022 01:50:31 -0600 From: Perry Yuan To: , , , CC: , , , , , , , , Subject: [PATCH v6 03/11] cpufreq: intel_pstate: use common macro definition for Energy Preference Performance(EPP) Date: Fri, 2 Dec 2022 15:47:11 +0800 Message-ID: <20221202074719.623673-4-perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202074719.623673-1-perry.yuan@amd.com> References: <20221202074719.623673-1-perry.yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT065:EE_|DM8PR12MB5445:EE_ X-MS-Office365-Filtering-Correlation-Id: ca69a75b-3585-41cc-d23e-08dad439e589 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: s2xGcXB04kYD+BkrAFFKCIWvgXhNf2rF3Fbp63+bSiuOjIAQ77F86+DlHrQPJXg/yegace0kIiHOdIpjZmQtEADMvJpfNGGl7OJsY0eqbUl6Zpm5MHaz0LHcHSRs3dFBAmJq+/yIE5rXSf2nEQM4M4quW8kq3LE4dKLXPg7aC2IvjGUcMoFWOkx2lq/zjDI57veAsiWdtf1ST9KzNDKoQf45955g66mcA0s+qiX2D/9+U/Lqc0cE2F2dCJWW3Bm8ZCHOSzBH4H/mxJgTrERhvDor1f7a2LAMApCLtvBNx29GABWHXBHQY5rqA1zirRwyq4WctQBhS3E0QX4xld+2oHVjbe7PJvXNYVah2612jL9zw7HDYy80jAr0DHPryv0dYKmuc4twYmJ0lwmTYSOEwPu7ogOCMm2Iqz4J2aNNoOamSA8I262NRV2e7bwBy1SQEBGxuunj2692UUc4/lDy9Ace1+qFyhnVe97+/xFpNx03tfQx+44l4E6o5hHqpmDMPVMDuxWz6ex+PNhRnnYhULZqg+hEqIt/tuPTrshT9buAmy08GnsLrNQsQXcPnp0lt/Zmi/rDUy1RaX/XzFcfRtNQ+EGjDNqVykz/H+4rstPmR/e/9htFXGMQdFbN0tMN+AMwvxPHOg4LmosM4pxOQrLqdD9gXS/aJaQcDlPRoB3MfuD8a9A7BX9KuUQggsPvSlHmnBKRgbD5bCt23zpZCURIRcqdeVyuhWA0ZpOxtsU= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(346002)(376002)(136003)(396003)(451199015)(36840700001)(46966006)(40470700004)(2906002)(44832011)(5660300002)(41300700001)(8936002)(8676002)(70586007)(316002)(110136005)(4326008)(54906003)(70206006)(36860700001)(36756003)(6666004)(1076003)(336012)(16526019)(82310400005)(478600001)(86362001)(47076005)(26005)(186003)(2616005)(426003)(82740400003)(40460700003)(83380400001)(7696005)(356005)(81166007)(40480700001)(36900700001);DIR:OUT;SFP:1101; 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This will simpify the intel_pstate and amd_pstate driver. Signed-off-by: Perry Yuan --- arch/x86/include/asm/msr-index.h | 4 --- drivers/cpufreq/intel_pstate.c | 37 +-------------------- include/linux/cpufreq_common.h | 56 ++++++++++++++++++++++++++++++++ 3 files changed, 57 insertions(+), 40 deletions(-) create mode 100644 include/linux/cpufreq_common.h diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 4a2af82553e4..3983378cff5b 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -472,10 +472,6 @@ #define HWP_MAX_PERF(x) ((x & 0xff) << 8) #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) #define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24) -#define HWP_EPP_PERFORMANCE 0x00 -#define HWP_EPP_BALANCE_PERFORMANCE 0x80 -#define HWP_EPP_BALANCE_POWERSAVE 0xC0 -#define HWP_EPP_POWERSAVE 0xFF #define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32) #define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42) diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c index ad9be31753b6..65036ca21719 100644 --- a/drivers/cpufreq/intel_pstate.c +++ b/drivers/cpufreq/intel_pstate.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -628,42 +629,6 @@ static int intel_pstate_set_epb(int cpu, s16 pref) return 0; } -/* - * EPP/EPB display strings corresponding to EPP index in the - * energy_perf_strings[] - * index String - *------------------------------------- - * 0 default - * 1 performance - * 2 balance_performance - * 3 balance_power - * 4 power - */ - -enum energy_perf_value_index { - EPP_INDEX_DEFAULT = 0, - EPP_INDEX_PERFORMANCE, - EPP_INDEX_BALANCE_PERFORMANCE, - EPP_INDEX_BALANCE_POWERSAVE, - EPP_INDEX_POWERSAVE, -}; - -static const char * const energy_perf_strings[] = { - [EPP_INDEX_DEFAULT] = "default", - [EPP_INDEX_PERFORMANCE] = "performance", - [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance", - [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power", - [EPP_INDEX_POWERSAVE] = "power", - NULL -}; -static unsigned int epp_values[] = { - [EPP_INDEX_DEFAULT] = 0, /* Unused index */ - [EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE, - [EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE, - [EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE, - [EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE, -}; - static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp) { s16 epp; diff --git a/include/linux/cpufreq_common.h b/include/linux/cpufreq_common.h new file mode 100644 index 000000000000..2d14b0b0f55c --- /dev/null +++ b/include/linux/cpufreq_common.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/include/linux/cpufreq_common.h + * + * Copyright (C) 2022 Advanced Micro Devices, Inc. + * + * Author: Perry Yuan + */ + +#ifndef _LINUX_CPUFREQ_COMMON_H +#define _LINUX_CPUFREQ_COMMON_H + +#include +/* + * EPP/EPB display strings corresponding to EPP index in the + * energy_perf_strings[] + * index String + *------------------------------------- + * 0 default + * 1 performance + * 2 balance_performance + * 3 balance_power + * 4 power + */ + +#define HWP_EPP_PERFORMANCE 0x00 +#define HWP_EPP_BALANCE_PERFORMANCE 0x80 +#define HWP_EPP_BALANCE_POWERSAVE 0xC0 +#define HWP_EPP_POWERSAVE 0xFF + +enum energy_perf_value_index { + EPP_INDEX_DEFAULT = 0, + EPP_INDEX_PERFORMANCE, + EPP_INDEX_BALANCE_PERFORMANCE, + EPP_INDEX_BALANCE_POWERSAVE, + EPP_INDEX_POWERSAVE, +}; + +static const char * const energy_perf_strings[] = { + [EPP_INDEX_DEFAULT] = "default", + [EPP_INDEX_PERFORMANCE] = "performance", + [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance", + [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power", + [EPP_INDEX_POWERSAVE] = "power", + NULL +}; + +static unsigned int epp_values[] = { + [EPP_INDEX_DEFAULT] = 0, /* Unused index */ + [EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE, + [EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE, + [EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE, + [EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE, +}; + +#endif /* _LINUX_CPUFREQ_COMMON_H */ \ No newline at end of file From patchwork Fri Dec 2 07:47:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 28740 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp702850wrr; Thu, 1 Dec 2022 23:53:01 -0800 (PST) X-Google-Smtp-Source: AA0mqf54kT0z1iezQ3w0y0bb2Fm+1BRUr+9AupdCEnN89Wlu2GqXYpoJiHK+tDfQsLmEdYryx8rn X-Received: by 2002:a63:1801:0:b0:45f:a78b:f905 with SMTP id y1-20020a631801000000b0045fa78bf905mr54939284pgl.296.1669967581469; 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Fri, 2 Dec 2022 01:50:35 -0600 From: Perry Yuan To: , , , CC: , , , , , , , , Subject: [PATCH v6 04/11] cpufreq: amd_pstate: implement Pstate EPP support for the AMD processors Date: Fri, 2 Dec 2022 15:47:12 +0800 Message-ID: <20221202074719.623673-5-perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202074719.623673-1-perry.yuan@amd.com> References: <20221202074719.623673-1-perry.yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT014:EE_|CH0PR12MB5298:EE_ X-MS-Office365-Filtering-Correlation-Id: bb0dbcba-2c12-408d-fb64-08dad439fe48 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4Vp3k4aHS2Lf3t/35MfwV8CMaAuivrcW7jBxBrf6NGgRZZMCK/0xwC3zJAudx9vtCLydQTyS5EUb2EBkFcNgK2tekbvvN79CI64Rg0kD/jdxikyB1T6omM4BW2p52KTAgeswL/WkBkwCpfrJMmjwSyRiDfF6hjTfsUyEdskIo6lr8XwzE91YagB/lO26cwCoFiQB+6ethWUwwK5t+Gzt5x+1p9clpKgQiIhj2vRGDs4IXkPWZklCpZvcCwu3MllflGG3KCQAMF0BV7fHXL+ZfwjEmf8AKg7LsabdL1dtvcu7p0oTUx3Jy5ff/xdTS/O3X0BpJg/ndwU9w1RWiOi7fgtTao8kXtUIYJVSnsGdVCSRIURUrMQ5oxSyfUth2rpGH6nWcmdvyqoPIwoOMpOP73SL6uE7Y27PtLc8eYf4+EeAmMu4NTz/GXJVnX16aPYoob1vwqaTUfmrCCmuRgxLSBrr3TD65RclJUyuBk1xU1/HfvRTu+w3RLP98905Ee21YKbGaK17s+JKUE2HQe5Had8OLGFN84QGpYUo9HFSFujMxMHEiuC0FqCNXS/TbF/yhlsEwwB7ZACtXyRiwBKg1HfK7OX9yDRBoG1CdSZqPQLz774SF0oZqbKT6zflJ+EZeVTWDAyKaXcKAcAGCh18jUc05Xn/Yc25jTtAI/dqZkbY8a9j7M38VUDKLJChwnHy/VSk3smwu070HY67XE0fJngtujfsasivMP5toBH7OyA= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(396003)(376002)(39860400002)(346002)(451199015)(36840700001)(40470700004)(46966006)(86362001)(82310400005)(478600001)(1076003)(336012)(26005)(2616005)(16526019)(186003)(7696005)(47076005)(426003)(30864003)(40480700001)(5660300002)(83380400001)(36860700001)(8936002)(36756003)(316002)(110136005)(54906003)(82740400003)(6666004)(2906002)(44832011)(40460700003)(70586007)(8676002)(356005)(81166007)(70206006)(4326008)(41300700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Dec 2022 07:51:17.0141 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bb0dbcba-2c12-408d-fb64-08dad439fe48 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT014.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5298 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751087926669045195?= X-GMAIL-MSGID: =?utf-8?q?1751087926669045195?= From: Perry Yuan Add EPP driver support for AMD SoCs which support a dedicated MSR for CPPC. EPP is used by the DPM controller to configure the frequency that a core operates at during short periods of activity. The SoC EPP targets are configured on a scale from 0 to 255 where 0 represents maximum performance and 255 represents maximum efficiency. The amd-pstate driver exports profile string names to userspace that are tied to specific EPP values. The balance_performance string (0x80) provides the best balance for efficiency versus power on most systems, but users can choose other strings to meet their needs as well. $ cat /sys/devices/system/cpu/cpufreq/policy0/energy_performance_available_preferences default performance balance_performance balance_power power $ cat /sys/devices/system/cpu/cpufreq/policy0/energy_performance_preference balance_performance To enable the driver,it needs to add `amd_pstate=active` to kernel command line and kernel will load the active mode epp driver Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 643 ++++++++++++++++++++++++++++++++++- include/linux/amd-pstate.h | 35 ++ 2 files changed, 672 insertions(+), 6 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 204e39006dda..5989d4d25d0f 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -37,9 +37,12 @@ #include #include #include +#include +#ifdef CONFIG_ACPI #include #include +#endif #include #include @@ -59,9 +62,130 @@ * we disable it by default to go acpi-cpufreq on these processors and add a * module parameter to be able to enable it manually for debugging. */ -static struct cpufreq_driver amd_pstate_driver; +static bool cppc_active; static int cppc_load __initdata; +static struct cpufreq_driver *default_pstate_driver; +static struct amd_cpudata **all_cpu_data; +static struct amd_pstate_params global_params; + +static DEFINE_MUTEX(amd_pstate_limits_lock); +static DEFINE_MUTEX(amd_pstate_driver_lock); + +static bool cppc_boost __read_mostly; +struct kobject *amd_pstate_kobj; + +#ifdef CONFIG_ACPI_CPPC_LIB +static s16 amd_pstate_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached) +{ + s16 epp; + struct cppc_perf_caps perf_caps; + int ret; + + if (boot_cpu_has(X86_FEATURE_CPPC)) { + if (!cppc_req_cached) { + epp = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, + &cppc_req_cached); + if (epp) + return epp; + } + epp = (cppc_req_cached >> 24) & 0xFF; + } else { + ret = cppc_get_epp_caps(cpudata->cpu, &perf_caps); + if (ret < 0) { + pr_debug("Could not retrieve energy perf value (%d)\n", ret); + return -EIO; + } + epp = (s16) perf_caps.energy_perf; + } + + return epp; +} +#endif + +static int amd_pstate_get_energy_pref_index(struct amd_cpudata *cpudata) +{ + s16 epp; + int index = -EINVAL; + + epp = amd_pstate_get_epp(cpudata, 0); + if (epp < 0) + return epp; + + switch (epp) { + case HWP_EPP_PERFORMANCE: + index = EPP_INDEX_PERFORMANCE; + break; + case HWP_EPP_BALANCE_PERFORMANCE: + index = EPP_INDEX_BALANCE_PERFORMANCE; + break; + case HWP_EPP_BALANCE_POWERSAVE: + index = EPP_INDEX_BALANCE_POWERSAVE; + break; + case HWP_EPP_POWERSAVE: + index = EPP_INDEX_POWERSAVE; + break; + default: + break; + } + + return index; +} + +#ifdef CONFIG_ACPI_CPPC_LIB +static int amd_pstate_set_epp(struct amd_cpudata *cpudata, u32 epp) +{ + int ret; + struct cppc_perf_ctrls perf_ctrls; + + if (boot_cpu_has(X86_FEATURE_CPPC)) { + u64 value = READ_ONCE(cpudata->cppc_req_cached); + + value &= ~GENMASK_ULL(31, 24); + value |= (u64)epp << 24; + WRITE_ONCE(cpudata->cppc_req_cached, value); + + ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); + if (!ret) + cpudata->epp_cached = epp; + } else { + perf_ctrls.energy_perf = epp; + ret = cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1); + if (ret) { + pr_debug("failed to set energy perf value (%d)\n", ret); + return ret; + } + cpudata->epp_cached = epp; + } + + return ret; +} + +static int amd_pstate_set_energy_pref_index(struct amd_cpudata *cpudata, + int pref_index) +{ + int epp = -EINVAL; + int ret; + + if (!pref_index) { + pr_debug("EPP pref_index is invalid\n"); + return -EINVAL; + } + + if (epp == -EINVAL) + epp = epp_values[pref_index]; + + if (epp > 0 && cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) { + pr_debug("EPP cannot be set under performance policy\n"); + return -EBUSY; + } + + ret = amd_pstate_set_epp(cpudata, epp); + + return ret; +} +#endif + static inline int pstate_enable(bool enable) { return wrmsrl_safe(MSR_AMD_CPPC_ENABLE, enable); @@ -70,11 +194,21 @@ static inline int pstate_enable(bool enable) static int cppc_enable(bool enable) { int cpu, ret = 0; + struct cppc_perf_ctrls perf_ctrls; for_each_present_cpu(cpu) { ret = cppc_set_enable(cpu, enable); if (ret) return ret; + + /* Enable autonomous mode for EPP */ + if (!cppc_active) { + /* Set desired perf as zero to allow EPP firmware control */ + perf_ctrls.desired_perf = 0; + ret = cppc_set_perf(cpu, &perf_ctrls); + if (ret) + return ret; + } } return ret; @@ -417,7 +551,7 @@ static void amd_pstate_boost_init(struct amd_cpudata *cpudata) return; cpudata->boost_supported = true; - amd_pstate_driver.boost_enabled = true; + default_pstate_driver->boost_enabled = true; } static void amd_perf_ctl_reset(unsigned int cpu) @@ -591,10 +725,61 @@ static ssize_t show_amd_pstate_highest_perf(struct cpufreq_policy *policy, return sprintf(&buf[0], "%u\n", perf); } +static ssize_t show_energy_performance_available_preferences( + struct cpufreq_policy *policy, char *buf) +{ + int i = 0; + int ret = 0; + + while (energy_perf_strings[i] != NULL) + ret += sysfs_emit(buf, "%s", energy_perf_strings[i++]); + + ret += sysfs_emit(buf, "\n"); + + return ret; +} + +static ssize_t store_energy_performance_preference( + struct cpufreq_policy *policy, const char *buf, size_t count) +{ + struct amd_cpudata *cpudata = policy->driver_data; + char str_preference[21]; + ssize_t ret; + + ret = sscanf(buf, "%20s", str_preference); + if (ret != 1) + return -EINVAL; + + ret = match_string(energy_perf_strings, -1, str_preference); + if (ret < 0) + return -EINVAL; + + mutex_lock(&amd_pstate_limits_lock); + ret = amd_pstate_set_energy_pref_index(cpudata, ret); + mutex_unlock(&amd_pstate_limits_lock); + + return ret ?: count; +} + +static ssize_t show_energy_performance_preference( + struct cpufreq_policy *policy, char *buf) +{ + struct amd_cpudata *cpudata = policy->driver_data; + int preference; + + preference = amd_pstate_get_energy_pref_index(cpudata); + if (preference < 0) + return preference; + + return sysfs_emit(buf, "%s\n", energy_perf_strings[preference]); +} + cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); cpufreq_freq_attr_ro(amd_pstate_highest_perf); +cpufreq_freq_attr_rw(energy_performance_preference); +cpufreq_freq_attr_ro(energy_performance_available_preferences); static struct freq_attr *amd_pstate_attr[] = { &amd_pstate_max_freq, @@ -603,6 +788,429 @@ static struct freq_attr *amd_pstate_attr[] = { NULL, }; +static struct freq_attr *amd_pstate_epp_attr[] = { + &amd_pstate_max_freq, + &amd_pstate_lowest_nonlinear_freq, + &amd_pstate_highest_perf, + &energy_performance_preference, + &energy_performance_available_preferences, + NULL, +}; + +static inline void update_boost_state(void) +{ + u64 misc_en; + struct amd_cpudata *cpudata; + + cpudata = all_cpu_data[0]; + rdmsrl(MSR_K7_HWCR, misc_en); + global_params.cppc_boost_disabled = misc_en & BIT_ULL(25); +} + +static bool amd_pstate_acpi_pm_profile_server(void) +{ + if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || + acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) + return true; + + return false; +} + +static int amd_pstate_init_cpu(unsigned int cpunum) +{ + struct amd_cpudata *cpudata; + + cpudata = all_cpu_data[cpunum]; + if (!cpudata) { + cpudata = kzalloc(sizeof(*cpudata), GFP_KERNEL); + if (!cpudata) + return -ENOMEM; + WRITE_ONCE(all_cpu_data[cpunum], cpudata); + + cpudata->cpu = cpunum; + + if (cppc_active) { + if (amd_pstate_acpi_pm_profile_server()) + cppc_boost = true; + } + + } + cpudata->epp_powersave = -EINVAL; + cpudata->epp_policy = 0; + pr_debug("controlling: cpu %d\n", cpunum); + return 0; +} + +static int __amd_pstate_cpu_init(struct cpufreq_policy *policy) +{ + int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; + struct amd_cpudata *cpudata; + struct device *dev; + int rc; + u64 value; + + rc = amd_pstate_init_cpu(policy->cpu); + if (rc) + return rc; + + cpudata = all_cpu_data[policy->cpu]; + + dev = get_cpu_device(policy->cpu); + if (!dev) + goto free_cpudata1; + + rc = amd_pstate_init_perf(cpudata); + if (rc) + goto free_cpudata1; + + min_freq = amd_get_min_freq(cpudata); + max_freq = amd_get_max_freq(cpudata); + nominal_freq = amd_get_nominal_freq(cpudata); + lowest_nonlinear_freq = amd_get_lowest_nonlinear_freq(cpudata); + if (min_freq < 0 || max_freq < 0 || min_freq > max_freq) { + dev_err(dev, "min_freq(%d) or max_freq(%d) value is incorrect\n", + min_freq, max_freq); + ret = -EINVAL; + goto free_cpudata1; + } + + policy->min = min_freq; + policy->max = max_freq; + + policy->cpuinfo.min_freq = min_freq; + policy->cpuinfo.max_freq = max_freq; + /* It will be updated by governor */ + policy->cur = policy->cpuinfo.min_freq; + + /* Initial processor data capability frequencies */ + cpudata->max_freq = max_freq; + cpudata->min_freq = min_freq; + cpudata->nominal_freq = nominal_freq; + cpudata->lowest_nonlinear_freq = lowest_nonlinear_freq; + + policy->driver_data = cpudata; + + update_boost_state(); + cpudata->epp_cached = amd_pstate_get_epp(cpudata, value); + + policy->min = policy->cpuinfo.min_freq; + policy->max = policy->cpuinfo.max_freq; + + if (boot_cpu_has(X86_FEATURE_CPPC)) + policy->fast_switch_possible = true; + + if (boot_cpu_has(X86_FEATURE_CPPC)) { + ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value); + if (ret) + return ret; + WRITE_ONCE(cpudata->cppc_req_cached, value); + + ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, &value); + if (ret) + return ret; + WRITE_ONCE(cpudata->cppc_cap1_cached, value); + } + amd_pstate_boost_init(cpudata); + + return 0; + +free_cpudata1: + kfree(cpudata); + return ret; +} + +static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) +{ + int ret; + + ret = __amd_pstate_cpu_init(policy); + if (ret) + return ret; + /* + * Set the policy to powersave to provide a valid fallback value in case + * the default cpufreq governor is neither powersave nor performance. + */ + policy->policy = CPUFREQ_POLICY_POWERSAVE; + + return 0; +} + +static int amd_pstate_epp_cpu_exit(struct cpufreq_policy *policy) +{ + pr_debug("CPU %d exiting\n", policy->cpu); + policy->fast_switch_possible = false; + return 0; +} + +static void amd_pstate_update_max_freq(unsigned int cpu) +{ + struct cpufreq_policy *policy = policy = cpufreq_cpu_get(cpu); + + if (!policy) + return; + + refresh_frequency_limits(policy); + cpufreq_cpu_put(policy); +} + +static void amd_pstate_epp_update_limits(unsigned int cpu) +{ + mutex_lock(&amd_pstate_driver_lock); + update_boost_state(); + if (global_params.cppc_boost_disabled) { + for_each_possible_cpu(cpu) + amd_pstate_update_max_freq(cpu); + } else { + cpufreq_update_policy(cpu); + } + mutex_unlock(&amd_pstate_driver_lock); +} + +static int cppc_boost_hold_time_ns = 3 * NSEC_PER_MSEC; + +static inline void amd_pstate_boost_up(struct amd_cpudata *cpudata) +{ + u64 hwp_req = READ_ONCE(cpudata->cppc_req_cached); + u64 hwp_cap = READ_ONCE(cpudata->cppc_cap1_cached); + u32 max_limit = (hwp_req & 0xff); + u32 min_limit = (hwp_req & 0xff00) >> 8; + u32 boost_level1; + + /* If max and min are equal or already at max, nothing to boost */ + if (max_limit == min_limit) + return; + + /* Set boost max and min to initial value */ + if (!cpudata->cppc_boost_min) + cpudata->cppc_boost_min = min_limit; + + boost_level1 = ((AMD_CPPC_NOMINAL_PERF(hwp_cap) + min_limit) >> 1); + + if (cpudata->cppc_boost_min < boost_level1) + cpudata->cppc_boost_min = boost_level1; + else if (cpudata->cppc_boost_min < AMD_CPPC_NOMINAL_PERF(hwp_cap)) + cpudata->cppc_boost_min = AMD_CPPC_NOMINAL_PERF(hwp_cap); + else if (cpudata->cppc_boost_min == AMD_CPPC_NOMINAL_PERF(hwp_cap)) + cpudata->cppc_boost_min = max_limit; + else + return; + + hwp_req &= ~AMD_CPPC_MIN_PERF(~0L); + hwp_req |= AMD_CPPC_MIN_PERF(cpudata->cppc_boost_min); + wrmsrl(MSR_AMD_CPPC_REQ, hwp_req); + cpudata->last_update = cpudata->sample.time; +} + +static inline void amd_pstate_boost_down(struct amd_cpudata *cpudata) +{ + bool expired; + + if (cpudata->cppc_boost_min) { + expired = time_after64(cpudata->sample.time, cpudata->last_update + + cppc_boost_hold_time_ns); + + if (expired) { + wrmsrl(MSR_AMD_CPPC_REQ, cpudata->cppc_req_cached); + cpudata->cppc_boost_min = 0; + } + } + + cpudata->last_update = cpudata->sample.time; +} + +static inline void amd_pstate_boost_update_util(struct amd_cpudata *cpudata, + u64 time) +{ + cpudata->sample.time = time; + if (smp_processor_id() != cpudata->cpu) + return; + + if (cpudata->sched_flags & SCHED_CPUFREQ_IOWAIT) { + bool do_io = false; + + cpudata->sched_flags = 0; + /* + * Set iowait_boost flag and update time. Since IO WAIT flag + * is set all the time, we can't just conclude that there is + * some IO bound activity is scheduled on this CPU with just + * one occurrence. If we receive at least two in two + * consecutive ticks, then we treat as boost candidate. + * This is leveraged from Intel Pstate driver. + */ + if (time_before64(time, cpudata->last_io_update + 2 * TICK_NSEC)) + do_io = true; + + cpudata->last_io_update = time; + + if (do_io) + amd_pstate_boost_up(cpudata); + + } else { + amd_pstate_boost_down(cpudata); + } +} + +static inline void amd_pstate_cppc_update_hook(struct update_util_data *data, + u64 time, unsigned int flags) +{ + struct amd_cpudata *cpudata = container_of(data, + struct amd_cpudata, update_util); + + cpudata->sched_flags |= flags; + + if (smp_processor_id() == cpudata->cpu) + amd_pstate_boost_update_util(cpudata, time); +} + +static void amd_pstate_clear_update_util_hook(unsigned int cpu) +{ + struct amd_cpudata *cpudata = all_cpu_data[cpu]; + + if (!cpudata->update_util_set) + return; + + cpufreq_remove_update_util_hook(cpu); + cpudata->update_util_set = false; + synchronize_rcu(); +} + +static void amd_pstate_set_update_util_hook(unsigned int cpu_num) +{ + struct amd_cpudata *cpudata = all_cpu_data[cpu_num]; + + if (!cppc_boost) { + if (cpudata->update_util_set) + amd_pstate_clear_update_util_hook(cpudata->cpu); + return; + } + + if (cpudata->update_util_set) + return; + + cpudata->sample.time = 0; + cpufreq_add_update_util_hook(cpu_num, &cpudata->update_util, + amd_pstate_cppc_update_hook); + cpudata->update_util_set = true; +} + +static void amd_pstate_epp_init(unsigned int cpu) +{ + struct amd_cpudata *cpudata = all_cpu_data[cpu]; + u32 max_perf, min_perf; + u64 value; + s16 epp; + int ret; + + max_perf = READ_ONCE(cpudata->highest_perf); + min_perf = READ_ONCE(cpudata->lowest_perf); + + value = READ_ONCE(cpudata->cppc_req_cached); + + if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) + min_perf = max_perf; + + /* Initial min/max values for CPPC Performance Controls Register */ + value &= ~AMD_CPPC_MIN_PERF(~0L); + value |= AMD_CPPC_MIN_PERF(min_perf); + + value &= ~AMD_CPPC_MAX_PERF(~0L); + value |= AMD_CPPC_MAX_PERF(max_perf); + + /* CPPC EPP feature require to set zero to the desire perf bit */ + value &= ~AMD_CPPC_DES_PERF(~0L); + value |= AMD_CPPC_DES_PERF(0); + + if (cpudata->epp_policy == cpudata->policy) + goto skip_epp; + + cpudata->epp_policy = cpudata->policy; + + if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) { + epp = amd_pstate_get_epp(cpudata, value); + cpudata->epp_powersave = epp; + if (epp < 0) + goto skip_epp; + /* force the epp value to be zero for performance policy */ + epp = 0; + } else { + if (cpudata->epp_powersave < 0) + goto skip_epp; + /* Get BIOS pre-defined epp value */ + epp = amd_pstate_get_epp(cpudata, value); + if (epp) + goto skip_epp; + epp = cpudata->epp_powersave; + } + /* Set initial EPP value */ + if (boot_cpu_has(X86_FEATURE_CPPC)) { + value &= ~GENMASK_ULL(31, 24); + value |= (u64)epp << 24; + } + +skip_epp: + WRITE_ONCE(cpudata->cppc_req_cached, value); + ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); + if (!ret) + cpudata->epp_cached = epp; +} + +static void amd_pstate_set_max_limits(struct amd_cpudata *cpudata) +{ + u64 hwp_cap = READ_ONCE(cpudata->cppc_cap1_cached); + u64 hwp_req = READ_ONCE(cpudata->cppc_req_cached); + u32 max_limit = (hwp_cap >> 24) & 0xff; + + hwp_req &= ~AMD_CPPC_MIN_PERF(~0L); + hwp_req |= AMD_CPPC_MIN_PERF(max_limit); + wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, hwp_req); +} + +static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy) +{ + struct amd_cpudata *cpudata; + + if (!policy->cpuinfo.max_freq) + return -ENODEV; + + pr_debug("set_policy: cpuinfo.max %u policy->max %u\n", + policy->cpuinfo.max_freq, policy->max); + + cpudata = all_cpu_data[policy->cpu]; + cpudata->policy = policy->policy; + + if (boot_cpu_has(X86_FEATURE_CPPC)) { + mutex_lock(&amd_pstate_limits_lock); + + if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) { + amd_pstate_clear_update_util_hook(policy->cpu); + amd_pstate_set_max_limits(cpudata); + } else { + amd_pstate_set_update_util_hook(policy->cpu); + } + + if (boot_cpu_has(X86_FEATURE_CPPC)) + amd_pstate_epp_init(policy->cpu); + + mutex_unlock(&amd_pstate_limits_lock); + } + + return 0; +} + +static void amd_pstate_verify_cpu_policy(struct amd_cpudata *cpudata, + struct cpufreq_policy_data *policy) +{ + update_boost_state(); + cpufreq_verify_within_cpu_limits(policy); +} + +static int amd_pstate_epp_verify_policy(struct cpufreq_policy_data *policy) +{ + amd_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy); + pr_debug("policy_max =%d, policy_min=%d\n", policy->max, policy->min); + return 0; +} + static struct cpufreq_driver amd_pstate_driver = { .flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS, .verify = amd_pstate_verify, @@ -616,8 +1224,20 @@ static struct cpufreq_driver amd_pstate_driver = { .attr = amd_pstate_attr, }; +static struct cpufreq_driver amd_pstate_epp_driver = { + .flags = CPUFREQ_CONST_LOOPS, + .verify = amd_pstate_epp_verify_policy, + .setpolicy = amd_pstate_epp_set_policy, + .init = amd_pstate_epp_cpu_init, + .exit = amd_pstate_epp_cpu_exit, + .update_limits = amd_pstate_epp_update_limits, + .name = "amd_pstate_epp", + .attr = amd_pstate_epp_attr, +}; + static int __init amd_pstate_init(void) { + static struct amd_cpudata **cpudata; int ret; if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) @@ -644,7 +1264,8 @@ static int __init amd_pstate_init(void) /* capability check */ if (boot_cpu_has(X86_FEATURE_CPPC)) { pr_debug("AMD CPPC MSR based functionality is supported\n"); - amd_pstate_driver.adjust_perf = amd_pstate_adjust_perf; + if (!cppc_active) + default_pstate_driver->adjust_perf = amd_pstate_adjust_perf; } else { pr_debug("AMD CPPC shared memory based functionality is supported\n"); static_call_update(amd_pstate_enable, cppc_enable); @@ -652,6 +1273,10 @@ static int __init amd_pstate_init(void) static_call_update(amd_pstate_update_perf, cppc_update_perf); } + cpudata = vzalloc(array_size(sizeof(void *), num_possible_cpus())); + if (!cpudata) + return -ENOMEM; + WRITE_ONCE(all_cpu_data, cpudata); /* enable amd pstate feature */ ret = amd_pstate_enable(true); if (ret) { @@ -659,9 +1284,9 @@ static int __init amd_pstate_init(void) return ret; } - ret = cpufreq_register_driver(&amd_pstate_driver); + ret = cpufreq_register_driver(default_pstate_driver); if (ret) - pr_err("failed to register amd_pstate_driver with return %d\n", + pr_err("failed to register amd pstate driver with return %d\n", ret); return ret; @@ -676,8 +1301,14 @@ static int __init amd_pstate_param(char *str) if (!strcmp(str, "disable")) { cppc_load = 0; pr_info("driver is explicitly disabled\n"); - } else if (!strcmp(str, "passive")) + } else if (!strcmp(str, "passive")) { cppc_load = 1; + default_pstate_driver = &amd_pstate_driver; + } else if (!strcmp(str, "active")) { + cppc_active = 1; + cppc_load = 1; + default_pstate_driver = &amd_pstate_epp_driver; + } return 0; } diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index 1c4b8659f171..888af62040f1 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -25,6 +25,7 @@ struct amd_aperf_mperf { u64 aperf; u64 mperf; u64 tsc; + u64 time; }; /** @@ -47,6 +48,18 @@ struct amd_aperf_mperf { * @prev: Last Aperf/Mperf/tsc count value read from register * @freq: current cpu frequency value * @boost_supported: check whether the Processor or SBIOS supports boost mode + * @epp_powersave: Last saved CPPC energy performance preference + when policy switched to performance + * @epp_policy: Last saved policy used to set energy-performance preference + * @epp_cached: Cached CPPC energy-performance preference value + * @policy: Cpufreq policy value + * @sched_flags: Store scheduler flags for possible cross CPU update + * @update_util_set: CPUFreq utility callback is set + * @last_update: Time stamp of the last performance state update + * @cppc_boost_min: Last CPPC boosted min performance state + * @cppc_cap1_cached: Cached value of the last CPPC Capabilities MSR + * @update_util: Cpufreq utility callback information + * @sample: the stored performance sample * * The amd_cpudata is key private data for each CPU thread in AMD P-State, and * represents all the attributes and goals that AMD P-State requests at runtime. @@ -72,6 +85,28 @@ struct amd_cpudata { u64 freq; bool boost_supported; + + /* EPP feature related attributes*/ + s16 epp_powersave; + s16 epp_policy; + s16 epp_cached; + u32 policy; + u32 sched_flags; + bool update_util_set; + u64 last_update; + u64 last_io_update; + u32 cppc_boost_min; + u64 cppc_cap1_cached; + struct update_util_data update_util; + struct amd_aperf_mperf sample; +}; + +/** + * struct amd_pstate_params - global parameters for the performance control + * @ cppc_boost_disabled wheher the core performance boost disabled + */ +struct amd_pstate_params { + bool cppc_boost_disabled; }; #endif /* _LINUX_AMD_PSTATE_H */ From patchwork Fri Dec 2 07:47:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 28741 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp702983wrr; Thu, 1 Dec 2022 23:53:34 -0800 (PST) X-Google-Smtp-Source: AA0mqf6WrpyYY5AoYuT3EoB8ERu/8VjWOgCriQfV6NNrfaeROggJsVn+bCghIaO2k/2RyaKXBjpS X-Received: by 2002:a17:907:2c75:b0:7c0:bbab:a550 with SMTP id ib21-20020a1709072c7500b007c0bbaba550mr1383263ejc.168.1669967614414; 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Fri, 2 Dec 2022 01:51:16 -0600 From: Perry Yuan To: , , , CC: , , , , , , , , Subject: [PATCH v6 05/11] cpufreq: amd_pstate: implement amd pstate cpu online and offline callback Date: Fri, 2 Dec 2022 15:47:13 +0800 Message-ID: <20221202074719.623673-6-perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202074719.623673-1-perry.yuan@amd.com> References: <20221202074719.623673-1-perry.yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT055:EE_|PH7PR12MB6466:EE_ X-MS-Office365-Filtering-Correlation-Id: 4bef6498-c38b-4543-d790-08dad439fff8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: NjmGmuRApnVi5H65t7GWLBliij1Zthz0bvIwCsOJNejxplajJVvk8M7NPzRpYT9K6fOH0WrAOTqTHJaLKndG28tK4xyHyyWKtFXX6uuvuz3EVpAlBIIgKeil36dofvWdqxNunqroawWi//c9ycHqGiclAQ809gM8/eOlAXUt6AmV+/MwBpP/dbBhZozubwhOJohzZacVerUncAz28Z/QHOXdvQpIm+3i/GLK9DbRDNO5aqU/mJW/THIfKT5LMz33cB//yEztiHCM+C0EOOq9w1sw5A0O1q5VK63vBabZ2xzigxxnw/iT1NlFpsanDDNpIZ7UkV1uwx9oWS8srWGT3zrqxNimDHN5sBX/iLDn73lCcJqRFppZUjl4O3XVHsP7DPIXtcn62O+QT6XrqgZQfS+U3PeGd8ZRp6PNhiRoXGrLYdaRFC58xkHNAcgoaZj4qpnupQbksmGeVm0c1GpTyVb+o12R0rY7C5FxC2L3D/pccdyXAEwKIEd12FqJc4NDZacKvrqcj2/GzZtpXKttEn6fls9LEKm173YRMxpfsnuVN8fE0sm2bcj6htU1iqo9Ntxm0wdEl7YKPnq9DUQayF/KvdHLlORqNsCjFCOkXH3UrUm5Ovon0SDamDoFRDSwMjmiBvgPHqhIrVnvAwL3ujs2SRj7738fSgK+T5WUmCYW/8q5+t+s6HpfgxJRTaK/SG7DtBecDSsBHJSviX24nwEl/tVJzle7LuIqzQrxnx0= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(376002)(39860400002)(136003)(396003)(451199015)(36840700001)(46966006)(40470700004)(36756003)(70206006)(44832011)(70586007)(41300700001)(5660300002)(4326008)(8936002)(26005)(2906002)(40460700003)(82310400005)(8676002)(83380400001)(478600001)(336012)(7696005)(2616005)(47076005)(54906003)(186003)(16526019)(86362001)(1076003)(316002)(110136005)(426003)(40480700001)(356005)(81166007)(82740400003)(36860700001)(6666004)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Dec 2022 07:51:19.8287 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4bef6498-c38b-4543-d790-08dad439fff8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT055.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6466 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751087960933037828?= X-GMAIL-MSGID: =?utf-8?q?1751087960933037828?= From: Perry Yuan Adds online and offline driver callback support to allow cpu cores go offline and help to restore the previous working states when core goes back online later for EPP driver mode. Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 89 ++++++++++++++++++++++++++++++++++++ include/linux/amd-pstate.h | 1 + 2 files changed, 90 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 5989d4d25d0f..7545d83a934b 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1197,6 +1197,93 @@ static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy) return 0; } +static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata) +{ + struct cppc_perf_ctrls perf_ctrls; + u64 value, max_perf; + int ret; + + ret = amd_pstate_enable(true); + if (ret) + pr_err("failed to enable amd pstate during resume, return %d\n", ret); + + value = READ_ONCE(cpudata->cppc_req_cached); + max_perf = READ_ONCE(cpudata->highest_perf); + + if (boot_cpu_has(X86_FEATURE_CPPC)) { + wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); + } else { + perf_ctrls.max_perf = max_perf; + perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(cpudata->epp_cached); + cppc_set_perf(cpudata->cpu, &perf_ctrls); + } +} + +static int amd_pstate_epp_cpu_online(struct cpufreq_policy *policy) +{ + struct amd_cpudata *cpudata = all_cpu_data[policy->cpu]; + + pr_debug("AMD CPU Core %d going online\n", cpudata->cpu); + + if (cppc_active) { + amd_pstate_epp_reenable(cpudata); + cpudata->suspended = false; + } + + return 0; +} + +static void amd_pstate_epp_offline(struct cpufreq_policy *policy) +{ + struct amd_cpudata *cpudata = all_cpu_data[policy->cpu]; + struct cppc_perf_ctrls perf_ctrls; + int min_perf; + u64 value; + + min_perf = READ_ONCE(cpudata->lowest_perf); + value = READ_ONCE(cpudata->cppc_req_cached); + + mutex_lock(&amd_pstate_limits_lock); + if (boot_cpu_has(X86_FEATURE_CPPC)) { + cpudata->epp_policy = CPUFREQ_POLICY_UNKNOWN; + + /* Set max perf same as min perf */ + value &= ~AMD_CPPC_MAX_PERF(~0L); + value |= AMD_CPPC_MAX_PERF(min_perf); + value &= ~AMD_CPPC_MIN_PERF(~0L); + value |= AMD_CPPC_MIN_PERF(min_perf); + wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); + } else { + perf_ctrls.desired_perf = 0; + perf_ctrls.max_perf = min_perf; + perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(HWP_EPP_POWERSAVE); + cppc_set_perf(cpudata->cpu, &perf_ctrls); + } + mutex_unlock(&amd_pstate_limits_lock); +} + +static int amd_pstate_cpu_offline(struct cpufreq_policy *policy) +{ + struct amd_cpudata *cpudata = all_cpu_data[policy->cpu]; + + pr_debug("AMD CPU Core %d going offline\n", cpudata->cpu); + + if (cpudata->suspended) + return 0; + + if (cppc_active) + amd_pstate_epp_offline(policy); + + return 0; +} + +static int amd_pstate_epp_cpu_offline(struct cpufreq_policy *policy) +{ + amd_pstate_clear_update_util_hook(policy->cpu); + + return amd_pstate_cpu_offline(policy); +} + static void amd_pstate_verify_cpu_policy(struct amd_cpudata *cpudata, struct cpufreq_policy_data *policy) { @@ -1231,6 +1318,8 @@ static struct cpufreq_driver amd_pstate_epp_driver = { .init = amd_pstate_epp_cpu_init, .exit = amd_pstate_epp_cpu_exit, .update_limits = amd_pstate_epp_update_limits, + .offline = amd_pstate_epp_cpu_offline, + .online = amd_pstate_epp_cpu_online, .name = "amd_pstate_epp", .attr = amd_pstate_epp_attr, }; diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index 888af62040f1..3dd26a3d104c 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -99,6 +99,7 @@ struct amd_cpudata { u64 cppc_cap1_cached; struct update_util_data update_util; struct amd_aperf_mperf sample; + bool suspended; }; /** From patchwork Fri Dec 2 07:47:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 28742 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp702988wrr; Thu, 1 Dec 2022 23:53:35 -0800 (PST) X-Google-Smtp-Source: AA0mqf7IxzuubObnkqRZD3ntz0qLfvVnTsk9vS1sPg5I0rJhr/xter38JKWvdZ2ZZfoP2P4zQRB6 X-Received: by 2002:a17:906:7f8d:b0:7ba:298d:6172 with SMTP id f13-20020a1709067f8d00b007ba298d6172mr36410560ejr.555.1669967615067; Thu, 01 Dec 2022 23:53:35 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1669967615; cv=pass; d=google.com; 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Fri, 2 Dec 2022 01:51:19 -0600 From: Perry Yuan To: , , , CC: , , , , , , , , Subject: [PATCH v6 06/11] cpufreq: amd-pstate: implement suspend and resume callbacks Date: Fri, 2 Dec 2022 15:47:14 +0800 Message-ID: <20221202074719.623673-7-perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202074719.623673-1-perry.yuan@amd.com> References: <20221202074719.623673-1-perry.yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT055:EE_|IA1PR12MB6019:EE_ X-MS-Office365-Filtering-Correlation-Id: 3aaf6891-566b-43e7-ae73-08dad43a0264 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HGuoSI0uyFC11JEQDnbwuh9LCI97iWRW4xjqdkbfscg9l38KSqeVevUZepQJOtozv6ZwroydGltWfNdtsHLd64va7IZNXRX1AeMiBQTWjULsT3MvwNBdR0rw1KicQZ+9gSXhyhW4CHFHPnMcBJz0oLD5wAGIKqj/RlDOCbNIQASgIdxcma4Je650UlY9QqRtZjmkx+oQsFe/hmHfVny9SXovPvR49YRq755muoK7VnIVruI4DyKUawtBT52NBf/hboepJw6AOu4SkK10zDG8PL12ZtqznIE9cyyRvcHJo2clHEkDpOPbCMjsuUFv2DryJpCxVFEVlnV2g8ZdODFyt/dSsqKNdsGQro5JWxq0hJG4jnwDuMGgbJGhfYkUR1dtsdrGensCpcqianvNDm6RAN//lAgoLRk+fFJh/xWFAKba7ent5ELKUeakCwBtdGKoSl2lZVkIMsmrElmtORMe6OlwtWOoCjuE91OPrTNjVbIriStRvnAUNNrbgG00yEkJey73HBcVhh8htzz6EXLvjj79feBKEN+tRhRKbUfn4iNEsbU1lp9ZqqQyUr8VHUCqCAHQBrfRWO93z/6PAqZ8H+Idi5T2j6ghJPxH6XYt5Qwf84asquKX5b9Z8ydX6Q7tM9xdeBoaSnrnkjBTlKgKhBrDY4TmpZscMtved+TdqnDcUv7c+GydypSkBHfdjn+UkMFph3KytKzNEtrkcGpxpT3XIBgpwU/y6+E7VjwyZ1w= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(39860400002)(376002)(346002)(136003)(451199015)(40470700004)(46966006)(36840700001)(2616005)(36860700001)(2906002)(83380400001)(7696005)(40460700003)(15650500001)(70586007)(26005)(8676002)(70206006)(356005)(81166007)(40480700001)(82310400005)(82740400003)(6666004)(478600001)(36756003)(41300700001)(426003)(1076003)(186003)(8936002)(47076005)(5660300002)(16526019)(316002)(54906003)(336012)(44832011)(110136005)(86362001)(4326008)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Dec 2022 07:51:23.8909 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3aaf6891-566b-43e7-ae73-08dad43a0264 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT055.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6019 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751087962244061266?= X-GMAIL-MSGID: =?utf-8?q?1751087962244061266?= From: Perry Yuan add suspend and resume support for the AMD processors by amd_pstate_epp driver instance. When the CPPC is suspended, EPP driver will set EPP profile to 'power' profile and set max/min perf to lowest perf value. When resume happens, it will restore the MSR registers with previous cached value. Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 40 ++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 7545d83a934b..b3a82cee2e83 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1284,6 +1284,44 @@ static int amd_pstate_epp_cpu_offline(struct cpufreq_policy *policy) return amd_pstate_cpu_offline(policy); } +static int amd_pstate_epp_suspend(struct cpufreq_policy *policy) +{ + struct amd_cpudata *cpudata = all_cpu_data[policy->cpu]; + int ret; + + /* avoid suspending when EPP is not enabled */ + if (!cppc_active) + return 0; + + /* set this flag to avoid setting core offline*/ + cpudata->suspended = true; + + /* disable CPPC in lowlevel firmware */ + ret = amd_pstate_enable(false); + if (ret) + pr_err("failed to suspend, return %d\n", ret); + + return 0; +} + +static int amd_pstate_epp_resume(struct cpufreq_policy *policy) +{ + struct amd_cpudata *cpudata = all_cpu_data[policy->cpu]; + + if (cpudata->suspended) { + mutex_lock(&amd_pstate_limits_lock); + + /* enable amd pstate from suspend state*/ + amd_pstate_epp_reenable(cpudata); + + mutex_unlock(&amd_pstate_limits_lock); + + cpudata->suspended = false; + } + + return 0; +} + static void amd_pstate_verify_cpu_policy(struct amd_cpudata *cpudata, struct cpufreq_policy_data *policy) { @@ -1320,6 +1358,8 @@ static struct cpufreq_driver amd_pstate_epp_driver = { .update_limits = amd_pstate_epp_update_limits, .offline = amd_pstate_epp_cpu_offline, .online = amd_pstate_epp_cpu_online, + .suspend = amd_pstate_epp_suspend, + .resume = amd_pstate_epp_resume, .name = "amd_pstate_epp", .attr = amd_pstate_epp_attr, }; From patchwork Fri Dec 2 07:47:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 28743 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp703025wrr; Thu, 1 Dec 2022 23:53:42 -0800 (PST) X-Google-Smtp-Source: AA0mqf4yNFdeMHvyq6sFwT3Tus7FQcp2PPxi0RDHq2bIjc5lnjvEXoVtk2Q8bqShpkgbrT/vnJzO X-Received: by 2002:a17:902:f78a:b0:186:5bbc:2ad9 with SMTP id q10-20020a170902f78a00b001865bbc2ad9mr63496900pln.157.1669967622101; Thu, 01 Dec 2022 23:53:42 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1669967622; cv=pass; d=google.com; s=arc-20160816; b=zLmrP4+OaYAE9Q3il2TnYBaT0n/lvk4alYqX4n0FdaU3s6GNitnGRRfTN5eHbhcpI2 TVqwFj/w+Zj4y9aAm/OziiVRHLOQXvjKvmCLkmGcdxyKzttS6CAnJMlCSCbsi8UU9J5V bqI9pd5ZGhd8OXnQ7rT01DqSZaXnG4pYHeAGp/mXpj5R0WG3N0msUysbBTFKPEa/VgfM 9ZLOjoo2C7dOM/qNPOmyVdjtdSy2piZef6L/vWh9/je9ZXYH7CLeGbCS/ekjqweLAqGc wm7tQYBEyAhI9cg+6L7KEwOf2hVxFKvuVS3n4TNB1kEAlbHfb+crqsyS+mapifeGIxt4 y8Bg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=0twL0htuKEWjgmgwAUFoURCxZ8iLhYjjEP18lP/gGUo=; b=I7/fzlzPN2S19oDqDr2chvUHkqyvfJk9PfF3hy8b2od2E4CSIaUMJGVdr2e4eaRdDb rJGJjX+2cmWqkT/QmB5ZYwiGvv25tfyQPU2QggyNWXFt0RCaOFI9aBAdctQi8TyDhN90 5rd/UYjvJVTwb3oB3NCRV+YzAZyC9mJks/2vyDkwSnaMDTows/iMnQrzgiEg41GrLawg Bz95XFnRfKX3CfXqirHquUFvTx4Dy2L8HXiRIXEeJtlEGjQLF1p8db2kcpRObIdGsQvm XXfBnBh2hqbAEjkEjWS6TmCuuDYuR95M7bZ3dugvTwo7KIcyLdI6/gtW98OpyBPgH8Z6 pjcw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=mKovbGwC; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Fri, 2 Dec 2022 01:51:23 -0600 From: Perry Yuan To: , , , CC: , , , , , , , , Subject: [PATCH v6 07/11] cpufreq: amd-pstate: add frequency dynamic boost sysfs control Date: Fri, 2 Dec 2022 15:47:15 +0800 Message-ID: <20221202074719.623673-8-perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202074719.623673-1-perry.yuan@amd.com> References: <20221202074719.623673-1-perry.yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT059:EE_|DS0PR12MB7512:EE_ X-MS-Office365-Filtering-Correlation-Id: 9d45da11-2c5a-4677-c1d2-08dad43a0460 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: w1yfk/sUHLnm1k//f9im3Oz53IFbP4CxYkoKMFYMxoWKR6uNr4rcCbP77ZPnNsgtS3xSkJXnWgG7LRzs6ea2b4I08fBKyHnmuTbvoNv/j5tyuNiUSID+TzKZpGiKQwUGpDSE9BU1TBvGP3gFbfHzUVfvTjIQEcZS5RAkt4fJwTMY18TCni0WVD/c4cf2rv5yc59in9QV+87TJeKGacwSf+MErl9BmQwkB4A6tZyirjlm8m872emUm+CU21oehEGjNOOhNOums1yrsMzzdVofAwxHROHku5YCKDFTwSruQwx9/PcYy07b4JBGoCkG4368GOnZP0eBOEm/y1jVPtrlSRE/9K9+hUMZYD78xON2glq8wZT7YYcI86xmqBtTcRSVok79Ms4qEh+grgRS8uT8Tp/gALD3sqfqA9MuWKVHfHTS0dOsuOaHcyHDxOc0ANNYj4Yc9VX1EmI/ayuhe7pZaIc0Is6jl1/4zhztcziGlH3Czyiy1y6sL0gLlQBtocInWnCIwu9ySO0KyBtb8Djn+PuKqamGktQRstx26bgpo1UpQLBsdCVyg94rAwX3Hw8k4TRx0sXJi75bIjoC3NPAtZqrY1kK8xB+WMaDRWrWOa5GOb8fBMHOuReUbomubKlqJzmF7WUjRoS9gk5qlEgOG/eH60CAD60zTOaKf4lvfSTYoc2QzyluTafde0oxuUxuylzQJM5NgtLDOEA2ZYpVWNIVWAuxN4ZPUHefjFznoDVR09kvkqEyIdC0BohwtsIDJlIpj3u7Y3LPyJHtLW8K1A== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(136003)(346002)(39860400002)(396003)(451199015)(36840700001)(40470700004)(46966006)(41300700001)(7696005)(6666004)(316002)(44832011)(83380400001)(2616005)(54906003)(36756003)(356005)(40460700003)(336012)(426003)(82740400003)(70206006)(86362001)(478600001)(16526019)(81166007)(70586007)(8676002)(186003)(5660300002)(4326008)(82310400005)(1076003)(110136005)(47076005)(8936002)(2906002)(26005)(36860700001)(40480700001)(36900700001)(309714004);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Dec 2022 07:51:27.1581 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9d45da11-2c5a-4677-c1d2-08dad43a0460 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT059.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7512 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751087968931536103?= X-GMAIL-MSGID: =?utf-8?q?1751087968931536103?= From: Perry Yuan Add one sysfs entry to control the CPU cores frequency boost state The attribute file can allow user to set max performance boosted or keeping at normal perf level. Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 66 ++++++++++++++++++++++++++++++++++-- 1 file changed, 64 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index b3a82cee2e83..6936df6e8642 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -774,12 +774,46 @@ static ssize_t show_energy_performance_preference( return sysfs_emit(buf, "%s\n", energy_perf_strings[preference]); } +static void amd_pstate_update_policies(void) +{ + int cpu; + + for_each_possible_cpu(cpu) + cpufreq_update_policy(cpu); +} + +static ssize_t show_boost(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + return sysfs_emit(buf, "%u\n", cppc_boost); +} + +static ssize_t store_boost(struct kobject *a, + struct kobj_attribute *b, + const char *buf, size_t count) +{ + bool new_state; + int ret; + + ret = kstrtobool(buf, &new_state); + if (ret) + return -EINVAL; + + mutex_lock(&amd_pstate_driver_lock); + cppc_boost = !!new_state; + amd_pstate_update_policies(); + mutex_unlock(&amd_pstate_driver_lock); + + return count; +} + cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); cpufreq_freq_attr_ro(amd_pstate_highest_perf); cpufreq_freq_attr_rw(energy_performance_preference); cpufreq_freq_attr_ro(energy_performance_available_preferences); +define_one_global_rw(boost); static struct freq_attr *amd_pstate_attr[] = { &amd_pstate_max_freq, @@ -797,6 +831,15 @@ static struct freq_attr *amd_pstate_epp_attr[] = { NULL, }; +static struct attribute *pstate_global_attributes[] = { + &boost.attr, + NULL +}; + +static const struct attribute_group amd_pstate_global_attr_group = { + .attrs = pstate_global_attributes, +}; + static inline void update_boost_state(void) { u64 misc_en; @@ -1415,9 +1458,28 @@ static int __init amd_pstate_init(void) ret = cpufreq_register_driver(default_pstate_driver); if (ret) - pr_err("failed to register amd pstate driver with return %d\n", - ret); + pr_err("failed to register driver with return %d\n", ret); + + amd_pstate_kobj = kobject_create_and_add("amd-pstate", &cpu_subsys.dev_root->kobj); + if (!amd_pstate_kobj) { + ret = -EINVAL; + pr_err("global sysfs registration failed.\n"); + goto kobject_free; + } + + ret = sysfs_create_group(amd_pstate_kobj, &amd_pstate_global_attr_group); + if (ret) { + pr_err("sysfs attribute export failed with error %d.\n", ret); + goto global_attr_free; + } + + return ret; +global_attr_free: + kobject_put(amd_pstate_kobj); +kobject_free: + kfree(cpudata); + cpufreq_unregister_driver(default_pstate_driver); return ret; } device_initcall(amd_pstate_init); From patchwork Fri Dec 2 07:47:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 28746 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp704243wrr; Thu, 1 Dec 2022 23:58:34 -0800 (PST) X-Google-Smtp-Source: AA0mqf4q91xQIhdkKpHmXaC4LrkzaXXFm1fApprVBmwXVjrPdzZm/sBHzG5h2v1aMo41W5H0Drbz X-Received: by 2002:a17:906:2345:b0:7ad:adfe:1ceb with SMTP id m5-20020a170906234500b007adadfe1cebmr51023787eja.89.1669967914479; Thu, 01 Dec 2022 23:58:34 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1669967914; cv=pass; d=google.com; s=arc-20160816; b=fnO+Vtu28I82WxJ+RNp+2APt3tJF+GHoA0UIB0hs7vW/cCgwgnjpx+m9b4pM5sHfLZ 8h3I5BZ1hQmlUl3++C6wZylWL74Tl4Lbzi0RhPvJyzdV54/hsqBHBRlF/+Ajl5mRYBoS aZGcHpg28V0TLslAabpsAVrFwR/ZLvgGM8S5OEqHqDJNBmGyvAymCeEd5Giqvv99Zwt1 RCekwcyvmYn0VNoYcbLt61BJj0tAb+FcRIJLNKeiCq+3oPUFDH981TS3n/Cvfq0uCIwD usq1M+tSFngUv9aA7gE3u7xJpVqwcKGwIv/MxH4ganze04WQ2i5hu0f1GpyaezB4+ssN P6/w== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=f+h6w480G7ILuZ3lh0HRzs+C09ou5AXJS7eh4zmsLT8=; b=XCcuMLKZAsjDLlELEWQ5UJUurAt7Ozls2D5NyQqdlJD/E4A/jSScexALKwxl4glt0l QbfULs9RtUe8c27f90VRUFs2oXUn6ueOMLhzCnMDrarw7+jm7Ai1vsW7Mbgj6OFGwzgi xiHTzt5rf/Q/Zm7q2qUc1bFQqX/Mrwg8Yn8Y5ctE0BkiGtJB8APAX8QMvr9DcJTX1nKf RTRSG4+uEUe2Ei0KUZWmbz5huSbLLPtF2bdP/xLpsffn7lWHcKkfxNtRTacv8TZL5bcj sCRdjb4bj5qlW89pgc6VSruXCN6aMFMq7UHy/VBSn1WzZhIwgVkrNQKJBswVcFRi0jQY KTdg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=O3ev4YLl; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Fri, 2 Dec 2022 01:51:26 -0600 From: Perry Yuan To: , , , CC: , , , , , , , , Subject: [PATCH v6 08/11] cpufreq: amd_pstate: add driver working mode status sysfs entry Date: Fri, 2 Dec 2022 15:47:16 +0800 Message-ID: <20221202074719.623673-9-perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202074719.623673-1-perry.yuan@amd.com> References: <20221202074719.623673-1-perry.yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT035:EE_|CY8PR12MB7196:EE_ X-MS-Office365-Filtering-Correlation-Id: 0725a9a5-0d64-410d-ae29-08dad43a185e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hWHbQGnDWsqcV2wE4NXSywMZaKUEwK6qTBxF8UPivRQSCpSDrf5Bi7gXqPl8svYUPfhjdmoSfKG98x2Xbp2LpK1VyHSmN3Q3tLs+nm+kuSRjNyof/NTgLomBSLa0ejFY+tr3kJhSGpJ5NsqniiqXvXP3gc2NGDmbdNtfu5DN+dnd1PudMcEUJumdgUyrCG7nBaoHse47jKAvL9bnQGl/CTLzbl1R1QCdsVyghu4TixgzQ5VqCJ27wrPFjjN33zn5qP2F/bamqe0qYS7jTtKQtVkh+nD2jZxrldzHLJ3YbuTwbUa/oMC41YQMXDqSaneorr+CBH9vkJSb+cdCFgddtnO6edlERDk24Q/EZ5LXF/kQLxXc5mpgBgoOd40cPtZKzW43OXbwRinMYVN7Ia5CEyKDTyp37FI0uZpdLPKKfNv7Dn9el3O7GLZ9AleBV0OnaQSXAsJb5TzTqUq3gNFHlYqCC9EQ8q++hrbIzyDzQikk2wmICi+AjiMr0V/s9va2NidL+APbxo0EQ90Nv5oEVNGhfWl4lniIs/EmHYvBL8y6fqCc/y9xVlTaEx9WfFaacOXRn5xVaAzVUnakYCsNVsu7hjT4yQKvq9w6T3a95ySu4jW/VKVGtoWZOGkU/ftvxtT2Jv7sTkb7z2SgGpn89epKi3uDKxVmwnbqUWACiJzfdAjltEw9vwg6rE1deRzKJ4MkbIPcWxe80MS9k8xUU9q0YsAbMv+JzEsyLgUaiKo= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(376002)(396003)(136003)(39860400002)(451199015)(46966006)(40470700004)(36840700001)(356005)(5660300002)(81166007)(2906002)(44832011)(82740400003)(8936002)(40480700001)(54906003)(70206006)(82310400005)(26005)(83380400001)(316002)(47076005)(7696005)(41300700001)(8676002)(4326008)(36860700001)(40460700003)(110136005)(478600001)(426003)(86362001)(36756003)(70586007)(16526019)(2616005)(1076003)(6666004)(186003)(336012)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Dec 2022 07:52:00.7615 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0725a9a5-0d64-410d-ae29-08dad43a185e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT035.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7196 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751088275838300761?= X-GMAIL-MSGID: =?utf-8?q?1751088275838300761?= From: Perry Yuan While amd-pstate driver was loaded with specific driver mode, it will need to check which mode is enabled for the pstate driver,add this sysfs entry to show the current status $ cat /sys/devices/system/cpu/amd-pstate/status active Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 44 ++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 6936df6e8642..7f748a579023 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -66,6 +66,8 @@ static bool cppc_active; static int cppc_load __initdata; static struct cpufreq_driver *default_pstate_driver; +static struct cpufreq_driver amd_pstate_epp_driver; +static struct cpufreq_driver amd_pstate_driver; static struct amd_cpudata **all_cpu_data; static struct amd_pstate_params global_params; @@ -807,6 +809,46 @@ static ssize_t store_boost(struct kobject *a, return count; } +static ssize_t amd_pstate_show_status(char *buf) +{ + if (!default_pstate_driver) + return sysfs_emit(buf, "off\n"); + + return sysfs_emit(buf, "%s\n", default_pstate_driver == &amd_pstate_epp_driver ? + "active" : "passive"); +} + +static int amd_pstate_update_status(const char *buf, size_t size) +{ + /* FIXME! */ + return -EOPNOTSUPP; +} + +static ssize_t show_status(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + ssize_t ret; + + mutex_lock(&amd_pstate_driver_lock); + ret = amd_pstate_show_status(buf); + mutex_unlock(&amd_pstate_driver_lock); + + return ret; +} + +static ssize_t store_status(struct kobject *a, struct kobj_attribute *b, + const char *buf, size_t count) +{ + char *p = memchr(buf, '\n', count); + int ret; + + mutex_lock(&amd_pstate_driver_lock); + ret = amd_pstate_update_status(buf, p ? p - buf : count); + mutex_unlock(&amd_pstate_driver_lock); + + return ret < 0 ? ret : count; +} + cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); @@ -814,6 +856,7 @@ cpufreq_freq_attr_ro(amd_pstate_highest_perf); cpufreq_freq_attr_rw(energy_performance_preference); cpufreq_freq_attr_ro(energy_performance_available_preferences); define_one_global_rw(boost); +define_one_global_rw(status); static struct freq_attr *amd_pstate_attr[] = { &amd_pstate_max_freq, @@ -833,6 +876,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = { static struct attribute *pstate_global_attributes[] = { &boost.attr, + &status.attr, NULL }; From patchwork Fri Dec 2 07:47:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 28751 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp707553wrr; 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Fri, 2 Dec 2022 01:52:00 -0600 From: Perry Yuan To: , , , CC: , , , , , , , , Subject: [PATCH v6 09/11] Documentation: amd-pstate: add amd pstate driver mode introduction Date: Fri, 2 Dec 2022 15:47:17 +0800 Message-ID: <20221202074719.623673-10-perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202074719.623673-1-perry.yuan@amd.com> References: <20221202074719.623673-1-perry.yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT049:EE_|CO6PR12MB5411:EE_ X-MS-Office365-Filtering-Correlation-Id: d14fb8f8-30b8-4e7e-777d-08dad43a1a95 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: SeQHYtGZhcaW42y8UOGHTVzDt0LtPJaWJbCGgmw+IJl1B+WnXANvtxK2VsZhBoIMTJUDJhxTWfR2wf0RFyY1/TSojplWxlav13YUpWaf8d+Sg1aEnxIuDNE+/Zr8sWEr6q9z0rnibaHEBp/fuNH5E/vPVp3Mxt3aafRvvp9WyqrEI5+9yZXiQ8ne81gyqlfyF+dUZiiQtU+YsPMvhOyJJrLk28SRbGW3uzXYPF9xNRSENMtuMVxD07wDWn9jzsrWyUoouCsswtaOfNRk5iEyfzbXbdZd0gSnzzwTsgFc4LAiLWK8C42Kniill/KsAK41Q+xiy9poEzcjtT+O/EdP0xmHTQGNtATxZRrpG02Rw7BziarhRc+msI3FQdQp5LAhS2flO7rHdppA8ykOwnwG9haX4MRuAfro2bHYHSYLgYqBU0ZalYjvO3RQWV5Iz65lqwMEq13IZAXbu57CF6PjrY087OMi8Gy6+5qvRbQ1RPecDo5d0Bhk1TZON+gRElazNXk4IjsqGr+RXktptP5P+lOZOT/BnIWSdwGOX4biU0yhTREFVKMDjChnKvCWTsgiTLa0E8RgbfuxEodEUa14PYRYJ7zVess5RpuzqpgtxZ/2OXK8AO/7rCASQSsYW5zGeBdREeO1j2yoXI/JLG/x6gW2odmtrrk6+B8gNFShicN3wYmlFDpwQ1zcoSC5Y9VLV1xLLl/lQbB2UEoIf7s4f8KSQZhgcd24CKmwIQudEJ4= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(136003)(39860400002)(346002)(396003)(451199015)(40470700004)(36840700001)(46966006)(40480700001)(81166007)(36756003)(86362001)(356005)(40460700003)(110136005)(316002)(44832011)(5660300002)(8936002)(70206006)(4326008)(70586007)(8676002)(41300700001)(478600001)(36860700001)(83380400001)(6666004)(82740400003)(2906002)(47076005)(26005)(7696005)(186003)(426003)(82310400005)(2616005)(16526019)(336012)(54906003)(1076003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Dec 2022 07:52:04.4760 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d14fb8f8-30b8-4e7e-777d-08dad43a1a95 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT049.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR12MB5411 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751088823727247271?= X-GMAIL-MSGID: =?utf-8?q?1751088823727247271?= From: Perry Yuan Introduce ``amd-pstate`` CPPC has two operation modes: * CPPC Autonomous (active) mode * CPPC non-autonomous (passive) mode. active mode and passive mode can be chosen by different kernel parameters. Signed-off-by: Perry Yuan --- Documentation/admin-guide/pm/amd-pstate.rst | 26 +++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index 33ab8ec8fc2f..62744dae3c5f 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -299,8 +299,30 @@ module which supports the new AMD P-States mechanism on most of the future AMD platforms. The AMD P-States mechanism is the more performance and energy efficiency frequency management method on AMD processors. -Kernel Module Options for ``amd-pstate`` -========================================= + +AMD Pstate Driver Operation Modes +================================= + +``amd_pstate`` CPPC has two operation modes: CPPC Autonomous(active) mode and +CPPC non-autonomous(passive) mode. +active mode and passive mode can be chosen by different kernel parameters. +When in Autonomous mode, CPPC ignores requests done in the Desired Performance +Target register and takes into account only the values set to the Minimum requested +performance, Maximum requested performance, and Energy Performance Preference +registers. When Autonomous is disabled, it only considers the Desired Performance Target. + +Active Mode +------------ + +``amd_pstate=active`` + +This is the low-level firmware control mode which is implemented by ``amd_pstate_epp`` +driver with ``amd_pstate=active`` passed to the kernel in the command line. +In this mode, ``amd_pstate_epp`` driver provides a hint to the hardware if software +wants to bias toward performance (0x0) or energy efficiency (0xff) to the CPPC firmware. +then CPPC power algorithm will calculate the runtime workload and adjust the realtime +cores frequency according to the power supply and thermal, core voltage and some other +hardware conditions. Passive Mode ------------ From patchwork Fri Dec 2 07:47:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 28750 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp707546wrr; Fri, 2 Dec 2022 00:07:15 -0800 (PST) X-Google-Smtp-Source: AA0mqf4dQae9+k3uosH5aRJfVQw57I0Ta4IOtmGb0NZMTqCNHkhM0X/cpqXnyrui7nIN58RLd0za X-Received: by 2002:a63:c48:0:b0:470:1186:de85 with SMTP id 8-20020a630c48000000b004701186de85mr48221323pgm.609.1669968435604; Fri, 02 Dec 2022 00:07:15 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1669968435; cv=pass; d=google.com; s=arc-20160816; b=T+YkfZ7fszM7ElQHLQpW1L7wBgR8qaIF0llWxjPLuiWBZb72kvrkqM3ZF3a65HboJB l5866fOggI2U2Qe0vvf4FzTbtlbV84pSVJgso54DDLXPmjRIcWE/VBpjrmFjNLuVkPIN 7GPM+gePiBj9Zb9R77erS45+Bvy/xvz77fCP+nffLlA30+Z/k5tvPvmg+omyDtWEE40j 4BY74dk9CD6gP5plwfMVczIyrQvShbP1dsOLeBy8Bwi5cmFv6SPRDvCBR/jCKO4xBzxd 4y2yJsDp/VxnNBSP0oNfXDLPy4iUbQEd0O8rx1DG5rnPEyESjfJ7fUbsveLN4rMXXI6n Cveg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Y7HUaZF2RWtW75YfO1ls7LGL9pKvYziwGx2Mp2RHCeg=; b=OF8e66xeB/zZwctte2gHrhjdTXI3YHAgm5XfczO1aAG2D9zsZJBTgrTfgN4VmVfaJ4 JFS09Ns8IUl8x7Gu8r22cPdUP5nbMcUPhgeqkJk9QyDDxGrxHzHMRX87Hdng86LZ98i5 gSxzRpGw1rQaB9VB1bhzZZjwfY6ippWv+hCDxJ0lXhSyeIOnEJmYh4gn5cRUtz9JhIwB d7ud6uDuqH/Ot05cEJrbbmPrSd5p4P7fVI79+Gmnqta3huCEx28jJWncekg3SSDLQsfD t1sk2jTe+n4Ylrk2danzWxgAhP6NKKWNBRqPyb67LupQDUV7mb7kDClS2BgF/Se7NEAg FSZQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=MgydiQWn; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Fri, 2 Dec 2022 01:52:04 -0600 From: Perry Yuan To: , , , CC: , , , , , , , , Subject: [PATCH v6 10/11] Documentation: introduce amd pstate active mode kernel command line options Date: Fri, 2 Dec 2022 15:47:18 +0800 Message-ID: <20221202074719.623673-11-perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202074719.623673-1-perry.yuan@amd.com> References: <20221202074719.623673-1-perry.yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT031:EE_|MW3PR12MB4475:EE_ X-MS-Office365-Filtering-Correlation-Id: 579428e6-ddfa-4135-95f6-08dad43a1cb4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qBYX4z5Odcct4mJP/ETsaZcsDf0PzgXPp8cX4dZJj454v6rgrWchNozJil1EzmU/1c47yFZQVMuY4IVm7vltL1xtDDJt719MGHfNNOiiArRtO87PLJQMf2vojOUwTx9x13x7mEY8JKepyoappGv0X6r/i5vIIBfiy5T1+la+jAxqJKy9M8ASwhf9H7Irx7Ks5vY5jAJq70KiPe0RGgS+C/iMl8GFV9IOtZvv6Z1bVtviSjO0tlIOPtQYQ4rF85ZwPdeQYF+4eCOBfRpMfB5V8AldDJCIJi4PFCCgFwL0hhKP2ndwjs3fNxobRMYFTobme7Euf/vKwGyvE/43tohB0i900G5p1jY4dLfYJIgl39biI2popvW+ymxpEuc5PR6CinuXTX10oReAty3J34/uNv+sTHm40cUsXEfV4dZ2z2XLwSceIlIRU/i8XfKAF7qa7caEl6VpHux4OZ7DNKMCijuv6qKrhRgSkMaYeGUUx0ltPVgHIvXbTRPGI9I+KrgH9AfTkMnbSGpu9MNF/u8w9d/O9G1Uqdm7bP4q49rq0mWpuyEpzwVtwnwlU2CJPzwSWJUffotl4a+6r/+gLYlmJ1/AG8YQH5meh0eSRViP8ZZo8Ep6ekuwOjPQKKaBNDZxCCaZMFrOGdEZ7CfxCeJEliqL1M6zAC3eF3ieTD+fkPLJH2HbJ/EoI2SRJ4aI7ZVCqyT8CagHKnxIkEizJbqJMzPZgk13RnbI0ZwPylgoCzg= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(376002)(136003)(346002)(396003)(451199015)(46966006)(40470700004)(36840700001)(16526019)(1076003)(5660300002)(82740400003)(86362001)(7696005)(336012)(186003)(36756003)(8936002)(4326008)(41300700001)(70586007)(2616005)(70206006)(8676002)(110136005)(54906003)(83380400001)(478600001)(426003)(47076005)(2906002)(26005)(40480700001)(316002)(44832011)(356005)(81166007)(40460700003)(6666004)(82310400005)(36860700001)(36900700001);DIR:OUT;SFP:1101; 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In autonomous mode SMU firmware decides frequencies at 1 ms timescale based on workload utilization, usage in other IPs, infrastructure limits such as power, thermals and so on. Signed-off-by: Perry Yuan --- Documentation/admin-guide/kernel-parameters.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 42af9ca0127e..73a02816f6f8 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -6970,3 +6970,10 @@ management firmware translates the requests into actual hardware states (core frequency, data fabric and memory clocks etc.) + active + Use amd_pstate_epp driver instance as the scaling driver, + driver provides a hint to the hardware if software wants + to bias toward performance (0x0) or energy efficiency (0xff) + to the CPPC firmware. then CPPC power algorithm will + calculate the runtime workload and adjust the realtime cores + frequency. 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Fri, 2 Dec 2022 01:52:07 -0600 From: Perry Yuan To: , , , CC: , , , , , , , , Subject: [PATCH v6 11/11] cpufreq: amd_pstate: convert sprintf with sysfs_emit() Date: Fri, 2 Dec 2022 15:47:19 +0800 Message-ID: <20221202074719.623673-12-perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202074719.623673-1-perry.yuan@amd.com> References: <20221202074719.623673-1-perry.yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT102:EE_|PH8PR12MB6721:EE_ X-MS-Office365-Filtering-Correlation-Id: 3b743755-5667-40cd-2d22-08dad43a1f33 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: SoymmnN7LgGuZgYqSx3acxsTbgbww4tcdhwCFoAf2acPsXQK2IU2hkFvm3f2tpQfNyGrMpS/JRpDkgjJZzZrnhr6PRC04h6i+cHSgZ8GVc/lkM6u5RrLHsTNc4IahNcWZq/In/+zeKwnFwFRsRnBqZBsrahIAF55MEdrE1BIuy2pxCEl1N+RBaqLfl7QrMfHiZryiIDRdHiC39KKCa2XvN7KfmHdSWGu71MjRi8j6cfe7dMYGCPMkIK8eUJg16WoYwHTUEoIf4eKUh3Sm5sZUIUjscp3iSyErFd/ui2nyeh2jy2M0Ob0sbc7PdXygbU8WlgQ9onAycyziy3DNWLRZCoa/u4CfV14yUcC+LjJgaunKrgbwv5Ds1bw1gYiWT1SnvmRAJDbN0OccAAnLX4AbaWhX6aT0/1c0YG3/gbqCbADzzOfZCNpnqwdgAFjmnlYUuBMMr4tW0alJcN16HNRfX2CVkcDpJi8mxTezo5am6tiR/fwePFDR/axc5hkQ31mB3Uqz800e4JFTLSD0+CnAV0378vqnCynbn0ei2yCabqFm2H1ZMh78W0D2Ym3AaHfIblepbX00qv02toZIZHxrhF2uywdSaaKf1YQgmh0Ey3eKZMx4QD14LvCuBiIxHeDRQouHa4ZM+yURMJHofC6P9HmMBy5p2ZypkmTrqTrE5zVYgn/CC2kKcQmon/8thr8O+xxGBWmpfY4+zHQPhWDgsXFxk7uZGG6Y9wzOWSJkSs= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(136003)(39860400002)(346002)(396003)(451199015)(40470700004)(36840700001)(46966006)(40480700001)(81166007)(36756003)(86362001)(356005)(40460700003)(110136005)(316002)(44832011)(5660300002)(8936002)(70206006)(4326008)(70586007)(8676002)(41300700001)(478600001)(36860700001)(83380400001)(6666004)(82740400003)(2906002)(47076005)(26005)(7696005)(186003)(426003)(82310400005)(2616005)(16526019)(336012)(54906003)(1076003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Dec 2022 07:52:12.2204 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3b743755-5667-40cd-2d22-08dad43a1f33 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT102.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6721 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751088201179841434?= X-GMAIL-MSGID: =?utf-8?q?1751088201179841434?= replace the sprintf with a more generic sysfs_emit function No potential function impact Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 7f748a579023..28e2dbaad542 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -696,7 +696,7 @@ static ssize_t show_amd_pstate_max_freq(struct cpufreq_policy *policy, if (max_freq < 0) return max_freq; - return sprintf(&buf[0], "%u\n", max_freq); + return sysfs_emit(buf, "%u\n", max_freq); } static ssize_t show_amd_pstate_lowest_nonlinear_freq(struct cpufreq_policy *policy, @@ -709,7 +709,7 @@ static ssize_t show_amd_pstate_lowest_nonlinear_freq(struct cpufreq_policy *poli if (freq < 0) return freq; - return sprintf(&buf[0], "%u\n", freq); + return sysfs_emit(buf, "%u\n", freq); } /* @@ -724,7 +724,7 @@ static ssize_t show_amd_pstate_highest_perf(struct cpufreq_policy *policy, perf = READ_ONCE(cpudata->highest_perf); - return sprintf(&buf[0], "%u\n", perf); + return sysfs_emit(buf, "%u\n", perf); } static ssize_t show_energy_performance_available_preferences(