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[2620:137:e000::1:20]) by mx.google.com with ESMTP id qf16-20020a1709077f1000b007c0c0d7c4c8si1082728ejc.44.2022.12.01.19.55.24; Thu, 01 Dec 2022 19:55:49 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=qXGOMAUQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232098AbiLBDpI (ORCPT + 99 others); Thu, 1 Dec 2022 22:45:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34068 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231195AbiLBDpF (ORCPT ); Thu, 1 Dec 2022 22:45:05 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1685E15739; Thu, 1 Dec 2022 19:44:59 -0800 (PST) X-UUID: 2a17ca0578314f7d8b1d7f4111d7d429-20221202 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=TAJ3T2+YM9j4HIm1trlpMZQnx74SQADR1vSM+bYGurk=; b=qXGOMAUQ//PZt5PLL7MoU7/h/vywAm9givDZt1eV9ULCWf8yiBmA0UCvjW23tnkFP7Re0yWnMwauhCCP6iRwT7N2vI9C9bo20A6sB8slTDeL6fmZIFksZ5tICumiCGPWdCnWNtaiWKcKIdYnLldjVEo0gC9ynRihQXgmZJa50rw=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:8904f67b-e575-4019-8b0e-0cc160290988,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:90 X-CID-INFO: VERSION:1.1.14,REQID:8904f67b-e575-4019-8b0e-0cc160290988,IP:0,URL :0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:90 X-CID-META: VersionHash:dcaaed0,CLOUDID:639e566c-41fe-47b6-8eb4-ec192dedaf7d,B ulkID:221202114456KP45APR0,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 2a17ca0578314f7d8b1d7f4111d7d429-20221202 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 797898477; Fri, 02 Dec 2022 11:44:54 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 2 Dec 2022 11:44:52 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 2 Dec 2022 11:44:52 +0800 From: Yunfei Dong To: Yunfei Dong , Rob Herring , Chen-Yu Tsai , Hans Verkuil , AngeloGioacchino Del Regno , Benjamin Gaignard , Tiffany Lin CC: Mauro Carvalho Chehab , Matthias Brugger , Hsin-Yi Wang , Daniel Vetter , Steve Cho , , , , , , Subject: [PATCH v4,1/3] media: dt-bindings: media: mediatek: vcodec: adapt to the 'clock-names' of different platforms Date: Fri, 2 Dec 2022 11:44:48 +0800 Message-ID: <20221202034450.3808-1-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, T_SPF_TEMPERROR,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751073003157181605?= X-GMAIL-MSGID: =?utf-8?q?1751073003157181605?= mt8195 and mt8192 have different clock numbers, separate 'clock-names' according to compatible name. Signed-off-by: Yunfei Dong --- compared with v3: - rewrite clock-names according to different platforms. Reference series: [1]: v5 of this series is presend by Allen-KH Cheng. message-id: 20221128143832.25584-4-allen-kh.cheng@mediatek.com --- .../media/mediatek,vcodec-subdev-decoder.yaml | 41 ++++++++++++++++--- 1 file changed, 35 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml index 7c5b4a91c59b..a08b2c814f40 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml @@ -110,15 +110,12 @@ patternProperties: Refer to bindings/iommu/mediatek,iommu.yaml. clocks: + minItems: 1 maxItems: 5 clock-names: - items: - - const: sel - - const: soc-vdec - - const: soc-lat - - const: vdec - - const: top + minItems: 1 + maxItems: 5 assigned-clocks: maxItems: 1 @@ -159,6 +156,38 @@ then: required: - interrupts +allOf: + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8192-vcodec-dec + then: + properties: + clock-names: + items: + - const: sel + - const: soc-vdec + - const: soc-lat + - const: vdec + - const: top + + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8195-vcodec-dec + then: + properties: + clock-names: + items: + - const: sel + - const: vdec + - const: lat + - const: top + additionalProperties: false examples: From patchwork Fri Dec 2 03:44:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?WXVuZmVpIERvbmcgKOiRo+S6kemjnik=?= X-Patchwork-Id: 28699 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp631827wrr; Thu, 1 Dec 2022 19:57:26 -0800 (PST) X-Google-Smtp-Source: AA0mqf6wKB+QZ+Dycjwf+nqRfuLuo7dWGMcqZ9TMNIoP7E32zcRfsoNfqVhhDuVRHPcgOOoVhIwx X-Received: by 2002:a63:fa49:0:b0:476:f92f:885b with SMTP id g9-20020a63fa49000000b00476f92f885bmr50516896pgk.31.1669953445952; Thu, 01 Dec 2022 19:57:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669953445; cv=none; d=google.com; s=arc-20160816; b=mNZpTTD8Of6O/zssW8NpCNS5HWlYL35YvklLHV2DmNXtYAk3eYCQ+hW32O7mx2Xhia wIDviSOh2xAaO3J2tpreg4EFjo78dsKLlM3H327j1Ux+Krsb5skwY5+VnhmhIstOqsRQ Y0vvOhUPrU6tt5ENI306Ma+ZFcyZTkSVthKYjn+YZgYI8mfiBLMthkqZ4xxA4Mlp68Rb kh1OYQrYFbAClyGqHfXXjYXsRGyGTP1MdLo0v+b2e5XoII5Uf3lpVmgp3AEtqBLlNGA5 9LZiGb+T7Esr424vcWlkGNYPY82mN2jVe/wSNa4mf0DRkXYMqmSIvERd16oI+cqwAwI/ uffQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=4vZnZiRiuzvJXiBOwiquPZDeka/mensDAmVnj/q79Rk=; b=u1VDoJKCSY1B3qvxhqCa/Q7y8ThQECb1/aECAIjzovtixgVNpYuqY2dBMfyZ5cnbPG qIDVXMHUaF2UzYl63xkSczkG8gBj32hD9L0SUD3ny8blQzKpKlEOsnw8zdJIIrUFBcWk tQceIvlveF1eU1RWbqL3arjhjIvQEUNwAB1MyoKQLTpORzcsXwh97lb42sOZ5nTJGOTH lAf1rX1mnJAmyXTwsEZTTMplJpl7ZJValGnmZkNQH+NMnymxsLTcgORIF2fra3vWo8Kx 1LD3wgAEMai7i8D1+XJmMuDH0SFrvdWMrhB/wxX1GdIbULieHFYI7EwgJOcH7jA3ZKQO 8Glw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=hDR0N7qo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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Changing the max reg value from 1 to 2. Adding the description for VDEC_SYS and VDEC_MISC. Signed-off-by: Yunfei Dong Acked-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno --- .../bindings/media/mediatek,vcodec-subdev-decoder.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml index a08b2c814f40..fffed7f515ae 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml @@ -61,7 +61,10 @@ properties: - mediatek,mt8195-vcodec-dec reg: - maxItems: 1 + minItems: 1 + items: + - description: VDEC_SYS register space + - description: VDEC_RACING_CTRL register space iommus: minItems: 1 @@ -98,6 +101,7 @@ patternProperties: reg: maxItems: 1 + description: VDEC_MISC register space interrupts: maxItems: 1 From patchwork Fri Dec 2 03:44:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?WXVuZmVpIERvbmcgKOiRo+S6kemjnik=?= X-Patchwork-Id: 28700 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp631829wrr; Thu, 1 Dec 2022 19:57:26 -0800 (PST) X-Google-Smtp-Source: AA0mqf42zU591TUc7FyRqmkveGwtf9aYKv3EdAQBvPowwdUSmRXzxBpH4MgL6Jtv2upiNy5u540P X-Received: by 2002:a05:6a00:1696:b0:53e:6656:d829 with SMTP id k22-20020a056a00169600b0053e6656d829mr72736455pfc.63.1669953446037; Thu, 01 Dec 2022 19:57:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669953446; cv=none; d=google.com; s=arc-20160816; b=IdQPxAi81PDUsHvRdrtn2z2VkH61mDdnbMgK0aKVg5KtT4PammB64/YKS8l+TcIf81 AXBYXo2XpCDWbWtB3So7HbZSkfw8d45dzm6o44dlxs77EhjotlbORGpByL6KXOFbQoo+ gYFRApYBS8fKfAcFt1Wtw0YjbYF2PraOx6BTkeB2RHMUP3TgHap2pJgUJm4F0fj2/vtG l+NQqBGWwQ3KT2ZW9DxIcmOjtOalroYuIm2cGfeR/jvBP1UOHpLQSn80PVPeplESzqzd khwvppYWs/c8HPxwNL9IM0jFhq/M1kwRr86ndjNcIq0V6nx02y5ZIm3mXRluTn8Okakz FJ1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=VCzoXxASQ6qGnA6F6VYifoo4ULC7Kk/0LQh8ibSLUMk=; b=XcGbWg0f8CRYCpn23tCul9Xr4EjMp0CYkTFoyF1e8qQ4mcyMR91Lm3uogDtRJCXbJD F60S6AZpNFYZCMXCU0zKESPdcmQjdt54KMcL4e/1kgVBd++1T/RiEq6W9DeS0/rtmgkE c66lrnoXEQN0kofCIdQWCD7W6GbzREfsjv4IaoXpI9HKhM5whVEmCtbpSWzJabkUadN6 62AZ68cHV9ciE+KfLKp7Rmdy0fI7Mqe3uQ3iTdfyBn/yZNIB777WhGAMpmZ4IV05uElv GiyXK4/3tgk/ngEarURxIzoDj97U/63+1eBStTj3UZv/HPcU0Q5LYYOXCMrykxSF7gu8 u/og== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=KogGqveB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id c14-20020a63ef4e000000b00477d61c12aesi6149726pgk.309.2022.12.01.19.57.12; Thu, 01 Dec 2022 19:57:26 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=KogGqveB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232312AbiLBDpN (ORCPT + 99 others); Thu, 1 Dec 2022 22:45:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34072 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232081AbiLBDpI (ORCPT ); Thu, 1 Dec 2022 22:45:08 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5002C83E95; Thu, 1 Dec 2022 19:45:03 -0800 (PST) X-UUID: 5faab9270cae4b65a0ef67ffb4583539-20221202 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=VCzoXxASQ6qGnA6F6VYifoo4ULC7Kk/0LQh8ibSLUMk=; b=KogGqveBfRmDHCBUfCY5XzffsbOMYJyXo8tfO0vIdJv7vRnH2tKn+fc/+0cfkHus5gk+pr+b9Arle+TBaoGy007XaHZuEyH2a+oz6z2w3402xwprAhHnPjYjOVvd+FQrvAbpAC1XhH34hR/s6wn87dENqgxfNSox03wshm5VmHI=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:2c61340c-da04-4e25-a1db-7147b45226e7,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:dcaaed0,CLOUDID:909e566c-41fe-47b6-8eb4-ec192dedaf7d,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 5faab9270cae4b65a0ef67ffb4583539-20221202 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 849256478; Fri, 02 Dec 2022 11:44:57 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 2 Dec 2022 11:44:55 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 2 Dec 2022 11:44:54 +0800 From: Yunfei Dong To: Yunfei Dong , Rob Herring , Chen-Yu Tsai , Hans Verkuil , AngeloGioacchino Del Regno , Benjamin Gaignard , Tiffany Lin CC: Mauro Carvalho Chehab , Matthias Brugger , Hsin-Yi Wang , Daniel Vetter , Steve Cho , , , , , , Subject: [PATCH v4,3/3] arm64: dts: mt8195: Add video decoder node Date: Fri, 2 Dec 2022 11:44:50 +0800 Message-ID: <20221202034450.3808-3-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221202034450.3808-1-yunfei.dong@mediatek.com> References: <20221202034450.3808-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751073104570584732?= X-GMAIL-MSGID: =?utf-8?q?1751073104570584732?= Add video decoder node to mt8195 device tree. Signed-off-by: Yunfei Dong Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 70 ++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 905d1a90b406..6829aa0dcf4c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1874,6 +1874,76 @@ power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; }; + video-codec@18000000 { + compatible = "mediatek,mt8195-vcodec-dec"; + mediatek,scp = <&scp>; + iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>; + #address-cells = <2>; + #size-cells = <2>; + reg = <0 0x18000000 0 0x1000>, + <0 0x18004000 0 0x1000>; + ranges = <0 0 0 0x18000000 0 0x26000>; + + video-codec@2000 { + compatible = "mediatek,mtk-vcodec-lat-soc"; + reg = <0 0x2000 0 0x800>; + iommus = <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>, + <&iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT>; + clocks = <&topckgen CLK_TOP_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D4>; + clock-names = "sel", "vdec", "lat", "top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; + }; + + video-codec@10000 { + compatible = "mediatek,mtk-vcodec-lat"; + reg = <0 0x10000 0 0x800>; + interrupts = ; + iommus = <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>; + clocks = <&topckgen CLK_TOP_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D4>; + clock-names = "sel", "vdec", "lat", "top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; + }; + + video-codec@25000 { + compatible = "mediatek,mtk-vcodec-core"; + reg = <0 0x25000 0 0x1000>; /* VDEC_CORE_MISC */ + interrupts = ; + iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_UFO_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PP_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PRED_RD_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PRED_WR_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PPWRAP_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_TILE_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_VLD_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_VLD2_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_AVC_MV_EXT>; + clocks = <&topckgen CLK_TOP_VDEC>, + <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D4>; + clock-names = "sel", "vdec", "lat", "top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; + }; + }; + larb24: larb@1800d000 { compatible = "mediatek,mt8195-smi-larb"; reg = <0 0x1800d000 0 0x1000>;