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[2620:137:e000::1:20]) by mx.google.com with ESMTP id v7-20020aa7cd47000000b0046c0e8b6cadsi1096840edw.450.2022.12.01.14.58.36; Thu, 01 Dec 2022 14:59:01 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@sberdevices.ru header.s=mail header.b=OSB0Cpsf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=sberdevices.ru Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231699AbiLAW5m (ORCPT + 99 others); Thu, 1 Dec 2022 17:57:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231575AbiLAW5i (ORCPT ); Thu, 1 Dec 2022 17:57:38 -0500 Received: from mx.sberdevices.ru (mx.sberdevices.ru [45.89.227.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2D3AFC7269; Thu, 1 Dec 2022 14:57:29 -0800 (PST) Received: from s-lin-edge02.sberdevices.ru (localhost [127.0.0.1]) by mx.sberdevices.ru (Postfix) with ESMTP id 825945FD09; Fri, 2 Dec 2022 01:57:27 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sberdevices.ru; s=mail; t=1669935447; bh=EQ9CARlmUHJwGJYtqkN5xpSRpu9hEHlDHl1ZbpZt5yY=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type; b=OSB0Cpsf4gX2hE4mYCIVr5A4vk7HKyQqqsx7issPWIb77oAGUKZb7fHkf3gXz4m/O u/eRI/swfEZW72yb6WdtFNY6tiT1qyjmPDUSp6T/dwX8v0QjwbhzToN9qr4hAYzpoP nRDfCK8Z7vC7yZvm9RdLXGYXpOFj+tCvdWc00oeMDs6BYTuWMlmHc3DjLYILWwhm7a YL0QlVrezUIL/gxKlVUqErrY4eqGzm6bR4GyBAwBSq8qfRPC0lygioIRwI3H7SpX+6 00YOjhKD7VXsudiTMeYE/vTi3I1gjPYWRvejAa5InIdoJYnn47LbRVBUKUfhceD2sb TYGu/+hrrN96Q== Received: from S-MS-EXCH01.sberdevices.ru (S-MS-EXCH01.sberdevices.ru [172.16.1.4]) by mx.sberdevices.ru (Postfix) with ESMTP; Fri, 2 Dec 2022 01:57:27 +0300 (MSK) From: Dmitry Rokosov To: , , , , , , , CC: , , , , , , , , Dmitry Rokosov Subject: [PATCH v8 01/11] dt-bindings: clock: meson: add A1 PLL clock controller bindings Date: Fri, 2 Dec 2022 01:56:53 +0300 Message-ID: <20221201225703.6507-2-ddrokosov@sberdevices.ru> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20221201225703.6507-1-ddrokosov@sberdevices.ru> References: <20221201225703.6507-1-ddrokosov@sberdevices.ru> MIME-Version: 1.0 X-Originating-IP: [172.16.1.6] X-ClientProxiedBy: S-MS-EXCH02.sberdevices.ru (172.16.1.5) To S-MS-EXCH01.sberdevices.ru (172.16.1.4) X-KSMG-Rule-ID: 4 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Status: not scanned, disabled by settings X-KSMG-AntiSpam-Interceptor-Info: not scanned X-KSMG-AntiPhishing: not scanned, disabled by settings X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 1.1.2.30, bases: 2022/12/01 20:49:00 #20634374 X-KSMG-AntiVirus-Status: Clean, skipped X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751054329829718347?= X-GMAIL-MSGID: =?utf-8?q?1751054329829718347?= From: Jian Hu Add the documentation to support Amlogic A1 PLL clock driver, and add A1 PLL clock controller bindings. Signed-off-by: Jian Hu Signed-off-by: Dmitry Rokosov --- .../bindings/clock/amlogic,a1-pll-clkc.yaml | 52 +++++++++++++++++++ include/dt-bindings/clock/a1-pll-clkc.h | 16 ++++++ 2 files changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml create mode 100644 include/dt-bindings/clock/a1-pll-clkc.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml new file mode 100644 index 000000000000..d67250fbeece --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/amlogic,a1-pll-clkc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic Meson A/C serials PLL Clock Control Unit Device Tree Bindings + +maintainers: + - Neil Armstrong + - Jerome Brunet + - Jian Hu + +properties: + compatible: + const: amlogic,a1-pll-clkc + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + + clocks: + items: + - description: input xtal_fixpll + - description: input xtal_hifipll + + clock-names: + items: + - const: xtal_fixpll + - const: xtal_hifipll + +required: + - compatible + - "#clock-cells" + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + clkc_pll: pll-clock-controller@7c80 { + compatible = "amlogic,a1-pll-clkc"; + reg = <0 0x7c80 0 0x18c>; + #clock-cells = <1>; + clocks = <&clkc_periphs 1>, + <&clkc_periphs 4>; + clock-names = "xtal_fixpll", "xtal_hifipll"; + }; diff --git a/include/dt-bindings/clock/a1-pll-clkc.h b/include/dt-bindings/clock/a1-pll-clkc.h new file mode 100644 index 000000000000..58eae237e503 --- /dev/null +++ b/include/dt-bindings/clock/a1-pll-clkc.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __A1_PLL_CLKC_H +#define __A1_PLL_CLKC_H + +#define CLKID_FIXED_PLL 1 +#define CLKID_FCLK_DIV2 6 +#define CLKID_FCLK_DIV3 7 +#define CLKID_FCLK_DIV5 8 +#define CLKID_FCLK_DIV7 9 +#define CLKID_HIFI_PLL 10 + +#endif /* __A1_PLL_CLKC_H */ From patchwork Thu Dec 1 22:56:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Rokosov X-Patchwork-Id: 28576 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp528480wrr; Thu, 1 Dec 2022 14:59:34 -0800 (PST) X-Google-Smtp-Source: AA0mqf6YpLDb1CVka2Q50Oe8Z3yk6KbY94TFGLeiiiN2Acewjpb9VM3zvGFgwxO7GJiEQFMiYsfY X-Received: by 2002:a05:6402:2949:b0:468:fb6b:3a79 with SMTP id ed9-20020a056402294900b00468fb6b3a79mr3886607edb.63.1669935574642; Thu, 01 Dec 2022 14:59:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669935574; cv=none; d=google.com; s=arc-20160816; b=ziT4nLk2jq6G/I8mfp5RnvnChpd6fik06RWS+etLUY7U/G+itDvE6+hXvwPQuxRZPJ bwAtncD4VxRjS+HEHKz1tCyZzIAEOy8SM5g+ZnOQwpWoWwrax9mR/QFOltYInEpKVsY9 cK2iUVcVIpYneUgk1uzHvweipflAKH1C9AW7IEAj8D42vFtDqIMnHi92oU+e/ftGXKjw uKDr2fZ/w4D3DAZlOpMnD1GgEZ2/bZ3jFWh1jzU7ihJD3xIZ7hZ+azmRfY8URzjuMJM9 Hv0rOs/s4aJ5RTDS6i16KQHPzv8cmpDr4XGtLELNJ4nhX8zDVI9i9JVZvsS50XaU3mi8 Fyhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=UKrWsAOhIJL4BKEX1Ufd25mHpT88I1IOGuLSaqJ24bw=; b=xPMETG1A3du+If4qSZUncXJ6ZrZjU18X70Cj75/KBS6KFCsqdx7X5MXQGdmdhF0bVi PIdgA2l5WM2vSRK2KdU/SOvHcUb4mwQCeB8XtWhD8fp2oR6AS4vjgr3uBCd0E8QUvrmb MTrLOZ1QhUm7in8N+5mvZeh1TcrvifuerE4B05QA8PJFFMqRP4aLiKXtQdwmim0DigLG kquWV+2WEfODAX9YexpV2GDn3Yed+J4D9fvZU6ggO5Tea33rdN7SFCNdP4gO9U/zfb2e Pa0TP+4jC+DF70Qa+GOevynaVui2jVPmUP8bXfRE+z+cSRv77ls6p+kY3R7wLOA6szG6 K8Hw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sberdevices.ru header.s=mail header.b=HgbSMrJ6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=sberdevices.ru Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id di7-20020a170906730700b007c00323cc16si5109864ejc.973.2022.12.01.14.59.10; Thu, 01 Dec 2022 14:59:34 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@sberdevices.ru header.s=mail header.b=HgbSMrJ6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=sberdevices.ru Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231777AbiLAW5w (ORCPT + 99 others); Thu, 1 Dec 2022 17:57:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50960 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231642AbiLAW5i (ORCPT ); Thu, 1 Dec 2022 17:57:38 -0500 Received: from mx.sberdevices.ru (mx.sberdevices.ru [45.89.227.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E249C726C; Thu, 1 Dec 2022 14:57:30 -0800 (PST) Received: from s-lin-edge02.sberdevices.ru (localhost [127.0.0.1]) by mx.sberdevices.ru (Postfix) with ESMTP id C5D885FD0B; Fri, 2 Dec 2022 01:57:28 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sberdevices.ru; s=mail; t=1669935448; bh=UKrWsAOhIJL4BKEX1Ufd25mHpT88I1IOGuLSaqJ24bw=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type; b=HgbSMrJ6DZ4te2zmP2j7VsCP2uKQrR97hFMvUcmebKJY96vOKlYe0HrP4SUechJVC ybQahPa6bDgjE1j7OprgAVgX490c5udD+CxXlgnxKoiY0Swlz14Y5C3upGJqzJV843 3c64uNJxzQilzvhPYtb6pEsVWMOrn8ivHK7uLqJRQetAYBuxkmZl+dcufu/6ZoL7rn lT0T58RoIzBXE1pp47DHgeRROMVJjDEq9m6YKYWTv10QM58sL6t5esyKFmjKHwbNms OEVvH9hergNPYgV+baLoFMzmLXtlUMBdMp68O9PMzlNKrkuiFQVfkwI1BBMLjiiKRX eDGjm5v6M307Q== Received: from S-MS-EXCH01.sberdevices.ru (S-MS-EXCH01.sberdevices.ru [172.16.1.4]) by mx.sberdevices.ru (Postfix) with ESMTP; Fri, 2 Dec 2022 01:57:28 +0300 (MSK) From: Dmitry Rokosov To: , , , , , , , CC: , , , , , , , , Dmitry Rokosov Subject: [PATCH v8 02/11] clk: meson: a1: add support for Amlogic A1 PLL clock driver Date: Fri, 2 Dec 2022 01:56:54 +0300 Message-ID: <20221201225703.6507-3-ddrokosov@sberdevices.ru> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20221201225703.6507-1-ddrokosov@sberdevices.ru> References: <20221201225703.6507-1-ddrokosov@sberdevices.ru> MIME-Version: 1.0 X-Originating-IP: [172.16.1.6] X-ClientProxiedBy: S-MS-EXCH02.sberdevices.ru (172.16.1.5) To S-MS-EXCH01.sberdevices.ru (172.16.1.4) X-KSMG-Rule-ID: 4 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Status: not scanned, disabled by settings X-KSMG-AntiSpam-Interceptor-Info: not scanned X-KSMG-AntiPhishing: not scanned, disabled by settings X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 1.1.2.30, bases: 2022/12/01 20:49:00 #20634374 X-KSMG-AntiVirus-Status: Clean, skipped X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751054365418951590?= X-GMAIL-MSGID: =?utf-8?q?1751054365418951590?= From: Jian Hu The Amlogic A1 clock includes three drivers: pll clocks, peripheral clocks, CPU clocks. sys pll and CPU clocks will be sent in next patch. Unlike the previous series, there is no EE/AO domain in A1 CLK controllers. Signed-off-by: Jian Hu Signed-off-by: Dmitry Rokosov --- drivers/clk/meson/Kconfig | 9 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/a1-pll.c | 360 +++++++++++++++++++++++++++++++++++++ drivers/clk/meson/a1-pll.h | 56 ++++++ 4 files changed, 426 insertions(+) create mode 100644 drivers/clk/meson/a1-pll.c create mode 100644 drivers/clk/meson/a1-pll.h diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index fc002c155bc3..ab34662b24f0 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -99,6 +99,15 @@ config COMMON_CLK_AXG_AUDIO Support for the audio clock controller on AmLogic A113D devices, aka axg, Say Y if you want audio subsystem to work. +config COMMON_CLK_A1_PLL + bool + depends on ARCH_MESON + select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_PLL + help + Support for the PLL clock controller on Amlogic A113L device, + aka a1. Say Y if you want PLL to work. + config COMMON_CLK_G12A tristate "G12 and SM1 SoC clock controllers support" depends on ARM64 diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 6eca2a406ee3..2f17f475a48f 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o +obj-$(CONFIG_COMMON_CLK_A1_PLL) += a1-pll.o obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o diff --git a/drivers/clk/meson/a1-pll.c b/drivers/clk/meson/a1-pll.c new file mode 100644 index 000000000000..69c1ca07d041 --- /dev/null +++ b/drivers/clk/meson/a1-pll.c @@ -0,0 +1,360 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + * Author: Jian Hu + */ + +#include +#include +#include +#include "a1-pll.h" +#include "clk-pll.h" +#include "clk-regmap.h" + +static struct clk_regmap a1_fixed_pll_dco = { + .data = &(struct meson_clk_pll_data){ + .en = { + .reg_off = ANACTRL_FIXPLL_CTRL0, + .shift = 28, + .width = 1, + }, + .m = { + .reg_off = ANACTRL_FIXPLL_CTRL0, + .shift = 0, + .width = 8, + }, + .n = { + .reg_off = ANACTRL_FIXPLL_CTRL0, + .shift = 10, + .width = 5, + }, + .frac = { + .reg_off = ANACTRL_FIXPLL_CTRL1, + .shift = 0, + .width = 19, + }, + .l = { + .reg_off = ANACTRL_FIXPLL_STS, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = ANACTRL_FIXPLL_CTRL0, + .shift = 29, + .width = 1, + }, + }, + .hw.init = &(struct clk_init_data){ + .name = "fixed_pll_dco", + .ops = &meson_clk_pll_ro_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal_fixpll", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap a1_fixed_pll = { + .data = &(struct clk_regmap_gate_data){ + .offset = ANACTRL_FIXPLL_CTRL0, + .bit_idx = 20, + }, + .hw.init = &(struct clk_init_data) { + .name = "fixed_pll", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_fixed_pll_dco.hw + }, + .num_parents = 1, + /* + * It is enough that the fdiv leaf has critical flag, + * No critical or unused flag here. + */ + }, +}; + +static const struct pll_mult_range a1_hifi_pll_mult_range = { + .min = 32, + .max = 64, +}; + +static const struct reg_sequence a1_hifi_init_regs[] = { + { .reg = ANACTRL_HIFIPLL_CTRL1, .def = 0x01800000 }, + { .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x00001100 }, + { .reg = ANACTRL_HIFIPLL_CTRL3, .def = 0x100a1100 }, + { .reg = ANACTRL_HIFIPLL_CTRL4, .def = 0x00302000 }, + { .reg = ANACTRL_HIFIPLL_CTRL0, .def = 0x01f18440 }, +}; + +static struct clk_regmap a1_hifi_pll = { + .data = &(struct meson_clk_pll_data){ + .en = { + .reg_off = ANACTRL_HIFIPLL_CTRL0, + .shift = 28, + .width = 1, + }, + .m = { + .reg_off = ANACTRL_HIFIPLL_CTRL0, + .shift = 0, + .width = 8, + }, + .n = { + .reg_off = ANACTRL_HIFIPLL_CTRL0, + .shift = 10, + .width = 5, + }, + .frac = { + .reg_off = ANACTRL_HIFIPLL_CTRL1, + .shift = 0, + .width = 19, + }, + .l = { + .reg_off = ANACTRL_HIFIPLL_STS, + .shift = 31, + .width = 1, + }, + .current_en = { + .reg_off = ANACTRL_HIFIPLL_CTRL0, + .shift = 26, + .width = 1, + }, + .l_detect = { + .reg_off = ANACTRL_HIFIPLL_CTRL2, + .shift = 6, + .width = 1, + }, + .range = &a1_hifi_pll_mult_range, + .init_regs = a1_hifi_init_regs, + .init_count = ARRAY_SIZE(a1_hifi_init_regs), + }, + .hw.init = &(struct clk_init_data){ + .name = "hifi_pll", + .ops = &meson_clk_pll_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal_hifipll", + }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor a1_fclk_div2_div = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div2_div", + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_fixed_pll.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap a1_fclk_div2 = { + .data = &(struct clk_regmap_gate_data){ + .offset = ANACTRL_FIXPLL_CTRL0, + .bit_idx = 21, + }, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div2", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_fclk_div2_div.hw + }, + .num_parents = 1, + /* + * This clock is used by DDR clock in BL2 firmware + * and is required by the platform to operate correctly. + * Until the following condition are met, we need this clock to + * be marked as critical: + * a) Mark the clock used by a firmware resource, if possible + * b) CCF has a clock hand-off mechanism to make the sure the + * clock stays on until the proper driver comes along + */ + .flags = CLK_IS_CRITICAL, + }, +}; + +static struct clk_fixed_factor a1_fclk_div3_div = { + .mult = 1, + .div = 3, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div3_div", + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_fixed_pll.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap a1_fclk_div3 = { + .data = &(struct clk_regmap_gate_data){ + .offset = ANACTRL_FIXPLL_CTRL0, + .bit_idx = 22, + }, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div3", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_fclk_div3_div.hw + }, + .num_parents = 1, + /* + * This clock is used by APB bus which is set in boot ROM code + * and is required by the platform to operate correctly. + * About critical, refer to a1_fclk_div2. + */ + .flags = CLK_IS_CRITICAL, + }, +}; + +static struct clk_fixed_factor a1_fclk_div5_div = { + .mult = 1, + .div = 5, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div5_div", + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_fixed_pll.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap a1_fclk_div5 = { + .data = &(struct clk_regmap_gate_data){ + .offset = ANACTRL_FIXPLL_CTRL0, + .bit_idx = 23, + }, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div5", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_fclk_div5_div.hw + }, + .num_parents = 1, + /* + * This clock is used by AXI bus which setted in Romcode + * and is required by the platform to operate correctly. + * About critical, refer to a1_fclk_div2. + */ + .flags = CLK_IS_CRITICAL, + }, +}; + +static struct clk_fixed_factor a1_fclk_div7_div = { + .mult = 1, + .div = 7, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div7_div", + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_fixed_pll.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap a1_fclk_div7 = { + .data = &(struct clk_regmap_gate_data){ + .offset = ANACTRL_FIXPLL_CTRL0, + .bit_idx = 24, + }, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div7", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_fclk_div7_div.hw + }, + .num_parents = 1, + }, +}; + +/* Array of all clocks provided by this provider */ +static struct clk_hw_onecell_data a1_pll_hw_onecell_data = { + .hws = { + [CLKID_FIXED_PLL_DCO] = &a1_fixed_pll_dco.hw, + [CLKID_FIXED_PLL] = &a1_fixed_pll.hw, + [CLKID_HIFI_PLL] = &a1_hifi_pll.hw, + [CLKID_FCLK_DIV2] = &a1_fclk_div2.hw, + [CLKID_FCLK_DIV3] = &a1_fclk_div3.hw, + [CLKID_FCLK_DIV5] = &a1_fclk_div5.hw, + [CLKID_FCLK_DIV7] = &a1_fclk_div7.hw, + [CLKID_FCLK_DIV2_DIV] = &a1_fclk_div2_div.hw, + [CLKID_FCLK_DIV3_DIV] = &a1_fclk_div3_div.hw, + [CLKID_FCLK_DIV5_DIV] = &a1_fclk_div5_div.hw, + [CLKID_FCLK_DIV7_DIV] = &a1_fclk_div7_div.hw, + [NR_PLL_CLKS] = NULL, + }, + .num = NR_PLL_CLKS, +}; + +static struct clk_regmap *const a1_pll_regmaps[] = { + &a1_fixed_pll_dco, + &a1_fixed_pll, + &a1_hifi_pll, + &a1_fclk_div2, + &a1_fclk_div3, + &a1_fclk_div5, + &a1_fclk_div7, +}; + +static struct regmap_config clkc_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, +}; + +static int meson_a1_pll_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct resource *res; + void __iomem *base; + struct regmap *map; + int ret, i; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + map = devm_regmap_init_mmio(dev, base, &clkc_regmap_config); + if (IS_ERR(map)) + return PTR_ERR(map); + + /* Populate regmap for the regmap backed clocks */ + for (i = 0; i < ARRAY_SIZE(a1_pll_regmaps); i++) + a1_pll_regmaps[i]->map = map; + + for (i = 0; i < a1_pll_hw_onecell_data.num; i++) { + /* array might be sparse */ + if (!a1_pll_hw_onecell_data.hws[i]) + continue; + + ret = devm_clk_hw_register(dev, a1_pll_hw_onecell_data.hws[i]); + if (ret) { + dev_err(dev, "Clock registration failed\n"); + return ret; + } + } + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + &a1_pll_hw_onecell_data); +} + +static const struct of_device_id clkc_match_table[] = { + { .compatible = "amlogic,a1-pll-clkc", }, + {} +}; + +static struct platform_driver a1_pll_driver = { + .probe = meson_a1_pll_probe, + .driver = { + .name = "a1-pll-clkc", + .of_match_table = clkc_match_table, + }, +}; + +builtin_platform_driver(a1_pll_driver); diff --git a/drivers/clk/meson/a1-pll.h b/drivers/clk/meson/a1-pll.h new file mode 100644 index 000000000000..8ded267061ad --- /dev/null +++ b/drivers/clk/meson/a1-pll.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __A1_PLL_H +#define __A1_PLL_H + +/* PLL register offset */ +#define ANACTRL_FIXPLL_CTRL0 0x0 +#define ANACTRL_FIXPLL_CTRL1 0x4 +#define ANACTRL_FIXPLL_CTRL2 0x8 +#define ANACTRL_FIXPLL_CTRL3 0xc +#define ANACTRL_FIXPLL_CTRL4 0x10 +#define ANACTRL_FIXPLL_STS 0x14 +#define ANACTRL_SYSPLL_CTRL0 0x80 +#define ANACTRL_SYSPLL_CTRL1 0x84 +#define ANACTRL_SYSPLL_CTRL2 0x88 +#define ANACTRL_SYSPLL_CTRL3 0x8c +#define ANACTRL_SYSPLL_CTRL4 0x90 +#define ANACTRL_SYSPLL_STS 0x94 +#define ANACTRL_HIFIPLL_CTRL0 0xc0 +#define ANACTRL_HIFIPLL_CTRL1 0xc4 +#define ANACTRL_HIFIPLL_CTRL2 0xc8 +#define ANACTRL_HIFIPLL_CTRL3 0xcc +#define ANACTRL_HIFIPLL_CTRL4 0xd0 +#define ANACTRL_HIFIPLL_STS 0xd4 +#define ANACTRL_AUDDDS_CTRL0 0x100 +#define ANACTRL_AUDDDS_CTRL1 0x104 +#define ANACTRL_AUDDDS_CTRL2 0x108 +#define ANACTRL_AUDDDS_CTRL3 0x10c +#define ANACTRL_AUDDDS_CTRL4 0x110 +#define ANACTRL_AUDDDS_STS 0x114 +#define ANACTRL_MISCTOP_CTRL0 0x140 +#define ANACTRL_POR_CNTL 0x188 + +/* + * CLKID index values + * + * These indices are entirely contrived and do not map onto the hardware. + * It has now been decided to expose everything by default in the DT header: + * include/dt-bindings/clock/a1-pll-clkc.h. Only the clocks ids we don't want + * to expose, such as the internal muxes and dividers of composite clocks, + * will remain defined here. + */ +#define CLKID_FIXED_PLL_DCO 0 +#define CLKID_FCLK_DIV2_DIV 2 +#define CLKID_FCLK_DIV3_DIV 3 +#define CLKID_FCLK_DIV5_DIV 4 +#define CLKID_FCLK_DIV7_DIV 5 +#define NR_PLL_CLKS 11 + +/* include the CLKIDs that have been made part of the DT binding */ +#include + +#endif /* __A1_PLL_H */ From patchwork Thu Dec 1 22:56:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Rokosov X-Patchwork-Id: 28577 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp528568wrr; Thu, 1 Dec 2022 14:59:44 -0800 (PST) X-Google-Smtp-Source: AA0mqf6p2Drr80QLgWGBuXshtMEyzePuEv/xlrO4JT1YRv0B/h51BJTX3Tto9krrASH7gnXopTlm X-Received: by 2002:aa7:db19:0:b0:46b:fc0d:ddc0 with SMTP id t25-20020aa7db19000000b0046bfc0dddc0mr3693682eds.214.1669935584600; Thu, 01 Dec 2022 14:59:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669935584; cv=none; d=google.com; s=arc-20160816; b=gBWttra587p70LfTd//dxokt+I9EsNzcD25w79aKFnmVinywxquF6BmZ+zN41AXxWu 9wJvJK4B7wYGZWPKg2YLjLSA08zbLmtSHJfEedNFRd8rmuY7IzxbbFf1dcz20B8OQlA8 v6ioG6/5V1WUgEDBrg8sIFeD33dFHoxyBlLxCKjQk7B0U+CjqEJGR/Da9h+Tu/8vYZID v1bzc6V8qZHZ2w7HsfX0VbnHs5r8QeFeTtiXLJZube8rzpkj3kjgqwSc8Z7I4rj1Vci/ nnRhmUeZOhDGADC9tFEkecIMlJdH5ntuxvZcbc51f4RPK+BMaezxRNtAS7dcHvbL1izn 42UQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=C+D9ln6/8IKJiYBIMQFlZoO/nexz66NO8XBFu+5s7R0=; b=wUdSSJnzuXgtYIQZVR8mTqaTWR82mq+IdWuOeV6gO+sup73z/XmSJdAD5dEDMIUB2v wsfO9SwJuSwkO15ldsxE2GZaBqrODiMY9S9W5d3NLmzHqylaCpG8RSOaZ+9D8l+NLJXF 43KBoGHDBpqGYZx6sKQvcozeLYGvsstZXnodymJakcR7199JCIt+syWRXjJHaepCEqXt 5agSOWeot85aDmrS7xLu3ENa156A29GD6ALvZRURlA1k0t5rN7SW9kPziQ09rT9BxvTu /m6FVZXG3jMlTe0tsTnRyUN4Z8chBDymfzxsueDJ49fUlFq1Q4Px6SzzKjQQY6FWyq2p kURQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sberdevices.ru header.s=mail header.b=LN5Qi32C; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=sberdevices.ru Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id r13-20020a05640251cd00b0046bc9cbd8f0si4039235edd.504.2022.12.01.14.59.21; Thu, 01 Dec 2022 14:59:44 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@sberdevices.ru header.s=mail header.b=LN5Qi32C; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=sberdevices.ru Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231782AbiLAW54 (ORCPT + 99 others); Thu, 1 Dec 2022 17:57:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51062 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231639AbiLAW5i (ORCPT ); Thu, 1 Dec 2022 17:57:38 -0500 Received: from mx.sberdevices.ru (mx.sberdevices.ru [45.89.227.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 61B4AC4CF9; Thu, 1 Dec 2022 14:57:31 -0800 (PST) Received: from s-lin-edge02.sberdevices.ru (localhost [127.0.0.1]) by mx.sberdevices.ru (Postfix) with ESMTP id AFD905FD0C; Fri, 2 Dec 2022 01:57:29 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sberdevices.ru; s=mail; t=1669935449; bh=C+D9ln6/8IKJiYBIMQFlZoO/nexz66NO8XBFu+5s7R0=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type; b=LN5Qi32C80ixRU5+vFMI2CVVT8SyRzcXz4nIKD3nbDX98QyL6pgtsYdCka3lh1dEL 329TerTENXCRvuo+/zwnkWWJZTjgCTgRiu7+te3MzXoZRDrCA59OWVlsGmOjqWvN9W X6S1ylFSVO4BxBlQkCZX9q2JOio4bzvScVlKt2lFwBBzV9CRj0JMkEllREtyOB6WDH +6+qL33DJwo9+WRd3FFgLaRfNdwT53wd2zHT+UKl7RUbo1H6qvFO5yDzE7ua0Z2aBM WdCUZ6fnlXE+DXUbzxXigtdNr46AKV6dxESrkQzqIUOziehsupzF3NzcszSXUwv8bQ 8Fxz7ck/0oO7Q== Received: from S-MS-EXCH01.sberdevices.ru (S-MS-EXCH01.sberdevices.ru [172.16.1.4]) by mx.sberdevices.ru (Postfix) with ESMTP; Fri, 2 Dec 2022 01:57:29 +0300 (MSK) From: Dmitry Rokosov To: , , , , , , , CC: , , , , , , , , Dmitry Rokosov Subject: [PATCH v8 03/11] dt-bindings: clock: meson: add A1 peripheral clock controller bindings Date: Fri, 2 Dec 2022 01:56:55 +0300 Message-ID: <20221201225703.6507-4-ddrokosov@sberdevices.ru> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20221201225703.6507-1-ddrokosov@sberdevices.ru> References: <20221201225703.6507-1-ddrokosov@sberdevices.ru> MIME-Version: 1.0 X-Originating-IP: [172.16.1.6] X-ClientProxiedBy: S-MS-EXCH02.sberdevices.ru (172.16.1.5) To S-MS-EXCH01.sberdevices.ru (172.16.1.4) X-KSMG-Rule-ID: 4 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Status: not scanned, disabled by settings X-KSMG-AntiSpam-Interceptor-Info: not scanned X-KSMG-AntiPhishing: not scanned, disabled by settings X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 1.1.2.30, bases: 2022/12/01 20:49:00 #20634374 X-KSMG-AntiVirus-Status: Clean, skipped X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751054375240858493?= X-GMAIL-MSGID: =?utf-8?q?1751054375240858493?= From: Jian Hu Add the documentation to support Amlogic A1 peripheral clock driver, and add A1 peripheral clock controller bindings. Signed-off-by: Jian Hu Signed-off-by: Dmitry Rokosov --- .../bindings/clock/amlogic,a1-clkc.yaml | 65 ++++++++++++ include/dt-bindings/clock/a1-clkc.h | 98 +++++++++++++++++++ 2 files changed, 163 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml create mode 100644 include/dt-bindings/clock/a1-clkc.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml new file mode 100644 index 000000000000..7729850046cf --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml @@ -0,0 +1,65 @@ +#SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/amlogic,a1-clkc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic Meson A/C serials Peripheral Clock Control Unit Device Tree Bindings + +maintainers: + - Neil Armstrong + - Jerome Brunet + - Jian Hu + +properties: + compatible: + const: amlogic,a1-periphs-clkc + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + + clocks: + items: + - description: input fixed pll div2 + - description: input fixed pll div3 + - description: input fixed pll div5 + - description: input fixed pll div7 + - description: input hifi pll + - description: input oscillator (usually at 24MHz) + + clock-names: + items: + - const: fclk_div2 + - const: fclk_div3 + - const: fclk_div5 + - const: fclk_div7 + - const: hifi_pll + - const: xtal + +required: + - compatible + - "#clock-cells" + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + clkc_periphs: periphs-clock-controller { + compatible = "amlogic,a1-periphs-clkc"; + reg = <0 0x800 0 0x104>; + #clock-cells = <1>; + clocks = <&clkc_pll 6>, + <&clkc_pll 7>, + <&clkc_pll 8>, + <&clkc_pll 9>, + <&clkc_pll 10>, + <&xtal>; + clock-names = "fclk_div2", "fclk_div3", "fclk_div5", + "fclk_div7", "hifi_pll", "xtal"; + }; diff --git a/include/dt-bindings/clock/a1-clkc.h b/include/dt-bindings/clock/a1-clkc.h new file mode 100644 index 000000000000..9bb36fca86dd --- /dev/null +++ b/include/dt-bindings/clock/a1-clkc.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __A1_CLKC_H +#define __A1_CLKC_H + +#define CLKID_XTAL_FIXPLL 1 +#define CLKID_XTAL_USB_PHY 2 +#define CLKID_XTAL_USB_CTRL 3 +#define CLKID_XTAL_HIFIPLL 4 +#define CLKID_XTAL_SYSPLL 5 +#define CLKID_XTAL_DDS 6 +#define CLKID_SYS_CLK 7 +#define CLKID_CLKTREE 8 +#define CLKID_RESET_CTRL 9 +#define CLKID_ANALOG_CTRL 10 +#define CLKID_PWR_CTRL 11 +#define CLKID_PAD_CTRL 12 +#define CLKID_SYS_CTRL 13 +#define CLKID_TEMP_SENSOR 14 +#define CLKID_AM2AXI_DIV 15 +#define CLKID_SPICC_B 16 +#define CLKID_SPICC_A 17 +#define CLKID_CLK_MSR 18 +#define CLKID_AUDIO 19 +#define CLKID_JTAG_CTRL 20 +#define CLKID_SARADC 21 +#define CLKID_PWM_EF 22 +#define CLKID_PWM_CD 23 +#define CLKID_PWM_AB 24 +#define CLKID_CEC 25 +#define CLKID_I2C_S 26 +#define CLKID_IR_CTRL 27 +#define CLKID_I2C_M_D 28 +#define CLKID_I2C_M_C 29 +#define CLKID_I2C_M_B 30 +#define CLKID_I2C_M_A 31 +#define CLKID_ACODEC 32 +#define CLKID_OTP 33 +#define CLKID_SD_EMMC_A 34 +#define CLKID_USB_PHY 35 +#define CLKID_USB_CTRL 36 +#define CLKID_SYS_DSPB 37 +#define CLKID_SYS_DSPA 38 +#define CLKID_DMA 39 +#define CLKID_IRQ_CTRL 40 +#define CLKID_NIC 41 +#define CLKID_GIC 42 +#define CLKID_UART_C 43 +#define CLKID_UART_B 44 +#define CLKID_UART_A 45 +#define CLKID_SYS_PSRAM 46 +#define CLKID_RSA 47 +#define CLKID_CORESIGHT 48 +#define CLKID_AM2AXI_VAD 49 +#define CLKID_AUDIO_VAD 50 +#define CLKID_AXI_DMC 51 +#define CLKID_AXI_PSRAM 52 +#define CLKID_RAMB 53 +#define CLKID_RAMA 54 +#define CLKID_AXI_SPIFC 55 +#define CLKID_AXI_NIC 56 +#define CLKID_AXI_DMA 57 +#define CLKID_CPU_CTRL 58 +#define CLKID_ROM 59 +#define CLKID_PROC_I2C 60 +#define CLKID_DSPA_SEL 61 +#define CLKID_DSPB_SEL 62 +#define CLKID_DSPA_EN 63 +#define CLKID_DSPA_EN_NIC 64 +#define CLKID_DSPB_EN 65 +#define CLKID_DSPB_EN_NIC 66 +#define CLKID_RTC_CLK 67 +#define CLKID_CECA_32K 68 +#define CLKID_CECB_32K 69 +#define CLKID_24M 70 +#define CLKID_12M 71 +#define CLKID_FCLK_DIV2_DIVN 72 +#define CLKID_GEN 73 +#define CLKID_SARADC_SEL 74 +#define CLKID_SARADC_CLK 75 +#define CLKID_PWM_A 76 +#define CLKID_PWM_B 77 +#define CLKID_PWM_C 78 +#define CLKID_PWM_D 79 +#define CLKID_PWM_E 80 +#define CLKID_PWM_F 81 +#define CLKID_SPICC 82 +#define CLKID_TS 83 +#define CLKID_SPIFC 84 +#define CLKID_USB_BUS 85 +#define CLKID_SD_EMMC 86 +#define CLKID_PSRAM 87 +#define CLKID_DMC 88 + +#endif /* __A1_CLKC_H */ From patchwork Thu Dec 1 22:56:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Rokosov X-Patchwork-Id: 28583 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp529338wrr; Thu, 1 Dec 2022 15:01:24 -0800 (PST) X-Google-Smtp-Source: AA0mqf7U0600xoAVJfZb7R5QNwVmYZ+Airpv7JoQ69K/PcC9r1pIBgeSoAl4UcfY+fAjW/g+4Itn X-Received: by 2002:a63:1151:0:b0:438:a750:99b7 with SMTP id 17-20020a631151000000b00438a75099b7mr42067765pgr.605.1669935683418; Thu, 01 Dec 2022 15:01:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669935683; cv=none; d=google.com; s=arc-20160816; b=rw31X0tVqJS3chHeBYl2tQuBmLZBJVe64X7MPpEQaHcSxYeH1EDvscg9A2kTntKywa /K/6ItNU8IPIJwIY/tQaiM/YwY+avljCqk051TyXrtzsRkA5hROW59jB/hsYLCc3yP8F P/pU1yxnIsyGgUKh60N2eNFxDoZVZtC65l1pZD0m4EmigR1ikkK7wdXb18cMpuFH2+0k 5idtrnz9Wz2+pZJSf5HRo/q4tR/JzONPhmclYQUpvuhr/ZuhF5D7B607JgqCgTosnZHE ndF8xD6dqBLP42WM38g7/9gG5H/vD5yy6+BbyXxYj1at/YlQffjSJB0LAqUHijlGWSRl MmEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=jlFI8jiIzHvwJyrx61i0yCrtfZpp7C91e4n7Ha5ayVs=; b=Q5rad/0mHxgsV8bawooHN3CQMfRAFV0MFY3T7P+6sAP82OyiE/f7Zis6wxHPp7xzsS ocz3ASqaT0plqGQ1j9Whchwm8xZpE0BmKziqcgCv58IPX4PpwexMdEMAnjGnUHvOkUFs GzG+b5TyWYgmOduzw/xSkOELUvWSd6XFmeovfYrjspv+uK1eGFHhcbW0BnEWMpI3dd/x jeIUh0aROmZ14aofj7NMRMD8WaHzKN2XLAIFXsdB0U8q7YH6wiysGhEGQP7ZIRMEQoDF p+ZJr1PsmAghN8WTtms7T8Aem33vyqGfbU/H97oQuEsOev9E1FGebdRpdX2bFbh74Qbo PDKg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sberdevices.ru header.s=mail header.b=ek4H1UPj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=sberdevices.ru Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id h1-20020a056a00230100b0057555579113si6308295pfh.316.2022.12.01.15.01.10; Thu, 01 Dec 2022 15:01:23 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@sberdevices.ru header.s=mail header.b=ek4H1UPj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=sberdevices.ru Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231787AbiLAW6C (ORCPT + 99 others); Thu, 1 Dec 2022 17:58:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51124 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231654AbiLAW5i (ORCPT ); Thu, 1 Dec 2022 17:57:38 -0500 Received: from mx.sberdevices.ru (mx.sberdevices.ru [45.89.227.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 741F21A4; Thu, 1 Dec 2022 14:57:32 -0800 (PST) Received: from s-lin-edge02.sberdevices.ru (localhost [127.0.0.1]) by mx.sberdevices.ru (Postfix) with ESMTP id D17005FD0D; Fri, 2 Dec 2022 01:57:30 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sberdevices.ru; s=mail; t=1669935450; bh=jlFI8jiIzHvwJyrx61i0yCrtfZpp7C91e4n7Ha5ayVs=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type; b=ek4H1UPjyqSDtKiYo12/oG6XCKi2UwTYMCzT+cnnx7mLoOqxGq6yTnrfONXUEfA9G 77hzodmBnpKsExSrf5m47F1y0LVFvqSp0DSpKckaQ2BXFfbV5rqDl7wjjaFzceBsL+ c/YMXyrCCt7WaQGyGQZO8QFwz1T0SRMt0lvj7EL+3jvSXb1BwC3vGiZB89LIQIeGuJ OtFlrUcTszAWRoF3eeWDGO7kIRrERhzDLc8/w31JWNWGMFjRAlrUcmlELx8jLUytLa 1Eg4zZoHpofE35ykjqGooY9r7QO7z/KqmGn9H9zPYKJzQVz/U2bFaN2x3cDcAsR/4M GMNYYSpYnrX0A== Received: from S-MS-EXCH01.sberdevices.ru (S-MS-EXCH01.sberdevices.ru [172.16.1.4]) by mx.sberdevices.ru (Postfix) with ESMTP; Fri, 2 Dec 2022 01:57:30 +0300 (MSK) From: Dmitry Rokosov To: , , , , , , , CC: , , , , , , , , Dmitry Rokosov Subject: [PATCH v8 04/11] clk: meson: a1: add support for Amlogic A1 Peripheral clock driver Date: Fri, 2 Dec 2022 01:56:56 +0300 Message-ID: <20221201225703.6507-5-ddrokosov@sberdevices.ru> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20221201225703.6507-1-ddrokosov@sberdevices.ru> References: <20221201225703.6507-1-ddrokosov@sberdevices.ru> MIME-Version: 1.0 X-Originating-IP: [172.16.1.6] X-ClientProxiedBy: S-MS-EXCH02.sberdevices.ru (172.16.1.5) To S-MS-EXCH01.sberdevices.ru (172.16.1.4) X-KSMG-Rule-ID: 4 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Status: not scanned, disabled by settings X-KSMG-AntiSpam-Interceptor-Info: not scanned X-KSMG-AntiPhishing: not scanned, disabled by settings X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 1.1.2.30, bases: 2022/12/01 20:49:00 #20634374 X-KSMG-AntiVirus-Status: Clean, skipped X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751054479021058993?= X-GMAIL-MSGID: =?utf-8?q?1751054479021058993?= From: Jian Hu Add Amlogic Meson A1 peripheral clock driver, it depends on the A1 PLL driver. Signed-off-by: Jian Hu Signed-off-by: Dmitry Rokosov --- drivers/clk/meson/Kconfig | 9 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/a1.c | 2249 ++++++++++++++++++++++++++++++++++++ drivers/clk/meson/a1.h | 120 ++ 4 files changed, 2379 insertions(+) create mode 100644 drivers/clk/meson/a1.c create mode 100644 drivers/clk/meson/a1.h diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index ab34662b24f0..bd44ba47200e 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -108,6 +108,15 @@ config COMMON_CLK_A1_PLL Support for the PLL clock controller on Amlogic A113L device, aka a1. Say Y if you want PLL to work. +config COMMON_CLK_A1 + bool + depends on ARCH_MESON + select COMMON_CLK_MESON_DUALDIV + select COMMON_CLK_MESON_REGMAP + help + Support for the Peripheral clock controller on Amlogic A113L device, + aka a1. Say Y if you want Peripherals to work. + config COMMON_CLK_G12A tristate "G12 and SM1 SoC clock controllers support" depends on ARM64 diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 2f17f475a48f..0e6f293c05d4 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o obj-$(CONFIG_COMMON_CLK_A1_PLL) += a1-pll.o +obj-$(CONFIG_COMMON_CLK_A1) += a1.o obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o diff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c new file mode 100644 index 000000000000..2cf20ae1db75 --- /dev/null +++ b/drivers/clk/meson/a1.c @@ -0,0 +1,2249 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + * Author: Jian Hu + */ + +#include +#include +#include +#include "a1.h" +#include "clk-dualdiv.h" +#include "clk-regmap.h" + +static struct clk_regmap a1_xtal_clktree = { + .data = &(struct clk_regmap_gate_data){ + .offset = SYS_OSCIN_CTRL, + .bit_idx = 0, + }, + .hw.init = &(struct clk_init_data) { + .name = "xtal_clktree", + .ops = &clk_regmap_gate_ro_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap a1_xtal_fixpll = { + .data = &(struct clk_regmap_gate_data){ + .offset = SYS_OSCIN_CTRL, + .bit_idx = 1, + }, + .hw.init = &(struct clk_init_data) { + .name = "xtal_fixpll", + .ops = &clk_regmap_gate_ro_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap a1_xtal_usb_phy = { + .data = &(struct clk_regmap_gate_data){ + .offset = SYS_OSCIN_CTRL, + .bit_idx = 2, + }, + .hw.init = &(struct clk_init_data) { + .name = "xtal_usb_phy", + .ops = &clk_regmap_gate_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap a1_xtal_usb_ctrl = { + .data = &(struct clk_regmap_gate_data){ + .offset = SYS_OSCIN_CTRL, + .bit_idx = 3, + }, + .hw.init = &(struct clk_init_data) { + .name = "xtal_usb_ctrl", + .ops = &clk_regmap_gate_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap a1_xtal_hifipll = { + .data = &(struct clk_regmap_gate_data){ + .offset = SYS_OSCIN_CTRL, + .bit_idx = 4, + }, + .hw.init = &(struct clk_init_data) { + .name = "xtal_hifipll", + .ops = &clk_regmap_gate_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap a1_xtal_syspll = { + .data = &(struct clk_regmap_gate_data){ + .offset = SYS_OSCIN_CTRL, + .bit_idx = 5, + }, + .hw.init = &(struct clk_init_data) { + .name = "xtal_syspll", + .ops = &clk_regmap_gate_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap a1_xtal_dds = { + .data = &(struct clk_regmap_gate_data){ + .offset = SYS_OSCIN_CTRL, + .bit_idx = 6, + }, + .hw.init = &(struct clk_init_data) { + .name = "xtal_dds", + .ops = &clk_regmap_gate_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + }, + .num_parents = 1, + }, +}; + +static const struct clk_parent_data sys_clk_parents[] = { + { .fw_name = "xtal" }, + { .fw_name = "fclk_div2" }, + { .fw_name = "fclk_div3" }, + { .fw_name = "fclk_div5" }, +}; + +static struct clk_regmap a1_sys_b_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = SYS_CLK_CTRL0, + .mask = 0x7, + .shift = 26, + }, + .hw.init = &(struct clk_init_data){ + .name = "sys_b_sel", + .ops = &clk_regmap_mux_ro_ops, + .parent_data = sys_clk_parents, + .num_parents = ARRAY_SIZE(sys_clk_parents), + }, +}; + +static struct clk_regmap a1_sys_b_div = { + .data = &(struct clk_regmap_div_data){ + .offset = SYS_CLK_CTRL0, + .shift = 16, + .width = 10, + }, + .hw.init = &(struct clk_init_data){ + .name = "sys_b_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_sys_b_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_sys_b = { + .data = &(struct clk_regmap_gate_data){ + .offset = SYS_CLK_CTRL0, + .bit_idx = 29, + }, + .hw.init = &(struct clk_init_data) { + .name = "sys_b", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_sys_b_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_sys_a_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = SYS_CLK_CTRL0, + .mask = 0x7, + .shift = 10, + }, + .hw.init = &(struct clk_init_data){ + .name = "sys_a_sel", + .ops = &clk_regmap_mux_ro_ops, + .parent_data = sys_clk_parents, + .num_parents = ARRAY_SIZE(sys_clk_parents), + }, +}; + +static struct clk_regmap a1_sys_a_div = { + .data = &(struct clk_regmap_div_data){ + .offset = SYS_CLK_CTRL0, + .shift = 0, + .width = 10, + }, + .hw.init = &(struct clk_init_data){ + .name = "sys_a_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_sys_a_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_sys_a = { + .data = &(struct clk_regmap_gate_data){ + .offset = SYS_CLK_CTRL0, + .bit_idx = 13, + }, + .hw.init = &(struct clk_init_data) { + .name = "sys_a", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_sys_a_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_sys_clk = { + .data = &(struct clk_regmap_mux_data){ + .offset = SYS_CLK_CTRL0, + .mask = 0x1, + .shift = 31, + }, + .hw.init = &(struct clk_init_data){ + .name = "sys_clk", + .ops = &clk_regmap_mux_ro_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_sys_a.hw, &a1_sys_b.hw, + }, + .num_parents = 2, + /* + * This clock is used by APB bus which is set in boot ROM code + * and is required by the platform to operate correctly. + * Until the following condition are met, we need this clock to + * be marked as critical: + * a) Mark the clock used by a firmware resource, if possible + * b) CCF has a clock hand-off mechanism to make the sure the + * clock stays on until the proper driver comes along + */ + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + }, +}; + +static struct clk_regmap a1_rtc_32k_clkin = { + .data = &(struct clk_regmap_gate_data){ + .offset = RTC_BY_OSCIN_CTRL0, + .bit_idx = 31, + }, + .hw.init = &(struct clk_init_data) { + .name = "rtc_32k_clkin", + .ops = &clk_regmap_gate_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + }, + .num_parents = 1, + }, +}; + +static const struct meson_clk_dualdiv_param a1_32k_div_table[] = { + { + .dual = 1, + .n1 = 733, + .m1 = 8, + .n2 = 732, + .m2 = 11, + }, + {} +}; + +static struct clk_regmap a1_rtc_32k_div = { + .data = &(struct meson_clk_dualdiv_data){ + .n1 = { + .reg_off = RTC_BY_OSCIN_CTRL0, + .shift = 0, + .width = 12, + }, + .n2 = { + .reg_off = RTC_BY_OSCIN_CTRL0, + .shift = 12, + .width = 12, + }, + .m1 = { + .reg_off = RTC_BY_OSCIN_CTRL1, + .shift = 0, + .width = 12, + }, + .m2 = { + .reg_off = RTC_BY_OSCIN_CTRL1, + .shift = 12, + .width = 12, + }, + .dual = { + .reg_off = RTC_BY_OSCIN_CTRL0, + .shift = 28, + .width = 1, + }, + .table = a1_32k_div_table, + }, + .hw.init = &(struct clk_init_data){ + .name = "rtc_32k_div", + .ops = &meson_clk_dualdiv_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_rtc_32k_clkin.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap a1_rtc_32k_xtal = { + .data = &(struct clk_regmap_gate_data){ + .offset = RTC_BY_OSCIN_CTRL1, + .bit_idx = 24, + }, + .hw.init = &(struct clk_init_data) { + .name = "rtc_32k_xtal", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_rtc_32k_clkin.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap a1_rtc_32k_sel = { + .data = &(struct clk_regmap_mux_data) { + .offset = RTC_CTRL, + .mask = 0x3, + .shift = 0, + .flags = CLK_MUX_ROUND_CLOSEST, + }, + .hw.init = &(struct clk_init_data){ + .name = "rtc_32k_sel", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_rtc_32k_xtal.hw, + &a1_rtc_32k_div.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +struct clk_regmap a1_rtc_clk = { + .data = &(struct clk_regmap_gate_data){ + .offset = RTC_BY_OSCIN_CTRL0, + .bit_idx = 30, + }, + .hw.init = &(struct clk_init_data){ + .name = "rtc_clk", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_rtc_32k_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static u32 mux_table_dsp_ab[] = { 0, 1, 2, 3, 4, 7 }; +static const struct clk_parent_data dsp_ab_clk_parent_data[] = { + { .fw_name = "xtal", }, + { .fw_name = "fclk_div2", }, + { .fw_name = "fclk_div3", }, + { .fw_name = "fclk_div5", }, + { .fw_name = "hifi_pll", }, + { .hw = &a1_rtc_clk.hw }, +}; + +static struct clk_regmap a1_dspa_a_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = DSPA_CLK_CTRL0, + .mask = 0x7, + .shift = 10, + .table = mux_table_dsp_ab, + }, + .hw.init = &(struct clk_init_data){ + .name = "dspa_a_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = dsp_ab_clk_parent_data, + .num_parents = ARRAY_SIZE(dsp_ab_clk_parent_data), + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_dspa_a_div = { + .data = &(struct clk_regmap_div_data){ + .offset = DSPA_CLK_CTRL0, + .shift = 0, + .width = 10, + }, + .hw.init = &(struct clk_init_data){ + .name = "dspa_a_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_dspa_a_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_dspa_a = { + .data = &(struct clk_regmap_gate_data){ + .offset = DSPA_CLK_CTRL0, + .bit_idx = 13, + }, + .hw.init = &(struct clk_init_data) { + .name = "dspa_a", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_dspa_a_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_dspa_b_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = DSPA_CLK_CTRL0, + .mask = 0x7, + .shift = 26, + .table = mux_table_dsp_ab, + }, + .hw.init = &(struct clk_init_data){ + .name = "dspa_b_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = dsp_ab_clk_parent_data, + .num_parents = ARRAY_SIZE(dsp_ab_clk_parent_data), + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_dspa_b_div = { + .data = &(struct clk_regmap_div_data){ + .offset = DSPA_CLK_CTRL0, + .shift = 16, + .width = 10, + }, + .hw.init = &(struct clk_init_data){ + .name = "dspa_b_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_dspa_b_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_dspa_b = { + .data = &(struct clk_regmap_gate_data){ + .offset = DSPA_CLK_CTRL0, + .bit_idx = 29, + }, + .hw.init = &(struct clk_init_data) { + .name = "dspa_b", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_dspa_b_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_dspa_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = DSPA_CLK_CTRL0, + .mask = 0x1, + .shift = 15, + }, + .hw.init = &(struct clk_init_data){ + .name = "dspa_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = (const struct clk_parent_data []) { + { .hw = &a1_dspa_a.hw }, + { .hw = &a1_dspa_b.hw }, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_dspa_en = { + .data = &(struct clk_regmap_gate_data){ + .offset = DSPA_CLK_EN, + .bit_idx = 1, + }, + .hw.init = &(struct clk_init_data) { + .name = "dspa_en", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_dspa_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_dspa_en_nic = { + .data = &(struct clk_regmap_gate_data){ + .offset = DSPA_CLK_EN, + .bit_idx = 0, + }, + .hw.init = &(struct clk_init_data) { + .name = "dspa_en_nic", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_dspa_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_dspb_a_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = DSPB_CLK_CTRL0, + .mask = 0x7, + .shift = 10, + .table = mux_table_dsp_ab, + }, + .hw.init = &(struct clk_init_data){ + .name = "dspb_a_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = dsp_ab_clk_parent_data, + .num_parents = ARRAY_SIZE(dsp_ab_clk_parent_data), + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_dspb_a_div = { + .data = &(struct clk_regmap_div_data){ + .offset = DSPB_CLK_CTRL0, + .shift = 0, + .width = 10, + }, + .hw.init = &(struct clk_init_data){ + .name = "dspb_a_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_dspb_a_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_dspb_a = { + .data = &(struct clk_regmap_gate_data){ + .offset = DSPB_CLK_CTRL0, + .bit_idx = 13, + }, + .hw.init = &(struct clk_init_data) { + .name = "dspb_a", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_dspb_a_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + }, +}; + +static struct clk_regmap a1_dspb_b_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = DSPB_CLK_CTRL0, + .mask = 0x7, + .shift = 26, + .table = mux_table_dsp_ab, + }, + .hw.init = &(struct clk_init_data){ + .name = "dspb_b_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = dsp_ab_clk_parent_data, + .num_parents = ARRAY_SIZE(dsp_ab_clk_parent_data), + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_dspb_b_div = { + .data = &(struct clk_regmap_div_data){ + .offset = DSPB_CLK_CTRL0, + .shift = 16, + .width = 10, + }, + .hw.init = &(struct clk_init_data){ + .name = "dspb_b_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_dspb_b_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_dspb_b = { + .data = &(struct clk_regmap_gate_data){ + .offset = DSPB_CLK_CTRL0, + .bit_idx = 29, + }, + .hw.init = &(struct clk_init_data) { + .name = "dspb_b", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_dspb_b_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + }, +}; + +static struct clk_regmap a1_dspb_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = DSPB_CLK_CTRL0, + .mask = 0x1, + .shift = 15, + }, + .hw.init = &(struct clk_init_data){ + .name = "dspb_sel", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_dspb_a.hw, &a1_dspb_b.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_dspb_en = { + .data = &(struct clk_regmap_gate_data){ + .offset = DSPB_CLK_EN, + .bit_idx = 1, + }, + .hw.init = &(struct clk_init_data) { + .name = "dspb_en", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_dspb_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + }, +}; + +static struct clk_regmap a1_dspb_en_nic = { + .data = &(struct clk_regmap_gate_data){ + .offset = DSPB_CLK_EN, + .bit_idx = 0, + }, + .hw.init = &(struct clk_init_data) { + .name = "dspb_en_nic", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_dspb_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + }, +}; + +static struct clk_regmap a1_24m = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLK12_24_CTRL, + .bit_idx = 11, + }, + .hw.init = &(struct clk_init_data) { + .name = "24m", + .ops = &clk_regmap_gate_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor a1_24m_div2 = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "24m_div2", + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_24m.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap a1_12m = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLK12_24_CTRL, + .bit_idx = 10, + }, + .hw.init = &(struct clk_init_data) { + .name = "12m", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_24m_div2.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap a1_fclk_div2_divn_pre = { + .data = &(struct clk_regmap_div_data){ + .offset = CLK12_24_CTRL, + .shift = 0, + .width = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div2_divn_pre", + .ops = &clk_regmap_divider_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "fclk_div2", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap a1_fclk_div2_divn = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLK12_24_CTRL, + .bit_idx = 12, + }, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div2_divn", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_fclk_div2_divn_pre.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +/* + * the index 2 is sys_pll_div16, it will complete in the CPU clock, + * the index 4 is the clock measurement source, it relies on + * the clock measurement register configuration. + */ +static u32 gen_clk_table[] = { 0, 1, 3, 5, 6, 7, 8 }; +static const struct clk_parent_data gen_clk_parent_data[] = { + { .fw_name = "xtal", }, + { .hw = &a1_rtc_clk.hw }, + { .fw_name = "hifi_pll", }, + { .fw_name = "fclk_div2", }, + { .fw_name = "fclk_div3", }, + { .fw_name = "fclk_div5", }, + { .fw_name = "fclk_div7", }, +}; + +static struct clk_regmap a1_gen_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = GEN_CLK_CTRL, + .mask = 0xf, + .shift = 12, + .table = gen_clk_table, + }, + .hw.init = &(struct clk_init_data){ + .name = "gen_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = gen_clk_parent_data, + .num_parents = ARRAY_SIZE(gen_clk_parent_data), + }, +}; + +static struct clk_regmap a1_gen_div = { + .data = &(struct clk_regmap_div_data){ + .offset = GEN_CLK_CTRL, + .shift = 0, + .width = 11, + }, + .hw.init = &(struct clk_init_data){ + .name = "gen_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_gen_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_gen = { + .data = &(struct clk_regmap_gate_data){ + .offset = GEN_CLK_CTRL, + .bit_idx = 11, + }, + .hw.init = &(struct clk_init_data) { + .name = "gen", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_gen_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_saradc_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = SAR_ADC_CLK_CTRL, + .mask = 0x1, + .shift = 9, + }, + .hw.init = &(struct clk_init_data){ + .name = "saradc_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = (const struct clk_parent_data []) { + { .fw_name = "xtal", }, + { .hw = &a1_sys_clk.hw, }, + }, + .num_parents = 2, + }, +}; + +static struct clk_regmap a1_saradc_div = { + .data = &(struct clk_regmap_div_data){ + .offset = SAR_ADC_CLK_CTRL, + .shift = 0, + .width = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "saradc_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_saradc_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_saradc_clk = { + .data = &(struct clk_regmap_gate_data){ + .offset = SAR_ADC_CLK_CTRL, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data) { + .name = "saradc_clk", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_saradc_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_pwm_a_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = PWM_CLK_AB_CTRL, + .mask = 0x1, + .shift = 9, + }, + .hw.init = &(struct clk_init_data){ + .name = "pwm_a_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = (const struct clk_parent_data []) { + { .fw_name = "xtal", }, + { .hw = &a1_sys_clk.hw, }, + }, + .num_parents = 2, + }, +}; + +static struct clk_regmap a1_pwm_a_div = { + .data = &(struct clk_regmap_div_data){ + .offset = PWM_CLK_AB_CTRL, + .shift = 0, + .width = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "pwm_a_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_pwm_a_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_pwm_a = { + .data = &(struct clk_regmap_gate_data){ + .offset = PWM_CLK_AB_CTRL, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data) { + .name = "pwm_a", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_pwm_a_div.hw + }, + .num_parents = 1, + /* + * The CPU working voltage is controlled by pwm_a + * in BL2 firmware. The clock is required by the platform + * to operate correctly. Add the CLK_IS_CRITICAL flag to + * avoid changing at runtime. + * About critical, refer to a1_sys_clk + */ + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + }, +}; + +static struct clk_regmap a1_pwm_b_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = PWM_CLK_AB_CTRL, + .mask = 0x1, + .shift = 25, + }, + .hw.init = &(struct clk_init_data){ + .name = "pwm_b_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = (const struct clk_parent_data []) { + { .fw_name = "xtal", }, + { .hw = &a1_sys_clk.hw, }, + }, + .num_parents = 2, + }, +}; + +static struct clk_regmap a1_pwm_b_div = { + .data = &(struct clk_regmap_div_data){ + .offset = PWM_CLK_AB_CTRL, + .shift = 16, + .width = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "pwm_b_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_pwm_b_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_pwm_b = { + .data = &(struct clk_regmap_gate_data){ + .offset = PWM_CLK_AB_CTRL, + .bit_idx = 24, + }, + .hw.init = &(struct clk_init_data) { + .name = "pwm_b", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_pwm_b_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_pwm_c_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = PWM_CLK_CD_CTRL, + .mask = 0x1, + .shift = 9, + }, + .hw.init = &(struct clk_init_data){ + .name = "pwm_c_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = (const struct clk_parent_data []) { + { .fw_name = "xtal", }, + { .hw = &a1_sys_clk.hw, }, + }, + .num_parents = 2, + }, +}; + +static struct clk_regmap a1_pwm_c_div = { + .data = &(struct clk_regmap_div_data){ + .offset = PWM_CLK_CD_CTRL, + .shift = 0, + .width = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "pwm_c_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_pwm_c_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_pwm_c = { + .data = &(struct clk_regmap_gate_data){ + .offset = PWM_CLK_CD_CTRL, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data) { + .name = "pwm_c", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_pwm_c_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_pwm_d_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = PWM_CLK_CD_CTRL, + .mask = 0x1, + .shift = 25, + }, + .hw.init = &(struct clk_init_data){ + .name = "pwm_d_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = (const struct clk_parent_data []) { + { .fw_name = "xtal", }, + { .hw = &a1_sys_clk.hw, }, + }, + .num_parents = 2, + }, +}; + +static struct clk_regmap a1_pwm_d_div = { + .data = &(struct clk_regmap_div_data){ + .offset = PWM_CLK_CD_CTRL, + .shift = 16, + .width = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "pwm_d_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_pwm_d_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_pwm_d = { + .data = &(struct clk_regmap_gate_data){ + .offset = PWM_CLK_CD_CTRL, + .bit_idx = 24, + }, + .hw.init = &(struct clk_init_data) { + .name = "pwm_d", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_pwm_d_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data pwm_ef_parent_data[] = { + { .fw_name = "xtal", }, + { .hw = &a1_sys_clk.hw }, + { .fw_name = "fclk_div5", }, + { .hw = &a1_rtc_clk.hw }, +}; + +static struct clk_regmap a1_pwm_e_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = PWM_CLK_EF_CTRL, + .mask = 0x3, + .shift = 9, + }, + .hw.init = &(struct clk_init_data){ + .name = "pwm_e_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = pwm_ef_parent_data, + .num_parents = ARRAY_SIZE(pwm_ef_parent_data), + }, +}; + +static struct clk_regmap a1_pwm_e_div = { + .data = &(struct clk_regmap_div_data){ + .offset = PWM_CLK_EF_CTRL, + .shift = 0, + .width = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "pwm_e_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_pwm_e_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_pwm_e = { + .data = &(struct clk_regmap_gate_data){ + .offset = PWM_CLK_EF_CTRL, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data) { + .name = "pwm_e", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_pwm_e_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_pwm_f_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = PWM_CLK_EF_CTRL, + .mask = 0x3, + .shift = 25, + }, + .hw.init = &(struct clk_init_data){ + .name = "pwm_f_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = pwm_ef_parent_data, + .num_parents = ARRAY_SIZE(pwm_ef_parent_data), + }, +}; + +static struct clk_regmap a1_pwm_f_div = { + .data = &(struct clk_regmap_div_data){ + .offset = PWM_CLK_EF_CTRL, + .shift = 16, + .width = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "pwm_f_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_pwm_f_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_pwm_f = { + .data = &(struct clk_regmap_gate_data){ + .offset = PWM_CLK_EF_CTRL, + .bit_idx = 24, + }, + .hw.init = &(struct clk_init_data) { + .name = "pwm_f", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_pwm_f_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +/* + * spicc clk + * fdiv2 |\ |\ _____ + * ---------| |---DIV--| | | | spicc out + * ---------| | | |-----|GATE |--------- + * ..... |/ | / |_____| + * --------------------|/ + * 24M + */ +static const struct clk_parent_data spicc_parents[] = { + { .fw_name = "fclk_div2"}, + { .fw_name = "fclk_div3"}, + { .fw_name = "fclk_div5"}, + { .fw_name = "hifi_pll" }, +}; + +static struct clk_regmap a1_spicc_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = SPICC_CLK_CTRL, + .mask = 0x3, + .shift = 9, + }, + .hw.init = &(struct clk_init_data){ + .name = "spicc_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = spicc_parents, + .num_parents = 4, + }, +}; + +static struct clk_regmap a1_spicc_div = { + .data = &(struct clk_regmap_div_data){ + .offset = SPICC_CLK_CTRL, + .shift = 0, + .width = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "spicc_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_spicc_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_spicc_sel2 = { + .data = &(struct clk_regmap_mux_data){ + .offset = SPICC_CLK_CTRL, + .mask = 0x1, + .shift = 15, + }, + .hw.init = &(struct clk_init_data){ + .name = "spicc_sel2", + .ops = &clk_regmap_mux_ops, + .parent_data = (const struct clk_parent_data []) { + { .hw = &a1_spicc_div.hw }, + { .fw_name = "xtal", }, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_spicc = { + .data = &(struct clk_regmap_gate_data){ + .offset = SPICC_CLK_CTRL, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data) { + .name = "spicc", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_spicc_sel2.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_ts_div = { + .data = &(struct clk_regmap_div_data){ + .offset = TS_CLK_CTRL, + .shift = 0, + .width = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "ts_div", + .ops = &clk_regmap_divider_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap a1_ts = { + .data = &(struct clk_regmap_gate_data){ + .offset = TS_CLK_CTRL, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data) { + .name = "ts", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_ts_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_spifc_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = SPIFC_CLK_CTRL, + .mask = 0x3, + .shift = 9, + }, + .hw.init = &(struct clk_init_data){ + .name = "spifc_sel", + .ops = &clk_regmap_mux_ops, + /* the same parent with spicc */ + .parent_data = spicc_parents, + .num_parents = 4, + }, +}; + +static struct clk_regmap a1_spifc_div = { + .data = &(struct clk_regmap_div_data){ + .offset = SPIFC_CLK_CTRL, + .shift = 0, + .width = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "spifc_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_spifc_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_spifc_sel2 = { + .data = &(struct clk_regmap_mux_data){ + .offset = SPIFC_CLK_CTRL, + .mask = 0x1, + .shift = 15, + }, + .hw.init = &(struct clk_init_data){ + .name = "spifc_sel2", + .ops = &clk_regmap_mux_ops, + .parent_data = (const struct clk_parent_data []) { + { .hw = &a1_spifc_div.hw }, + { .fw_name = "xtal", }, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_spifc = { + .data = &(struct clk_regmap_gate_data){ + .offset = SPIFC_CLK_CTRL, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data) { + .name = "spifc", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_spifc_sel2.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data usb_bus_parent_data[] = { + { .fw_name = "xtal", }, + { .hw = &a1_sys_clk.hw }, + { .fw_name = "fclk_div3", }, + { .fw_name = "fclk_div5", }, +}; + +static struct clk_regmap a1_usb_bus_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = USB_BUSCLK_CTRL, + .mask = 0x3, + .shift = 9, + }, + .hw.init = &(struct clk_init_data){ + .name = "usb_bus_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = usb_bus_parent_data, + .num_parents = ARRAY_SIZE(usb_bus_parent_data), + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_usb_bus_div = { + .data = &(struct clk_regmap_div_data){ + .offset = USB_BUSCLK_CTRL, + .shift = 0, + .width = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "usb_bus_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_usb_bus_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_usb_bus = { + .data = &(struct clk_regmap_gate_data){ + .offset = USB_BUSCLK_CTRL, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data) { + .name = "usb_bus", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_usb_bus_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data sd_emmc_parents[] = { + { .fw_name = "fclk_div2", }, + { .fw_name = "fclk_div3", }, + { .fw_name = "fclk_div5", }, + { .fw_name = "hifi_pll", }, +}; + +static struct clk_regmap a1_sd_emmc_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = SD_EMMC_CLK_CTRL, + .mask = 0x3, + .shift = 9, + }, + .hw.init = &(struct clk_init_data){ + .name = "sd_emmc_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = sd_emmc_parents, + .num_parents = 4, + }, +}; + +static struct clk_regmap a1_sd_emmc_div = { + .data = &(struct clk_regmap_div_data){ + .offset = SD_EMMC_CLK_CTRL, + .shift = 0, + .width = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "sd_emmc_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_sd_emmc_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_sd_emmc_sel2 = { + .data = &(struct clk_regmap_mux_data){ + .offset = SD_EMMC_CLK_CTRL, + .mask = 0x1, + .shift = 15, + }, + .hw.init = &(struct clk_init_data){ + .name = "sd_emmc_sel2", + .ops = &clk_regmap_mux_ops, + .parent_data = (const struct clk_parent_data []) { + { .hw = &a1_sd_emmc_div.hw }, + { .fw_name = "xtal", }, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_sd_emmc = { + .data = &(struct clk_regmap_gate_data){ + .offset = SD_EMMC_CLK_CTRL, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data) { + .name = "sd_emmc", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_sd_emmc_sel2.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_psram_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = PSRAM_CLK_CTRL, + .mask = 0x3, + .shift = 9, + }, + .hw.init = &(struct clk_init_data){ + .name = "psram_sel", + .ops = &clk_regmap_mux_ops, + /* the same parent with sd_emmc */ + .parent_data = sd_emmc_parents, + .num_parents = 4, + }, +}; + +static struct clk_regmap a1_psram_div = { + .data = &(struct clk_regmap_div_data){ + .offset = PSRAM_CLK_CTRL, + .shift = 0, + .width = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "psram_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_psram_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_psram_sel2 = { + .data = &(struct clk_regmap_mux_data){ + .offset = PSRAM_CLK_CTRL, + .mask = 0x1, + .shift = 15, + }, + .hw.init = &(struct clk_init_data){ + .name = "psram_sel2", + .ops = &clk_regmap_mux_ops, + .parent_data = (const struct clk_parent_data []) { + { .hw = &a1_psram_div.hw }, + { .fw_name = "xtal", }, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_psram = { + .data = &(struct clk_regmap_gate_data){ + .offset = PSRAM_CLK_CTRL, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data) { + .name = "psram", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_psram_sel2.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_dmc_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = DMC_CLK_CTRL, + .mask = 0x3, + .shift = 9, + }, + .hw.init = &(struct clk_init_data){ + .name = "dmc_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = sd_emmc_parents, + .num_parents = 4, + }, +}; + +static struct clk_regmap a1_dmc_div = { + .data = &(struct clk_regmap_div_data){ + .offset = DMC_CLK_CTRL, + .shift = 0, + .width = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "dmc_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_dmc_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_dmc_sel2 = { + .data = &(struct clk_regmap_mux_data){ + .offset = DMC_CLK_CTRL, + .mask = 0x1, + .shift = 15, + }, + .hw.init = &(struct clk_init_data){ + .name = "dmc_sel2", + .ops = &clk_regmap_mux_ops, + .parent_data = (const struct clk_parent_data []) { + { .hw = &a1_dmc_div.hw }, + { .fw_name = "xtal", }, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_dmc = { + .data = &(struct clk_regmap_gate_data){ + .offset = DMC_CLK_CTRL, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data) { + .name = "dmc", + .ops = &clk_regmap_gate_ro_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_dmc_sel2.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_ceca_32k_clkin = { + .data = &(struct clk_regmap_gate_data){ + .offset = CECA_CLK_CTRL0, + .bit_idx = 31, + }, + .hw.init = &(struct clk_init_data) { + .name = "ceca_32k_clkin", + .ops = &clk_regmap_gate_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap a1_ceca_32k_div = { + .data = &(struct meson_clk_dualdiv_data){ + .n1 = { + .reg_off = CECA_CLK_CTRL0, + .shift = 0, + .width = 12, + }, + .n2 = { + .reg_off = CECA_CLK_CTRL0, + .shift = 12, + .width = 12, + }, + .m1 = { + .reg_off = CECA_CLK_CTRL1, + .shift = 0, + .width = 12, + }, + .m2 = { + .reg_off = CECA_CLK_CTRL1, + .shift = 12, + .width = 12, + }, + .dual = { + .reg_off = CECA_CLK_CTRL0, + .shift = 28, + .width = 1, + }, + .table = a1_32k_div_table, + }, + .hw.init = &(struct clk_init_data){ + .name = "ceca_32k_div", + .ops = &meson_clk_dualdiv_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_ceca_32k_clkin.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap a1_ceca_32k_sel_pre = { + .data = &(struct clk_regmap_mux_data) { + .offset = CECA_CLK_CTRL1, + .mask = 0x1, + .shift = 24, + .flags = CLK_MUX_ROUND_CLOSEST, + }, + .hw.init = &(struct clk_init_data){ + .name = "ceca_32k_sel_pre", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_ceca_32k_div.hw, + &a1_ceca_32k_clkin.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_ceca_32k_sel = { + .data = &(struct clk_regmap_mux_data) { + .offset = CECA_CLK_CTRL1, + .mask = 0x1, + .shift = 31, + .flags = CLK_MUX_ROUND_CLOSEST, + }, + .hw.init = &(struct clk_init_data){ + .name = "ceca_32k_sel", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_ceca_32k_sel_pre.hw, + &a1_rtc_clk.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_ceca_32k_clkout = { + .data = &(struct clk_regmap_gate_data){ + .offset = CECA_CLK_CTRL0, + .bit_idx = 30, + }, + .hw.init = &(struct clk_init_data){ + .name = "ceca_32k_clkout", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_ceca_32k_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_cecb_32k_clkin = { + .data = &(struct clk_regmap_gate_data){ + .offset = CECB_CLK_CTRL0, + .bit_idx = 31, + }, + .hw.init = &(struct clk_init_data) { + .name = "cecb_32k_clkin", + .ops = &clk_regmap_gate_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap a1_cecb_32k_div = { + .data = &(struct meson_clk_dualdiv_data){ + .n1 = { + .reg_off = CECB_CLK_CTRL0, + .shift = 0, + .width = 12, + }, + .n2 = { + .reg_off = CECB_CLK_CTRL0, + .shift = 12, + .width = 12, + }, + .m1 = { + .reg_off = CECB_CLK_CTRL1, + .shift = 0, + .width = 12, + }, + .m2 = { + .reg_off = CECB_CLK_CTRL1, + .shift = 12, + .width = 12, + }, + .dual = { + .reg_off = CECB_CLK_CTRL0, + .shift = 28, + .width = 1, + }, + .table = a1_32k_div_table, + }, + .hw.init = &(struct clk_init_data){ + .name = "cecb_32k_div", + .ops = &meson_clk_dualdiv_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_cecb_32k_clkin.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap a1_cecb_32k_sel_pre = { + .data = &(struct clk_regmap_mux_data) { + .offset = CECB_CLK_CTRL1, + .mask = 0x1, + .shift = 24, + .flags = CLK_MUX_ROUND_CLOSEST, + }, + .hw.init = &(struct clk_init_data){ + .name = "cecb_32k_sel_pre", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_cecb_32k_div.hw, + &a1_cecb_32k_clkin.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_cecb_32k_sel = { + .data = &(struct clk_regmap_mux_data) { + .offset = CECB_CLK_CTRL1, + .mask = 0x1, + .shift = 31, + .flags = CLK_MUX_ROUND_CLOSEST, + }, + .hw.init = &(struct clk_init_data){ + .name = "cecb_32k_sel", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_cecb_32k_sel_pre.hw, + &a1_rtc_clk.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap a1_cecb_32k_clkout = { + .data = &(struct clk_regmap_gate_data){ + .offset = CECB_CLK_CTRL0, + .bit_idx = 30, + }, + .hw.init = &(struct clk_init_data){ + .name = "cecb_32k_clkout", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_cecb_32k_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +#define MESON_GATE(_name, _reg, _bit) \ + MESON_PCLK(_name, _reg, _bit, &a1_sys_clk.hw) + +static MESON_GATE(a1_clk_tree, SYS_CLK_EN0, 0); +static MESON_GATE(a1_reset_ctrl, SYS_CLK_EN0, 1); +static MESON_GATE(a1_analog_ctrl, SYS_CLK_EN0, 2); +static MESON_GATE(a1_pwr_ctrl, SYS_CLK_EN0, 3); +static MESON_GATE(a1_pad_ctrl, SYS_CLK_EN0, 4); +static MESON_GATE(a1_sys_ctrl, SYS_CLK_EN0, 5); +static MESON_GATE(a1_temp_sensor, SYS_CLK_EN0, 6); +static MESON_GATE(a1_am2axi_dev, SYS_CLK_EN0, 7); +static MESON_GATE(a1_spicc_b, SYS_CLK_EN0, 8); +static MESON_GATE(a1_spicc_a, SYS_CLK_EN0, 9); +static MESON_GATE(a1_clk_msr, SYS_CLK_EN0, 10); +static MESON_GATE(a1_audio, SYS_CLK_EN0, 11); +static MESON_GATE(a1_jtag_ctrl, SYS_CLK_EN0, 12); +static MESON_GATE(a1_saradc, SYS_CLK_EN0, 13); +static MESON_GATE(a1_pwm_ef, SYS_CLK_EN0, 14); +static MESON_GATE(a1_pwm_cd, SYS_CLK_EN0, 15); +static MESON_GATE(a1_pwm_ab, SYS_CLK_EN0, 16); +static MESON_GATE(a1_cec, SYS_CLK_EN0, 17); +static MESON_GATE(a1_i2c_s, SYS_CLK_EN0, 18); +static MESON_GATE(a1_ir_ctrl, SYS_CLK_EN0, 19); +static MESON_GATE(a1_i2c_m_d, SYS_CLK_EN0, 20); +static MESON_GATE(a1_i2c_m_c, SYS_CLK_EN0, 21); +static MESON_GATE(a1_i2c_m_b, SYS_CLK_EN0, 22); +static MESON_GATE(a1_i2c_m_a, SYS_CLK_EN0, 23); +static MESON_GATE(a1_acodec, SYS_CLK_EN0, 24); +static MESON_GATE(a1_otp, SYS_CLK_EN0, 25); +static MESON_GATE(a1_sd_emmc_a, SYS_CLK_EN0, 26); +static MESON_GATE(a1_usb_phy, SYS_CLK_EN0, 27); +static MESON_GATE(a1_usb_ctrl, SYS_CLK_EN0, 28); +static MESON_GATE(a1_sys_dspb, SYS_CLK_EN0, 29); +static MESON_GATE(a1_sys_dspa, SYS_CLK_EN0, 30); +static MESON_GATE(a1_dma, SYS_CLK_EN0, 31); +static MESON_GATE(a1_irq_ctrl, SYS_CLK_EN1, 0); +static MESON_GATE(a1_nic, SYS_CLK_EN1, 1); +static MESON_GATE(a1_gic, SYS_CLK_EN1, 2); +static MESON_GATE(a1_uart_c, SYS_CLK_EN1, 3); +static MESON_GATE(a1_uart_b, SYS_CLK_EN1, 4); +static MESON_GATE(a1_uart_a, SYS_CLK_EN1, 5); +static MESON_GATE(a1_sys_psram, SYS_CLK_EN1, 6); +static MESON_GATE(a1_rsa, SYS_CLK_EN1, 8); +static MESON_GATE(a1_coresight, SYS_CLK_EN1, 9); +static MESON_GATE(a1_am2axi_vad, AXI_CLK_EN, 0); +static MESON_GATE(a1_audio_vad, AXI_CLK_EN, 1); +static MESON_GATE(a1_axi_dmc, AXI_CLK_EN, 3); +static MESON_GATE(a1_axi_psram, AXI_CLK_EN, 4); +static MESON_GATE(a1_ramb, AXI_CLK_EN, 5); +static MESON_GATE(a1_rama, AXI_CLK_EN, 6); +static MESON_GATE(a1_axi_spifc, AXI_CLK_EN, 7); +static MESON_GATE(a1_axi_nic, AXI_CLK_EN, 8); +static MESON_GATE(a1_axi_dma, AXI_CLK_EN, 9); +static MESON_GATE(a1_cpu_ctrl, AXI_CLK_EN, 10); +static MESON_GATE(a1_rom, AXI_CLK_EN, 11); +static MESON_GATE(a1_prod_i2c, AXI_CLK_EN, 12); + +/* Array of all clocks provided by this provider */ +static struct clk_hw_onecell_data a1_periphs_hw_onecell_data = { + .hws = { + [CLKID_SYS_B_SEL] = &a1_sys_b_sel.hw, + [CLKID_SYS_B_DIV] = &a1_sys_b_div.hw, + [CLKID_SYS_B] = &a1_sys_b.hw, + [CLKID_SYS_A_SEL] = &a1_sys_a_sel.hw, + [CLKID_SYS_A_DIV] = &a1_sys_a_div.hw, + [CLKID_SYS_A] = &a1_sys_a.hw, + [CLKID_SYS_CLK] = &a1_sys_clk.hw, + [CLKID_XTAL_CLKTREE] = &a1_xtal_clktree.hw, + [CLKID_XTAL_FIXPLL] = &a1_xtal_fixpll.hw, + [CLKID_XTAL_USB_PHY] = &a1_xtal_usb_phy.hw, + [CLKID_XTAL_USB_CTRL] = &a1_xtal_usb_ctrl.hw, + [CLKID_XTAL_HIFIPLL] = &a1_xtal_hifipll.hw, + [CLKID_XTAL_SYSPLL] = &a1_xtal_syspll.hw, + [CLKID_XTAL_DDS] = &a1_xtal_dds.hw, + [CLKID_CLKTREE] = &a1_clk_tree.hw, + [CLKID_RESET_CTRL] = &a1_reset_ctrl.hw, + [CLKID_ANALOG_CTRL] = &a1_analog_ctrl.hw, + [CLKID_PWR_CTRL] = &a1_pwr_ctrl.hw, + [CLKID_PAD_CTRL] = &a1_pad_ctrl.hw, + [CLKID_SYS_CTRL] = &a1_sys_ctrl.hw, + [CLKID_TEMP_SENSOR] = &a1_temp_sensor.hw, + [CLKID_AM2AXI_DIV] = &a1_am2axi_dev.hw, + [CLKID_SPICC_B] = &a1_spicc_b.hw, + [CLKID_SPICC_A] = &a1_spicc_a.hw, + [CLKID_CLK_MSR] = &a1_clk_msr.hw, + [CLKID_AUDIO] = &a1_audio.hw, + [CLKID_JTAG_CTRL] = &a1_jtag_ctrl.hw, + [CLKID_SARADC] = &a1_saradc.hw, + [CLKID_PWM_EF] = &a1_pwm_ef.hw, + [CLKID_PWM_CD] = &a1_pwm_cd.hw, + [CLKID_PWM_AB] = &a1_pwm_ab.hw, + [CLKID_CEC] = &a1_cec.hw, + [CLKID_I2C_S] = &a1_i2c_s.hw, + [CLKID_IR_CTRL] = &a1_ir_ctrl.hw, + [CLKID_I2C_M_D] = &a1_i2c_m_d.hw, + [CLKID_I2C_M_C] = &a1_i2c_m_c.hw, + [CLKID_I2C_M_B] = &a1_i2c_m_b.hw, + [CLKID_I2C_M_A] = &a1_i2c_m_a.hw, + [CLKID_ACODEC] = &a1_acodec.hw, + [CLKID_OTP] = &a1_otp.hw, + [CLKID_SD_EMMC_A] = &a1_sd_emmc_a.hw, + [CLKID_USB_PHY] = &a1_usb_phy.hw, + [CLKID_USB_CTRL] = &a1_usb_ctrl.hw, + [CLKID_SYS_DSPB] = &a1_sys_dspb.hw, + [CLKID_SYS_DSPA] = &a1_sys_dspa.hw, + [CLKID_DMA] = &a1_dma.hw, + [CLKID_IRQ_CTRL] = &a1_irq_ctrl.hw, + [CLKID_NIC] = &a1_nic.hw, + [CLKID_GIC] = &a1_gic.hw, + [CLKID_UART_C] = &a1_uart_c.hw, + [CLKID_UART_B] = &a1_uart_b.hw, + [CLKID_UART_A] = &a1_uart_a.hw, + [CLKID_SYS_PSRAM] = &a1_sys_psram.hw, + [CLKID_RSA] = &a1_rsa.hw, + [CLKID_CORESIGHT] = &a1_coresight.hw, + [CLKID_AM2AXI_VAD] = &a1_am2axi_vad.hw, + [CLKID_AUDIO_VAD] = &a1_audio_vad.hw, + [CLKID_AXI_DMC] = &a1_axi_dmc.hw, + [CLKID_AXI_PSRAM] = &a1_axi_psram.hw, + [CLKID_RAMB] = &a1_ramb.hw, + [CLKID_RAMA] = &a1_rama.hw, + [CLKID_AXI_SPIFC] = &a1_axi_spifc.hw, + [CLKID_AXI_NIC] = &a1_axi_nic.hw, + [CLKID_AXI_DMA] = &a1_axi_dma.hw, + [CLKID_CPU_CTRL] = &a1_cpu_ctrl.hw, + [CLKID_ROM] = &a1_rom.hw, + [CLKID_PROC_I2C] = &a1_prod_i2c.hw, + [CLKID_DSPA_A_SEL] = &a1_dspa_a_sel.hw, + [CLKID_DSPA_A_DIV] = &a1_dspa_a_div.hw, + [CLKID_DSPA_A] = &a1_dspa_a.hw, + [CLKID_DSPA_B_SEL] = &a1_dspa_b_sel.hw, + [CLKID_DSPA_B_DIV] = &a1_dspa_b_div.hw, + [CLKID_DSPA_B] = &a1_dspa_b.hw, + [CLKID_DSPA_SEL] = &a1_dspa_sel.hw, + [CLKID_DSPB_A_SEL] = &a1_dspb_a_sel.hw, + [CLKID_DSPB_A_DIV] = &a1_dspb_a_div.hw, + [CLKID_DSPB_A] = &a1_dspb_a.hw, + [CLKID_DSPB_B_SEL] = &a1_dspb_b_sel.hw, + [CLKID_DSPB_B_DIV] = &a1_dspb_b_div.hw, + [CLKID_DSPB_B] = &a1_dspb_b.hw, + [CLKID_DSPB_SEL] = &a1_dspb_sel.hw, + [CLKID_DSPA_EN] = &a1_dspa_en.hw, + [CLKID_DSPA_EN_NIC] = &a1_dspa_en_nic.hw, + [CLKID_DSPB_EN] = &a1_dspb_en.hw, + [CLKID_DSPB_EN_NIC] = &a1_dspb_en_nic.hw, + [CLKID_24M] = &a1_24m.hw, + [CLKID_24M_DIV2] = &a1_24m_div2.hw, + [CLKID_12M] = &a1_12m.hw, + [CLKID_DIV2_PRE] = &a1_fclk_div2_divn_pre.hw, + [CLKID_FCLK_DIV2_DIVN] = &a1_fclk_div2_divn.hw, + [CLKID_GEN_SEL] = &a1_gen_sel.hw, + [CLKID_GEN_DIV] = &a1_gen_div.hw, + [CLKID_GEN] = &a1_gen.hw, + [CLKID_SARADC_SEL] = &a1_saradc_sel.hw, + [CLKID_SARADC_DIV] = &a1_saradc_div.hw, + [CLKID_SARADC_CLK] = &a1_saradc_clk.hw, + [CLKID_PWM_A_SEL] = &a1_pwm_a_sel.hw, + [CLKID_PWM_A_DIV] = &a1_pwm_a_div.hw, + [CLKID_PWM_A] = &a1_pwm_a.hw, + [CLKID_PWM_B_SEL] = &a1_pwm_b_sel.hw, + [CLKID_PWM_B_DIV] = &a1_pwm_b_div.hw, + [CLKID_PWM_B] = &a1_pwm_b.hw, + [CLKID_PWM_C_SEL] = &a1_pwm_c_sel.hw, + [CLKID_PWM_C_DIV] = &a1_pwm_c_div.hw, + [CLKID_PWM_C] = &a1_pwm_c.hw, + [CLKID_PWM_D_SEL] = &a1_pwm_d_sel.hw, + [CLKID_PWM_D_DIV] = &a1_pwm_d_div.hw, + [CLKID_PWM_D] = &a1_pwm_d.hw, + [CLKID_PWM_E_SEL] = &a1_pwm_e_sel.hw, + [CLKID_PWM_E_DIV] = &a1_pwm_e_div.hw, + [CLKID_PWM_E] = &a1_pwm_e.hw, + [CLKID_PWM_F_SEL] = &a1_pwm_f_sel.hw, + [CLKID_PWM_F_DIV] = &a1_pwm_f_div.hw, + [CLKID_PWM_F] = &a1_pwm_f.hw, + [CLKID_SPICC_SEL] = &a1_spicc_sel.hw, + [CLKID_SPICC_DIV] = &a1_spicc_div.hw, + [CLKID_SPICC_SEL2] = &a1_spicc_sel2.hw, + [CLKID_SPICC] = &a1_spicc.hw, + [CLKID_TS_DIV] = &a1_ts_div.hw, + [CLKID_TS] = &a1_ts.hw, + [CLKID_SPIFC_SEL] = &a1_spifc_sel.hw, + [CLKID_SPIFC_DIV] = &a1_spifc_div.hw, + [CLKID_SPIFC_SEL2] = &a1_spifc_sel2.hw, + [CLKID_SPIFC] = &a1_spifc.hw, + [CLKID_USB_BUS_SEL] = &a1_usb_bus_sel.hw, + [CLKID_USB_BUS_DIV] = &a1_usb_bus_div.hw, + [CLKID_USB_BUS] = &a1_usb_bus.hw, + [CLKID_SD_EMMC_SEL] = &a1_sd_emmc_sel.hw, + [CLKID_SD_EMMC_DIV] = &a1_sd_emmc_div.hw, + [CLKID_SD_EMMC_SEL2] = &a1_sd_emmc_sel2.hw, + [CLKID_SD_EMMC] = &a1_sd_emmc.hw, + [CLKID_PSRAM_SEL] = &a1_psram_sel.hw, + [CLKID_PSRAM_DIV] = &a1_psram_div.hw, + [CLKID_PSRAM_SEL2] = &a1_psram_sel2.hw, + [CLKID_PSRAM] = &a1_psram.hw, + [CLKID_DMC_SEL] = &a1_dmc_sel.hw, + [CLKID_DMC_DIV] = &a1_dmc_div.hw, + [CLKID_DMC_SEL2] = &a1_dmc_sel2.hw, + [CLKID_DMC] = &a1_dmc.hw, + [CLKID_RTC_32K_CLKIN] = &a1_rtc_32k_clkin.hw, + [CLKID_RTC_32K_DIV] = &a1_rtc_32k_div.hw, + [CLKID_RTC_32K_XTAL] = &a1_rtc_32k_xtal.hw, + [CLKID_RTC_32K_SEL] = &a1_rtc_32k_sel.hw, + [CLKID_RTC_CLK] = &a1_rtc_clk.hw, + [CLKID_CECA_32K_CLKIN] = &a1_ceca_32k_clkin.hw, + [CLKID_CECA_32K_DIV] = &a1_ceca_32k_div.hw, + [CLKID_CECA_32K_SEL_PRE] = &a1_ceca_32k_sel_pre.hw, + [CLKID_CECA_32K_SEL] = &a1_ceca_32k_sel.hw, + [CLKID_CECA_32K] = &a1_ceca_32k_clkout.hw, + [CLKID_CECB_32K_CLKIN] = &a1_cecb_32k_clkin.hw, + [CLKID_CECB_32K_DIV] = &a1_cecb_32k_div.hw, + [CLKID_CECB_32K_SEL_PRE] = &a1_cecb_32k_sel_pre.hw, + [CLKID_CECB_32K_SEL] = &a1_cecb_32k_sel.hw, + [CLKID_CECB_32K] = &a1_cecb_32k_clkout.hw, + [NR_CLKS] = NULL, + }, + .num = NR_CLKS, +}; + +/* Convenience table to populate regmap in .probe */ +static struct clk_regmap *const a1_periphs_regmaps[] = { + &a1_xtal_clktree, + &a1_xtal_fixpll, + &a1_xtal_usb_phy, + &a1_xtal_usb_ctrl, + &a1_xtal_hifipll, + &a1_xtal_syspll, + &a1_xtal_dds, + &a1_clk_tree, + &a1_reset_ctrl, + &a1_analog_ctrl, + &a1_pwr_ctrl, + &a1_sys_ctrl, + &a1_temp_sensor, + &a1_am2axi_dev, + &a1_spicc_b, + &a1_spicc_a, + &a1_clk_msr, + &a1_audio, + &a1_jtag_ctrl, + &a1_saradc, + &a1_pwm_ef, + &a1_pwm_cd, + &a1_pwm_ab, + &a1_cec, + &a1_i2c_s, + &a1_ir_ctrl, + &a1_i2c_m_d, + &a1_i2c_m_c, + &a1_i2c_m_b, + &a1_i2c_m_a, + &a1_acodec, + &a1_otp, + &a1_sd_emmc_a, + &a1_usb_phy, + &a1_usb_ctrl, + &a1_sys_dspb, + &a1_sys_dspa, + &a1_dma, + &a1_irq_ctrl, + &a1_nic, + &a1_gic, + &a1_uart_c, + &a1_uart_b, + &a1_uart_a, + &a1_sys_psram, + &a1_rsa, + &a1_coresight, + &a1_am2axi_vad, + &a1_audio_vad, + &a1_axi_dmc, + &a1_axi_psram, + &a1_ramb, + &a1_rama, + &a1_axi_spifc, + &a1_axi_nic, + &a1_axi_dma, + &a1_cpu_ctrl, + &a1_rom, + &a1_prod_i2c, + &a1_dspa_a_sel, + &a1_dspa_a_div, + &a1_dspa_a, + &a1_dspa_b_sel, + &a1_dspa_b_div, + &a1_dspa_b, + &a1_dspa_sel, + &a1_dspb_a_sel, + &a1_dspb_a_div, + &a1_dspb_a, + &a1_dspb_b_sel, + &a1_dspb_b_div, + &a1_dspb_b, + &a1_dspb_sel, + &a1_dspa_en, + &a1_dspa_en_nic, + &a1_dspb_en, + &a1_dspb_en_nic, + &a1_24m, + &a1_12m, + &a1_fclk_div2_divn_pre, + &a1_fclk_div2_divn, + &a1_gen_sel, + &a1_gen_div, + &a1_gen, + &a1_saradc_sel, + &a1_saradc_div, + &a1_saradc_clk, + &a1_pwm_a_sel, + &a1_pwm_a_div, + &a1_pwm_a, + &a1_pwm_b_sel, + &a1_pwm_b_div, + &a1_pwm_b, + &a1_pwm_c_sel, + &a1_pwm_c_div, + &a1_pwm_c, + &a1_pwm_d_sel, + &a1_pwm_d_div, + &a1_pwm_d, + &a1_pwm_e_sel, + &a1_pwm_e_div, + &a1_pwm_e, + &a1_pwm_f_sel, + &a1_pwm_f_div, + &a1_pwm_f, + &a1_spicc_sel, + &a1_spicc_div, + &a1_spicc_sel2, + &a1_spicc, + &a1_ts_div, + &a1_ts, + &a1_spifc_sel, + &a1_spifc_div, + &a1_spifc_sel2, + &a1_spifc, + &a1_usb_bus_sel, + &a1_usb_bus_div, + &a1_usb_bus, + &a1_sd_emmc_sel, + &a1_sd_emmc_div, + &a1_sd_emmc_sel2, + &a1_sd_emmc, + &a1_psram_sel, + &a1_psram_div, + &a1_psram_sel2, + &a1_psram, + &a1_dmc_sel, + &a1_dmc_div, + &a1_dmc_sel2, + &a1_dmc, + &a1_sys_b_sel, + &a1_sys_b_div, + &a1_sys_b, + &a1_sys_a_sel, + &a1_sys_a_div, + &a1_sys_a, + &a1_sys_clk, + &a1_rtc_32k_clkin, + &a1_rtc_32k_div, + &a1_rtc_32k_xtal, + &a1_rtc_32k_sel, + &a1_rtc_clk, + &a1_ceca_32k_clkin, + &a1_ceca_32k_div, + &a1_ceca_32k_sel_pre, + &a1_ceca_32k_sel, + &a1_ceca_32k_clkout, + &a1_cecb_32k_clkin, + &a1_cecb_32k_div, + &a1_cecb_32k_sel_pre, + &a1_cecb_32k_sel, + &a1_cecb_32k_clkout, +}; + +static struct regmap_config clkc_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, +}; + +static int meson_a1_periphs_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct resource *res; + void __iomem *base; + struct regmap *map; + int ret, i; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + map = devm_regmap_init_mmio(dev, base, &clkc_regmap_config); + if (IS_ERR(map)) + return PTR_ERR(map); + + /* Populate regmap for the regmap backed clocks */ + for (i = 0; i < ARRAY_SIZE(a1_periphs_regmaps); i++) + a1_periphs_regmaps[i]->map = map; + + for (i = 0; i < a1_periphs_hw_onecell_data.num; i++) { + /* array might be sparse */ + if (!a1_periphs_hw_onecell_data.hws[i]) + continue; + + ret = devm_clk_hw_register(dev, + a1_periphs_hw_onecell_data.hws[i]); + if (ret) { + dev_err(dev, "Clock registration failed\n"); + return ret; + } + } + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + &a1_periphs_hw_onecell_data); +} + +static const struct of_device_id clkc_match_table[] = { + { .compatible = "amlogic,a1-periphs-clkc", }, + {} +}; + +static struct platform_driver a1_periphs_driver = { + .probe = meson_a1_periphs_probe, + .driver = { + .name = "a1-periphs-clkc", + .of_match_table = clkc_match_table, + }, +}; + +builtin_platform_driver(a1_periphs_driver); diff --git a/drivers/clk/meson/a1.h b/drivers/clk/meson/a1.h new file mode 100644 index 000000000000..1ae5e04848d6 --- /dev/null +++ b/drivers/clk/meson/a1.h @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __A1_H +#define __A1_H + +/* peripheral clock controller register offset */ +#define SYS_OSCIN_CTRL 0x0 +#define RTC_BY_OSCIN_CTRL0 0x4 +#define RTC_BY_OSCIN_CTRL1 0x8 +#define RTC_CTRL 0xc +#define SYS_CLK_CTRL0 0x10 +#define AXI_CLK_CTRL0 0x14 +#define SYS_CLK_EN0 0x1c +#define SYS_CLK_EN1 0x20 +#define AXI_CLK_EN 0x24 +#define DSPA_CLK_EN 0x28 +#define DSPB_CLK_EN 0x2c +#define DSPA_CLK_CTRL0 0x30 +#define DSPB_CLK_CTRL0 0x34 +#define CLK12_24_CTRL 0x38 +#define GEN_CLK_CTRL 0x3c +#define TIMESTAMP_CTRL0 0x40 +#define TIMESTAMP_CTRL1 0x44 +#define TIMESTAMP_CTRL2 0x48 +#define TIMESTAMP_VAL0 0x4c +#define TIMESTAMP_VAL1 0x50 +#define TIMEBASE_CTRL0 0x54 +#define TIMEBASE_CTRL1 0x58 +#define SAR_ADC_CLK_CTRL 0xc0 +#define PWM_CLK_AB_CTRL 0xc4 +#define PWM_CLK_CD_CTRL 0xc8 +#define PWM_CLK_EF_CTRL 0xcc +#define SPICC_CLK_CTRL 0xd0 +#define TS_CLK_CTRL 0xd4 +#define SPIFC_CLK_CTRL 0xd8 +#define USB_BUSCLK_CTRL 0xdc +#define SD_EMMC_CLK_CTRL 0xe0 +#define CECA_CLK_CTRL0 0xe4 +#define CECA_CLK_CTRL1 0xe8 +#define CECB_CLK_CTRL0 0xec +#define CECB_CLK_CTRL1 0xf0 +#define PSRAM_CLK_CTRL 0xf4 +#define DMC_CLK_CTRL 0xf8 +#define FCLK_DIV1_SEL 0xfc +#define TST_CTRL 0x100 + +#define CLKID_XTAL_CLKTREE 0 +#define CLKID_SYS_A_SEL 89 +#define CLKID_SYS_A_DIV 90 +#define CLKID_SYS_A 91 +#define CLKID_SYS_B_SEL 92 +#define CLKID_SYS_B_DIV 93 +#define CLKID_SYS_B 94 +#define CLKID_DSPA_A_SEL 95 +#define CLKID_DSPA_A_DIV 96 +#define CLKID_DSPA_A 97 +#define CLKID_DSPA_B_SEL 98 +#define CLKID_DSPA_B_DIV 99 +#define CLKID_DSPA_B 100 +#define CLKID_DSPB_A_SEL 101 +#define CLKID_DSPB_A_DIV 102 +#define CLKID_DSPB_A 103 +#define CLKID_DSPB_B_SEL 104 +#define CLKID_DSPB_B_DIV 105 +#define CLKID_DSPB_B 106 +#define CLKID_RTC_32K_CLKIN 107 +#define CLKID_RTC_32K_DIV 108 +#define CLKID_RTC_32K_XTAL 109 +#define CLKID_RTC_32K_SEL 110 +#define CLKID_CECB_32K_CLKIN 111 +#define CLKID_CECB_32K_DIV 112 +#define CLKID_CECB_32K_SEL_PRE 113 +#define CLKID_CECB_32K_SEL 114 +#define CLKID_CECA_32K_CLKIN 115 +#define CLKID_CECA_32K_DIV 116 +#define CLKID_CECA_32K_SEL_PRE 117 +#define CLKID_CECA_32K_SEL 118 +#define CLKID_DIV2_PRE 119 +#define CLKID_24M_DIV2 120 +#define CLKID_GEN_SEL 121 +#define CLKID_GEN_DIV 122 +#define CLKID_SARADC_DIV 123 +#define CLKID_PWM_A_SEL 124 +#define CLKID_PWM_A_DIV 125 +#define CLKID_PWM_B_SEL 126 +#define CLKID_PWM_B_DIV 127 +#define CLKID_PWM_C_SEL 128 +#define CLKID_PWM_C_DIV 129 +#define CLKID_PWM_D_SEL 130 +#define CLKID_PWM_D_DIV 131 +#define CLKID_PWM_E_SEL 132 +#define CLKID_PWM_E_DIV 133 +#define CLKID_PWM_F_SEL 134 +#define CLKID_PWM_F_DIV 135 +#define CLKID_SPICC_SEL 136 +#define CLKID_SPICC_DIV 137 +#define CLKID_SPICC_SEL2 138 +#define CLKID_TS_DIV 139 +#define CLKID_SPIFC_SEL 140 +#define CLKID_SPIFC_DIV 141 +#define CLKID_SPIFC_SEL2 142 +#define CLKID_USB_BUS_SEL 143 +#define CLKID_USB_BUS_DIV 144 +#define CLKID_SD_EMMC_SEL 145 +#define CLKID_SD_EMMC_DIV 146 +#define CLKID_SD_EMMC_SEL2 147 +#define CLKID_PSRAM_SEL 148 +#define CLKID_PSRAM_DIV 149 +#define CLKID_PSRAM_SEL2 150 +#define CLKID_DMC_SEL 151 +#define CLKID_DMC_DIV 152 +#define CLKID_DMC_SEL2 153 +#define NR_CLKS 154 + +#include + +#endif /* __A1_H */ From patchwork Thu Dec 1 22:56:57 2022 Content-Type: text/plain; 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The main difference is located in the init/enable/disable sequences; the rate logic is the same. So drivers for the new PLLs can be inherited from the clk-pll driver and redefine init/enable/disable routines only. For that purpose we need to have meson_clk_pll_wait_lock() in the export symbols list, because each lock operation should be ended with wait cycles. Signed-off-by: Dmitry Rokosov --- drivers/clk/meson/clk-pll.c | 3 ++- drivers/clk/meson/clk-pll.h | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index 9e55617bc3b4..81c810d57a48 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -273,7 +273,7 @@ static int meson_clk_pll_determine_rate(struct clk_hw *hw, return 0; } -static int meson_clk_pll_wait_lock(struct clk_hw *hw) +int meson_clk_pll_wait_lock(struct clk_hw *hw) { struct clk_regmap *clk = to_clk_regmap(hw); struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); @@ -289,6 +289,7 @@ static int meson_clk_pll_wait_lock(struct clk_hw *hw) return -ETIMEDOUT; } +EXPORT_SYMBOL_GPL(meson_clk_pll_wait_lock); static int meson_clk_pll_init(struct clk_hw *hw) { diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h index 367efd0f6410..85fec18c4b8a 100644 --- a/drivers/clk/meson/clk-pll.h +++ b/drivers/clk/meson/clk-pll.h @@ -47,4 +47,6 @@ extern const struct clk_ops meson_clk_pll_ro_ops; extern const struct clk_ops meson_clk_pll_ops; extern const struct clk_ops meson_clk_pcie_pll_ops; +int meson_clk_pll_wait_lock(struct clk_hw *hw); + #endif /* __MESON_CLK_PLL_H */ From patchwork Thu Dec 1 22:56:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Rokosov X-Patchwork-Id: 28580 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp529046wrr; Thu, 1 Dec 2022 15:00:50 -0800 (PST) X-Google-Smtp-Source: AA0mqf7hX9ZZ3TWJ5zONCQ3UanVl2VYLgc8AT4S5Q+lgC4kR+NnBOZg4cd7iMwcpKskfQ+hLFyc5 X-Received: by 2002:a17:906:1748:b0:7b2:7fa8:3d84 with SMTP id d8-20020a170906174800b007b27fa83d84mr15732667eje.650.1669935649912; Thu, 01 Dec 2022 15:00:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669935649; cv=none; d=google.com; s=arc-20160816; b=Sec4eAK5O+qiOsM8N0D7EH8pN0UpUrllRMeQ2q+JFa5CAkDWJWapy6KuBPSeQnUlOW RSwGvD6sZ8A48BerxUB3aZpFxizcGuO4/CYE28bIZBWcGMN0tuUYOIJl0NWOEInW3M7b vg0oGooioeMoNJ92buQI/jRWlUgMMoLLqFMLJOfczB5sDh0DXoMsWhZCZlE9586oXS5Q ur72EX0ORpD2gyG3jIGqjxJb3NZGGpM4bk7FAllaQEF4iCRH1NM+Tv2A9KQEqu9rseHo eua1d0T4DGuCRqr1bg6XyfoaYFSG7b/XSGEERKlCSaWWx4yXrztb+d1J6VKGsiQ84nV0 aG9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=nLy/4b8i+xMemeS4hoDjkYNxHQBeN/nSL76OykbPHmM=; b=N0UT3U5VTxUEvQ8w8y/gG4b4KZNmRVR2MNbTyxT4xGRd15QqWFPUg98Xdl4pEoCT+B NER24ixwnfWr1grdShdxRMLW+9vCpwaVurKDr/U1m3N8mIBLmPH8CuAEnTNP1YaIyxCv GZLNu3tpyOJhZYzc0dLx/r/9Cnxp79KXjBLiJQ3Zl9KfXhkopqhkU5ha2r7ABjni482f 73yMFTJjtWQ3txV2fNGtmX6CBgKHKBGn0SDhywJO5Gu5zfje8ij1JlhIEIYWhbXCAfJd I1rZMyZviPNcchKZYjOGFIo9dd0KU/I/s+qw+OhLCB8sXMpF7AbIUlNr5pug38Ne4eQZ +UAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sberdevices.ru header.s=mail header.b=RXK5VNxF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=sberdevices.ru Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id h6-20020a056402280600b00463cd7d6e7asi4963291ede.30.2022.12.01.15.00.25; Thu, 01 Dec 2022 15:00:49 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@sberdevices.ru header.s=mail header.b=RXK5VNxF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=sberdevices.ru Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231803AbiLAW6K (ORCPT + 99 others); Thu, 1 Dec 2022 17:58:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51064 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231671AbiLAW5k (ORCPT ); Thu, 1 Dec 2022 17:57:40 -0500 Received: from mx.sberdevices.ru (mx.sberdevices.ru [45.89.227.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8164A1B7; Thu, 1 Dec 2022 14:57:38 -0800 (PST) Received: from s-lin-edge02.sberdevices.ru (localhost [127.0.0.1]) by mx.sberdevices.ru (Postfix) with ESMTP id 266CF5FD10; Fri, 2 Dec 2022 01:57:33 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sberdevices.ru; s=mail; t=1669935453; bh=nLy/4b8i+xMemeS4hoDjkYNxHQBeN/nSL76OykbPHmM=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type; b=RXK5VNxFeGUkUgpr/1p32w/BEOuGguD/Jkj6QIAutFore0z29ROYG48QCdgVHTy3w GEiFA97xM/JMM9uiq1wA7mE+Six3c4IftH8cuKhO4if13/7XEHS9sC/PVsIsb1zjNC 0XVDuoKap+rzv/FTrHVvbmtr8Ihkraxk+bCficfezNsu3xDZMiNLKMmQjH/qN74PRw jknvsLUqSr0+W8UK1y/CwV32Pi03UchJ/BjjZpH6MrYSMdt49dNtG1Oxww6PnttyCW N8La6v4MrpzzpXRlYgt08hvCCyaUmvpNYWxmGE/4chbVSlvkgPlzhsRDAxoj0vEDXB ysORhjsnCjFsg== Received: from S-MS-EXCH01.sberdevices.ru (S-MS-EXCH01.sberdevices.ru [172.16.1.4]) by mx.sberdevices.ru (Postfix) with ESMTP; Fri, 2 Dec 2022 01:57:33 +0300 (MSK) From: Dmitry Rokosov To: , , , , , , , CC: , , , , , , , , Dmitry Rokosov Subject: [PATCH v8 06/11] clk: meson: introduce a1-clkc common driver for all A1 clock controllers Date: Fri, 2 Dec 2022 01:56:58 +0300 Message-ID: <20221201225703.6507-7-ddrokosov@sberdevices.ru> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20221201225703.6507-1-ddrokosov@sberdevices.ru> References: <20221201225703.6507-1-ddrokosov@sberdevices.ru> MIME-Version: 1.0 X-Originating-IP: [172.16.1.6] X-ClientProxiedBy: S-MS-EXCH02.sberdevices.ru (172.16.1.5) To S-MS-EXCH01.sberdevices.ru (172.16.1.4) X-KSMG-Rule-ID: 4 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Status: not scanned, disabled by settings X-KSMG-AntiSpam-Interceptor-Info: not scanned X-KSMG-AntiPhishing: not scanned, disabled by settings X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 1.1.2.30, bases: 2022/12/01 20:49:00 #20634374 X-KSMG-AntiVirus-Status: Clean, skipped X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751054444009788952?= X-GMAIL-MSGID: =?utf-8?q?1751054444009788952?= Generally, A1 SoC has four clock controllers on the board: PLL, Peripherals, CPU, and Audio. The audio clock controller is different from others, but the rest are very similar from a functional and regmap point of view. So a it's good idea to generalize some routines for all of them. Exactly, meson-a1-clkc driver contains the common probe() flow. Signed-off-by: Dmitry Rokosov --- drivers/clk/meson/Kconfig | 4 ++ drivers/clk/meson/Makefile | 1 + drivers/clk/meson/meson-a1-clkc.c | 63 +++++++++++++++++++++++++++++++ drivers/clk/meson/meson-a1-clkc.h | 25 ++++++++++++ 4 files changed, 93 insertions(+) create mode 100644 drivers/clk/meson/meson-a1-clkc.c create mode 100644 drivers/clk/meson/meson-a1-clkc.h diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index bd44ba47200e..1c885541c3a9 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -43,6 +43,10 @@ config COMMON_CLK_MESON_CPU_DYNDIV tristate select COMMON_CLK_MESON_REGMAP +config COMMON_CLK_MESON_A1_CLKC + tristate + select COMMON_CLK_MESON_REGMAP + config COMMON_CLK_MESON8B bool "Meson8 SoC Clock controller support" depends on ARM diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 0e6f293c05d4..15136d861a65 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o obj-$(CONFIG_COMMON_CLK_MESON_REGMAP) += clk-regmap.o obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) += sclk-div.o obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o +obj-$(CONFIG_COMMON_CLK_MESON_A1_CLKC) += meson-a1-clkc.o # Amlogic Clock controllers diff --git a/drivers/clk/meson/meson-a1-clkc.c b/drivers/clk/meson/meson-a1-clkc.c new file mode 100644 index 000000000000..2fe320a0e16e --- /dev/null +++ b/drivers/clk/meson/meson-a1-clkc.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Amlogic Meson-A1 Clock Controller Driver + * + * Copyright (c) 2022, SberDevices. All Rights Reserved. + * Author: Dmitry Rokosov + */ + +#include +#include "meson-a1-clkc.h" + +static struct regmap_config clkc_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, +}; + +int meson_a1_clkc_probe(struct platform_device *pdev) +{ + struct meson_a1_clkc_data *clkc; + struct device *dev = &pdev->dev; + struct resource *res; + void __iomem *base; + struct regmap *map; + int clkid, i, err; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return dev_err_probe(dev, -ENXIO, "can't get IO resource\n"); + + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return dev_err_probe(dev, PTR_ERR(base), + "can't ioremap resource %pr\n", res); + + map = devm_regmap_init_mmio(dev, base, &clkc_regmap_config); + if (IS_ERR(map)) + return dev_err_probe(dev, PTR_ERR(map), + "can't init regmap mmio region\n"); + + clkc = (struct meson_a1_clkc_data *)of_device_get_match_data(dev); + if (!clkc) + return dev_err_probe(dev, -ENODEV, + "can't get A1 clkc driver data\n"); + + /* Populate regmap for the regmap backed clocks */ + for (i = 0; i < clkc->num_regs; i++) + clkc->regs[i]->map = map; + + for (clkid = 0; clkid < clkc->hw->num; clkid++) { + err = devm_clk_hw_register(dev, clkc->hw->hws[clkid]); + if (err) + return dev_err_probe(dev, err, + "clock registration failed\n"); + } + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + (void *)clkc->hw); +} +EXPORT_SYMBOL_GPL(meson_a1_clkc_probe); + +MODULE_AUTHOR("Dmitry Rokosov "); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/meson/meson-a1-clkc.h b/drivers/clk/meson/meson-a1-clkc.h new file mode 100644 index 000000000000..503eca0f6cb5 --- /dev/null +++ b/drivers/clk/meson/meson-a1-clkc.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Amlogic Meson-A1 Clock Controller driver + * + * Copyright (c) 2022, SberDevices. All Rights Reserved. + * Author: Dmitry Rokosov + */ + +#ifndef __MESON_A1_CLKC_H__ +#define __MESON_A1_CLKC_H__ + +#include +#include +#include + +#include "clk-regmap.h" + +struct meson_a1_clkc_data { + const struct clk_hw_onecell_data *hw; + struct clk_regmap *const *regs; + size_t num_regs; +}; + +int meson_a1_clkc_probe(struct platform_device *pdev); +#endif From patchwork Thu Dec 1 22:56:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Rokosov X-Patchwork-Id: 28581 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp529260wrr; Thu, 1 Dec 2022 15:01:16 -0800 (PST) X-Google-Smtp-Source: AA0mqf6w1adTi9AKYbCQlspkFe2XFR/d4TDeT6JwN/2M4RQi3Gz06yokLzUzV9zoYo2/V4/kchjk X-Received: by 2002:a17:902:7d98:b0:17e:6852:1191 with SMTP id a24-20020a1709027d9800b0017e68521191mr60156005plm.159.1669935675957; Thu, 01 Dec 2022 15:01:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669935675; cv=none; d=google.com; s=arc-20160816; b=Gbgqg4Zv2QLYAms6xpvnnsrNQLqlH8QyXDswC7EPcFqZ89Q2dfS5FSexrEKJ2kK1N3 n2XPfBL6fkCuZccVKPVnnCrLifaJRRiZ+5p2fgegMn2ppmTLlTvQ5U+t1ogm20FYBshQ ZcFTd8GIeJAHQ+vAxYzcKBeqlZY8++ND+PC+4LD9q1Zv9QuzjSvuubMEAM1ubfD0uiSb TV62Cl5C1BRj6E1E9RmCHs/tZfnAlGJLpfZECn/WZGdmNxmxgTd+jIU+LucBShr3yisO r9cDtPn3U56myfkhQA3hCMDyvOkbbbPETtCdCpK10syeDYlEZKRuetavJpGKi0ETdaPU s1FQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=yHtPjPY3Pi0E/KZWXUevKiyPqbylvlBtgVBnbDvgnbs=; b=hhaOOIeFmMVboIUWflElHcEtOMEN0Lpac7gHjb2Ty7Hcx8l/V0/ChH+SbeuCrtRZEZ 4btPMQVcaSWw5g+YbETY5idWvVkGCULNy9SteAyqXJDwyKZR93dneTLtlaOLw3eavQjg C6dBTCKjqfoQOBMkAhR1/8l4TgDd+ubWsOBc9mz2rE8lZJ5GnnpL1r0HQFDwklvSsEqM yJ7Mq2dG1JQSI4N1zvBRXZi28TsceznX3ZWStl3rcRd5bS5iahpLfZdsFvXWmcLGVCpu QFeeTNzEHps9mTI1QMxvYkcI4mN2zt1BPCqDOHT15x1vD64TiE4MAK/eWWRptpuKKYG/ nWdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sberdevices.ru header.s=mail header.b=LFOHEGZm; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=sberdevices.ru Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id j7-20020a056a00234700b0056c057b09b0si6638229pfj.216.2022.12.01.15.01.00; Thu, 01 Dec 2022 15:01:15 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@sberdevices.ru header.s=mail header.b=LFOHEGZm; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=sberdevices.ru Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231817AbiLAW6U (ORCPT + 99 others); Thu, 1 Dec 2022 17:58:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231676AbiLAW5k (ORCPT ); Thu, 1 Dec 2022 17:57:40 -0500 Received: from mx.sberdevices.ru (mx.sberdevices.ru [45.89.227.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A377FA18D; Thu, 1 Dec 2022 14:57:38 -0800 (PST) Received: from s-lin-edge02.sberdevices.ru (localhost [127.0.0.1]) by mx.sberdevices.ru (Postfix) with ESMTP id 9A1625FD11; Fri, 2 Dec 2022 01:57:34 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sberdevices.ru; s=mail; t=1669935454; bh=yHtPjPY3Pi0E/KZWXUevKiyPqbylvlBtgVBnbDvgnbs=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type; b=LFOHEGZmp06vMwQ5GWGxpoVqJ/+6kVODPQp18Ln2PwmfT920wdR6JTl+lEMra3y6g USXmvoFfvUa9p1zdBVBZRDhgKpgXnORpNaS2xOQCihCXCe5tKcsRMrmzu5HiI4MSuN y/FmvsV3z9cpShuuM1k+z1ZDHS5+jBWxyhWcnL5qb8vzyVlBrr00kXRF+w6xT/iYLq xinQQ+3Zlz2GpPO3YXUMDpV2ubuCZJa18HZbl/Hv0Ab8pZNQQSdVQ2cqyUcLc3wgWB WHDK44JlpTdoQWwYtU9LW3F1hFIz7DHxBuP5x40tJHN9Nzw39ajzDRH///UV2DP7sE XyJ5Xr1ujMkVg== Received: from S-MS-EXCH01.sberdevices.ru (S-MS-EXCH01.sberdevices.ru [172.16.1.4]) by mx.sberdevices.ru (Postfix) with ESMTP; Fri, 2 Dec 2022 01:57:34 +0300 (MSK) From: Dmitry Rokosov To: , , , , , , , CC: , , , , , , , , Dmitry Rokosov Subject: [PATCH v8 07/11] clk: meson: a1: redesign Amlogic A1 PLL clock controller Date: Fri, 2 Dec 2022 01:56:59 +0300 Message-ID: <20221201225703.6507-8-ddrokosov@sberdevices.ru> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20221201225703.6507-1-ddrokosov@sberdevices.ru> References: <20221201225703.6507-1-ddrokosov@sberdevices.ru> MIME-Version: 1.0 X-Originating-IP: [172.16.1.6] X-ClientProxiedBy: S-MS-EXCH02.sberdevices.ru (172.16.1.5) To S-MS-EXCH01.sberdevices.ru (172.16.1.4) X-KSMG-Rule-ID: 4 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Status: not scanned, disabled by settings X-KSMG-AntiSpam-Interceptor-Info: not scanned X-KSMG-AntiPhishing: not scanned, disabled by settings X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 1.1.2.30, bases: 2022/12/01 20:49:00 #20634374 X-KSMG-AntiVirus-Status: Clean, skipped X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751054471820420496?= X-GMAIL-MSGID: =?utf-8?q?1751054471820420496?= Summary changes: - supported meson-a1-clkc common driver - inherited from the base clk-pll driver, implemented own version of init/enable/disable/enabled routines; rate calculating logic is fully the same - aligned CLKID-related definitions with CLKID list from order perspective to remove holes and permutations - corrected Kconfig dependencies and types - provided correct MODULE_AUTHORs() and MODULE_LICENSE() - optimized and fix up some clock relationships - removed unused register offset definitions (ANACTRL_* group) Signed-off-by: Dmitry Rokosov --- drivers/clk/meson/Kconfig | 5 +- drivers/clk/meson/a1-pll.c | 267 +++++++++++++++++++++++++------------ drivers/clk/meson/a1-pll.h | 37 ++--- 3 files changed, 202 insertions(+), 107 deletions(-) diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 1c885541c3a9..deb273673ec1 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -104,10 +104,11 @@ config COMMON_CLK_AXG_AUDIO aka axg, Say Y if you want audio subsystem to work. config COMMON_CLK_A1_PLL - bool - depends on ARCH_MESON + tristate "Meson A1 SoC PLL controller support" + depends on ARM64 select COMMON_CLK_MESON_REGMAP select COMMON_CLK_MESON_PLL + select COMMON_CLK_MESON_A1_CLKC help Support for the PLL clock controller on Amlogic A113L device, aka a1. Say Y if you want PLL to work. diff --git a/drivers/clk/meson/a1-pll.c b/drivers/clk/meson/a1-pll.c index 69c1ca07d041..23487ca797b3 100644 --- a/drivers/clk/meson/a1-pll.c +++ b/drivers/clk/meson/a1-pll.c @@ -2,15 +2,133 @@ /* * Copyright (c) 2019 Amlogic, Inc. All rights reserved. * Author: Jian Hu + * + * Copyright (c) 2022, SberDevices. All Rights Reserved. + * Author: Dmitry Rokosov */ #include #include #include +#include "meson-a1-clkc.h" #include "a1-pll.h" -#include "clk-pll.h" #include "clk-regmap.h" +static inline +struct meson_a1_pll_data *meson_a1_pll_data(struct clk_regmap *clk) +{ + return (struct meson_a1_pll_data *)clk->data; +} + +static int meson_a1_pll_init(struct clk_hw *hw) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_a1_pll_data *pll = meson_a1_pll_data(clk); + + regmap_multi_reg_write(clk->map, pll->base.init_regs, + pll->base.init_count); + + return 0; +} + +static int meson_a1_pll_is_enabled(struct clk_hw *hw) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_a1_pll_data *pll = meson_a1_pll_data(clk); + + if (MESON_PARM_APPLICABLE(&pll->base.rst) && + meson_parm_read(clk->map, &pll->base.rst)) + return 0; + + if (!meson_parm_read(clk->map, &pll->base.en) || + !meson_parm_read(clk->map, &pll->base.l)) + return 0; + + return 1; +} + +static int meson_a1_pll_enable(struct clk_hw *hw) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_a1_pll_data *pll = meson_a1_pll_data(clk); + + /* Do nothing if the PLL is already enabled */ + if (clk_hw_is_enabled(hw)) + return 0; + + /* Enable the pll */ + meson_parm_write(clk->map, &pll->base.en, 1); + + /* + * Compared with the previous SoCs, self-adaption current module + * is newly added for A1, keep the new power-on sequence to enable the + * PLL. The sequence is: + * 1. enable the pll, delay for 10us + * 2. enable the pll self-adaption current module, delay for 40us + * 3. enable the lock detect module + */ + usleep_range(10, 20); + meson_parm_write(clk->map, &pll->current_en, 1); + usleep_range(40, 50); + + meson_parm_write(clk->map, &pll->l_detect, 1); + meson_parm_write(clk->map, &pll->l_detect, 0); + + if (meson_clk_pll_wait_lock(hw)) + return -EIO; + + return 0; +} + +static void meson_a1_pll_disable(struct clk_hw *hw) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_a1_pll_data *pll = meson_a1_pll_data(clk); + + /* Disable the pll */ + meson_parm_write(clk->map, &pll->base.en, 0); + + /* Disable PLL internal self-adaption current module */ + meson_parm_write(clk->map, &pll->current_en, 0); +} + +/* + * A1 PLL clock controller driver is based on meson clk_pll driver, + * so some rate calculating routines are reused + */ +static unsigned long meson_a1_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return meson_clk_pll_ops.recalc_rate(hw, parent_rate); +} + +static int meson_a1_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + return meson_clk_pll_ops.determine_rate(hw, req); +} + +static int meson_a1_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + return meson_clk_pll_ops.set_rate(hw, rate, parent_rate); +} + +static const struct clk_ops meson_a1_pll_ops = { + .init = meson_a1_pll_init, + .recalc_rate = meson_a1_pll_recalc_rate, + .determine_rate = meson_a1_pll_determine_rate, + .set_rate = meson_a1_pll_set_rate, + .is_enabled = meson_a1_pll_is_enabled, + .enable = meson_a1_pll_enable, + .disable = meson_a1_pll_disable +}; + +static const struct clk_ops meson_a1_pll_ro_ops = { + .recalc_rate = meson_a1_pll_recalc_rate, + .is_enabled = meson_a1_pll_is_enabled, +}; + static struct clk_regmap a1_fixed_pll_dco = { .data = &(struct meson_clk_pll_data){ .en = { @@ -46,7 +164,7 @@ static struct clk_regmap a1_fixed_pll_dco = { }, .hw.init = &(struct clk_init_data){ .name = "fixed_pll_dco", - .ops = &meson_clk_pll_ro_ops, + .ops = &meson_a1_pll_ro_ops, .parent_data = &(const struct clk_parent_data) { .fw_name = "xtal_fixpll", }, @@ -87,31 +205,36 @@ static const struct reg_sequence a1_hifi_init_regs[] = { }; static struct clk_regmap a1_hifi_pll = { - .data = &(struct meson_clk_pll_data){ - .en = { - .reg_off = ANACTRL_HIFIPLL_CTRL0, - .shift = 28, - .width = 1, - }, - .m = { - .reg_off = ANACTRL_HIFIPLL_CTRL0, - .shift = 0, - .width = 8, - }, - .n = { - .reg_off = ANACTRL_HIFIPLL_CTRL0, - .shift = 10, - .width = 5, - }, - .frac = { - .reg_off = ANACTRL_HIFIPLL_CTRL1, - .shift = 0, - .width = 19, - }, - .l = { - .reg_off = ANACTRL_HIFIPLL_STS, - .shift = 31, - .width = 1, + .data = &(struct meson_a1_pll_data){ + .base = { + .en = { + .reg_off = ANACTRL_HIFIPLL_CTRL0, + .shift = 28, + .width = 1, + }, + .m = { + .reg_off = ANACTRL_HIFIPLL_CTRL0, + .shift = 0, + .width = 8, + }, + .n = { + .reg_off = ANACTRL_HIFIPLL_CTRL0, + .shift = 10, + .width = 5, + }, + .frac = { + .reg_off = ANACTRL_HIFIPLL_CTRL1, + .shift = 0, + .width = 19, + }, + .l = { + .reg_off = ANACTRL_HIFIPLL_STS, + .shift = 31, + .width = 1, + }, + .range = &a1_hifi_pll_mult_range, + .init_regs = a1_hifi_init_regs, + .init_count = ARRAY_SIZE(a1_hifi_init_regs), }, .current_en = { .reg_off = ANACTRL_HIFIPLL_CTRL0, @@ -123,13 +246,10 @@ static struct clk_regmap a1_hifi_pll = { .shift = 6, .width = 1, }, - .range = &a1_hifi_pll_mult_range, - .init_regs = a1_hifi_init_regs, - .init_count = ARRAY_SIZE(a1_hifi_init_regs), }, .hw.init = &(struct clk_init_data){ .name = "hifi_pll", - .ops = &meson_clk_pll_ops, + .ops = &meson_a1_pll_ops, .parent_data = &(const struct clk_parent_data) { .fw_name = "xtal_hifipll", }, @@ -276,15 +396,15 @@ static struct clk_hw_onecell_data a1_pll_hw_onecell_data = { .hws = { [CLKID_FIXED_PLL_DCO] = &a1_fixed_pll_dco.hw, [CLKID_FIXED_PLL] = &a1_fixed_pll.hw, - [CLKID_HIFI_PLL] = &a1_hifi_pll.hw, - [CLKID_FCLK_DIV2] = &a1_fclk_div2.hw, - [CLKID_FCLK_DIV3] = &a1_fclk_div3.hw, - [CLKID_FCLK_DIV5] = &a1_fclk_div5.hw, - [CLKID_FCLK_DIV7] = &a1_fclk_div7.hw, [CLKID_FCLK_DIV2_DIV] = &a1_fclk_div2_div.hw, [CLKID_FCLK_DIV3_DIV] = &a1_fclk_div3_div.hw, [CLKID_FCLK_DIV5_DIV] = &a1_fclk_div5_div.hw, [CLKID_FCLK_DIV7_DIV] = &a1_fclk_div7_div.hw, + [CLKID_FCLK_DIV2] = &a1_fclk_div2.hw, + [CLKID_FCLK_DIV3] = &a1_fclk_div3.hw, + [CLKID_FCLK_DIV5] = &a1_fclk_div5.hw, + [CLKID_FCLK_DIV7] = &a1_fclk_div7.hw, + [CLKID_HIFI_PLL] = &a1_hifi_pll.hw, [NR_PLL_CLKS] = NULL, }, .num = NR_PLL_CLKS, @@ -293,68 +413,39 @@ static struct clk_hw_onecell_data a1_pll_hw_onecell_data = { static struct clk_regmap *const a1_pll_regmaps[] = { &a1_fixed_pll_dco, &a1_fixed_pll, - &a1_hifi_pll, &a1_fclk_div2, &a1_fclk_div3, &a1_fclk_div5, &a1_fclk_div7, + &a1_hifi_pll, }; -static struct regmap_config clkc_regmap_config = { - .reg_bits = 32, - .val_bits = 32, - .reg_stride = 4, +static const struct meson_a1_clkc_data a1_pll_clkc __maybe_unused = { + .hw = &a1_pll_hw_onecell_data, + .regs = a1_pll_regmaps, + .num_regs = ARRAY_SIZE(a1_pll_regmaps), }; -static int meson_a1_pll_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct resource *res; - void __iomem *base; - struct regmap *map; - int ret, i; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - - base = devm_ioremap_resource(dev, res); - if (IS_ERR(base)) - return PTR_ERR(base); - - map = devm_regmap_init_mmio(dev, base, &clkc_regmap_config); - if (IS_ERR(map)) - return PTR_ERR(map); - - /* Populate regmap for the regmap backed clocks */ - for (i = 0; i < ARRAY_SIZE(a1_pll_regmaps); i++) - a1_pll_regmaps[i]->map = map; - - for (i = 0; i < a1_pll_hw_onecell_data.num; i++) { - /* array might be sparse */ - if (!a1_pll_hw_onecell_data.hws[i]) - continue; - - ret = devm_clk_hw_register(dev, a1_pll_hw_onecell_data.hws[i]); - if (ret) { - dev_err(dev, "Clock registration failed\n"); - return ret; - } - } - - return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, - &a1_pll_hw_onecell_data); -} - -static const struct of_device_id clkc_match_table[] = { - { .compatible = "amlogic,a1-pll-clkc", }, - {} +#ifdef CONFIG_OF +static const struct of_device_id a1_pll_clkc_match_table[] = { + { + .compatible = "amlogic,a1-pll-clkc", + .data = &a1_pll_clkc, + }, + {}, }; +MODULE_DEVICE_TABLE(of, a1_pll_clkc_match_table); +#endif /* CONFIG_OF */ -static struct platform_driver a1_pll_driver = { - .probe = meson_a1_pll_probe, - .driver = { - .name = "a1-pll-clkc", - .of_match_table = clkc_match_table, +static struct platform_driver a1_pll_clkc_driver = { + .probe = meson_a1_clkc_probe, + .driver = { + .name = "a1-pll-clkc", + .of_match_table = of_match_ptr(a1_pll_clkc_match_table), }, }; -builtin_platform_driver(a1_pll_driver); +module_platform_driver(a1_pll_clkc_driver); +MODULE_AUTHOR("Jian Hu "); +MODULE_AUTHOR("Dmitry Rokosov "); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/meson/a1-pll.h b/drivers/clk/meson/a1-pll.h index 8ded267061ad..2ff5a2042a97 100644 --- a/drivers/clk/meson/a1-pll.h +++ b/drivers/clk/meson/a1-pll.h @@ -1,38 +1,29 @@ /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* + * Amlogic Meson-A1 PLL Clock Controller internals + * * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + * Author: Jian Hu + * + * Copyright (c) 2022, SberDevices. All Rights Reserved. + * Author: Dmitry Rokosov */ #ifndef __A1_PLL_H #define __A1_PLL_H +#include "clk-pll.h" + /* PLL register offset */ #define ANACTRL_FIXPLL_CTRL0 0x0 #define ANACTRL_FIXPLL_CTRL1 0x4 -#define ANACTRL_FIXPLL_CTRL2 0x8 -#define ANACTRL_FIXPLL_CTRL3 0xc -#define ANACTRL_FIXPLL_CTRL4 0x10 #define ANACTRL_FIXPLL_STS 0x14 -#define ANACTRL_SYSPLL_CTRL0 0x80 -#define ANACTRL_SYSPLL_CTRL1 0x84 -#define ANACTRL_SYSPLL_CTRL2 0x88 -#define ANACTRL_SYSPLL_CTRL3 0x8c -#define ANACTRL_SYSPLL_CTRL4 0x90 -#define ANACTRL_SYSPLL_STS 0x94 #define ANACTRL_HIFIPLL_CTRL0 0xc0 #define ANACTRL_HIFIPLL_CTRL1 0xc4 #define ANACTRL_HIFIPLL_CTRL2 0xc8 #define ANACTRL_HIFIPLL_CTRL3 0xcc #define ANACTRL_HIFIPLL_CTRL4 0xd0 #define ANACTRL_HIFIPLL_STS 0xd4 -#define ANACTRL_AUDDDS_CTRL0 0x100 -#define ANACTRL_AUDDDS_CTRL1 0x104 -#define ANACTRL_AUDDDS_CTRL2 0x108 -#define ANACTRL_AUDDDS_CTRL3 0x10c -#define ANACTRL_AUDDDS_CTRL4 0x110 -#define ANACTRL_AUDDDS_STS 0x114 -#define ANACTRL_MISCTOP_CTRL0 0x140 -#define ANACTRL_POR_CNTL 0x188 /* * CLKID index values @@ -53,4 +44,16 @@ /* include the CLKIDs that have been made part of the DT binding */ #include +/** + * struct meson_a1_pll_data - A1 PLL state + * @base: Basic CLK PLL state + * @current_en: Enable or disable the PLL self-adaption current module + * @l_detect: Enable or disable the lock detect module + */ +struct meson_a1_pll_data { + struct meson_clk_pll_data base; + struct parm current_en; + struct parm l_detect; +}; + #endif /* __A1_PLL_H */ From patchwork Thu Dec 1 22:57:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Rokosov X-Patchwork-Id: 28582 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp529265wrr; Thu, 1 Dec 2022 15:01:16 -0800 (PST) X-Google-Smtp-Source: AA0mqf4rXVXWb/M6XEgxaOmbPRzwl2u8SoULfz5r0DpwCCv4VcsfrJXbdiDsHXoIvbR4LGAP8JDC X-Received: by 2002:a17:90a:7d0f:b0:219:7ec6:8f3f with SMTP id g15-20020a17090a7d0f00b002197ec68f3fmr3911351pjl.103.1669935676400; Thu, 01 Dec 2022 15:01:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669935676; cv=none; d=google.com; s=arc-20160816; b=rykJARJ7o/v6FHDHRN2dtd8BS66+nHWmMp1uK3Q+vQ9H0QLfWFixb1RnCZkyewEbRl 50lreTl6neSWXSeuN9oKHbqA16ZRGm23Nd7VUeKMqFxj0HLNb1K1pktW4Nrs8ehUPnT+ aPntv1p6GZ/gilsD8lUpFf2hJvrut1yF/Its4Ih2AQRFxBMQYPbAOcBpoYKqTBwPjndg SXtJGMxwXcJ8ZQnW1XFWJ2LGwrpXWDe666y+k7S9NIZtBGbRUGPIolXfwU2OvWP3HoNm qtL2OuECh/NOuPsjb7SteHBAwI6iqnTIuwglbbQZW1hFaJQNxrU7eC9sjqc8xP3axHwP gwrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=8WuFTtlyje+RAPuOwRdLKN6aHl8n49XuWh4hJVbyhvE=; b=uJUA462lLYRdHGn46fF+2VjAFS+aMh0bKxHIDo2f1qi7FdVheBW8QO97+vkjuMGAP8 0QOEAcYspdvS6JEqU5ePpeBbZP6kJ7hzJEHdxM/MCzhREjdN1E0x+Xi+ZHV5A2N0suX+ VNHGR85KXmTSREQQbTxTA4KPJ2FcNLyNlZN2HMp3RmYUuoaOH8wHuDu94Y1sC3+4gNG6 a4aOADDHdMxkgrBVe9XIYFwquOH505DqPNY2P6UNq7ndDaWhMnLnQ0jr55KAt9xX+XI6 zsCen7/g6lPFMtUiqkmUQHGE/WiFxO1PZ5k8YI7VgrQjzfle2V3pZ+fIm273MiNYsqQe myAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sberdevices.ru header.s=mail header.b=qdLxOm4e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=sberdevices.ru Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Dmitry Rokosov --- .../bindings/clock/amlogic,a1-pll-clkc.yaml | 27 ++++++++++++------- MAINTAINERS | 1 + 2 files changed, 18 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml index d67250fbeece..83f98a73c04e 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/amlogic,a1-pll-clkc.yaml#" +$id: "http://devicetree.org/schemas/clock/amlogic,a1-pll-clkc.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: Amlogic Meson A/C serials PLL Clock Control Unit Device Tree Bindings @@ -10,6 +10,7 @@ maintainers: - Neil Armstrong - Jerome Brunet - Jian Hu + - Dmitry Rokosov properties: compatible: @@ -23,8 +24,8 @@ properties: clocks: items: - - description: input xtal_fixpll - - description: input xtal_hifipll + - description: input xtal_fixpll + - description: input xtal_hifipll clock-names: items: @@ -42,11 +43,17 @@ additionalProperties: false examples: - | - clkc_pll: pll-clock-controller@7c80 { - compatible = "amlogic,a1-pll-clkc"; - reg = <0 0x7c80 0 0x18c>; - #clock-cells = <1>; - clocks = <&clkc_periphs 1>, - <&clkc_periphs 4>; - clock-names = "xtal_fixpll", "xtal_hifipll"; + #include + apb { + #address-cells = <2>; + #size-cells = <2>; + + clkc_pll: pll-clock-controller@7c80 { + compatible = "amlogic,a1-pll-clkc"; + reg = <0 0x7c80 0 0x18c>; + #clock-cells = <1>; + clocks = <&clkc_periphs CLKID_XTAL_FIXPLL>, + <&clkc_periphs CLKID_XTAL_HIFIPLL>; + clock-names = "xtal_fixpll", "xtal_hifipll"; + }; }; diff --git a/MAINTAINERS b/MAINTAINERS index e04d944005ba..a02d81edeb4b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1837,6 +1837,7 @@ L: linux-amlogic@lists.infradead.org S: Maintained F: Documentation/devicetree/bindings/clock/amlogic* F: drivers/clk/meson/ +F: include/dt-bindings/clock/a1* F: include/dt-bindings/clock/gxbb* F: include/dt-bindings/clock/meson* From patchwork Thu Dec 1 22:57:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Rokosov X-Patchwork-Id: 28585 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp529873wrr; Thu, 1 Dec 2022 15:02:19 -0800 (PST) X-Google-Smtp-Source: AA0mqf4dn0+W1fj6fZvUTTmyIHJh8sR06RX+u7XlVuMBCaNoQBK3YgZ1J+CCMhPno+rSAjI483cj X-Received: by 2002:a63:fa41:0:b0:476:e84c:ab65 with SMTP id g1-20020a63fa41000000b00476e84cab65mr44076394pgk.513.1669935739041; Thu, 01 Dec 2022 15:02:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669935739; cv=none; d=google.com; s=arc-20160816; b=j31rLRwMghrRDapcBBzkkg9x0JLmfwlW7TqJlNiRoR1sRtYV5JHlpOviXBX8N8gxYM Q8PuZNnOtuZ5is3/jJcIBIHSTnbbD/oNMShKFe3C9Sc12lrRxPU5D1dsrYCZqS70wo4p 5pJuztTmTfaU2h7Ih3OL/nogs96gGMYLb3t5jfu0Tsaujgum/+MQXDm8b674R4UciKOA SjLZDlScaILdQzuANELEb1lQCrZQH9BC16zP0SrmkemQE9fkvtOnHhlHVUr3MGZtKp57 fO3pBJCxOwX1ynNFpdhkp8fYZbcWFYB/oyUO+e78lhvklGG0laaUe1p39FUI+mNQyosu 2wQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Y12T2sON/JzfwnBJOAk/5DddjeRob0ccjHbxS2nX4ek=; b=NR/P20D/e1DHC+SIdzZasVlQw7lqnYPoAbEkwd6ZQu+0iW4l9OTqRKhHDgywL/GSP0 fhvIgcuN39s2s1m+a2fLYGJ+bIs1S2ZioZ9sbyCUbD6ggMr3VOdRCrSh3vH2btwtUR5y ewuIYzxPVWgkQI3cj7J4xQ+h+uXoAt+H7Mg7admAlMOjiQ+/ImEKYQIgRwQIrhukF/iU j+Wz9LPhRginAXcMPn565z6xQemVueAShTdqVQ1dBS6RXQ4lltErg+qt85QygVKzpdgJ 4um6ENSZPy6kXXvV6jQXNDebPLn1O0m/5Ww2iF55UNSEfS7h30KnQp4Hgdqd4RNFXfeI yB4A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sberdevices.ru header.s=mail header.b=Iw1fA9Je; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=sberdevices.ru Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id b11-20020a170903228b00b00188ef2314b2si6377878plh.79.2022.12.01.15.02.05; Thu, 01 Dec 2022 15:02:19 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@sberdevices.ru header.s=mail header.b=Iw1fA9Je; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=sberdevices.ru Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231575AbiLAW6g (ORCPT + 99 others); Thu, 1 Dec 2022 17:58:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51066 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231687AbiLAW5m (ORCPT ); Thu, 1 Dec 2022 17:57:42 -0500 Received: from mx.sberdevices.ru (mx.sberdevices.ru [45.89.227.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9C55A459; Thu, 1 Dec 2022 14:57:38 -0800 (PST) Received: from s-lin-edge02.sberdevices.ru (localhost [127.0.0.1]) by mx.sberdevices.ru (Postfix) with ESMTP id E10425FD13; Fri, 2 Dec 2022 01:57:36 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sberdevices.ru; s=mail; t=1669935456; bh=Y12T2sON/JzfwnBJOAk/5DddjeRob0ccjHbxS2nX4ek=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type; b=Iw1fA9Jef0yMmREm4KuRWfc59Byy9T5u73vF7jxviZ9w1Frx67ixb8axLKaoAU+rV iXIJ5b8ZdUDJsxvKiAeQqttOSUpTgkVmjtNdtAvEL8BQHhNWf4N2EqPf07W2j7eT5a anH/jF5mtrq8sZBZd1jNFc6RDU+dA31fLkT1Y73b4MkRQ5kgvVd/Oyw+YmTQVnA4tN VL4QiHlo+/efxrzxKUtEvDVQ0Dt1LwXsnA8DpIPYj4XPHaQ1qobyJh1H4Br50Aw2a+ qxPuuWqSTnz2lk6mzWl4HBA0C2pXMOCwGa1EzEXOFMubTPMeigTbSV7nHb3/k0gYrk WkjvVWMPWBHwA== Received: from S-MS-EXCH01.sberdevices.ru (S-MS-EXCH01.sberdevices.ru [172.16.1.4]) by mx.sberdevices.ru (Postfix) with ESMTP; Fri, 2 Dec 2022 01:57:36 +0300 (MSK) From: Dmitry Rokosov To: , , , , , , , CC: , , , , , , , , Dmitry Rokosov Subject: [PATCH v8 09/11] clk: meson: redesign A1 Peripherals CLK controller Date: Fri, 2 Dec 2022 01:57:01 +0300 Message-ID: <20221201225703.6507-10-ddrokosov@sberdevices.ru> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20221201225703.6507-1-ddrokosov@sberdevices.ru> References: <20221201225703.6507-1-ddrokosov@sberdevices.ru> MIME-Version: 1.0 X-Originating-IP: [172.16.1.6] X-ClientProxiedBy: S-MS-EXCH02.sberdevices.ru (172.16.1.5) To S-MS-EXCH01.sberdevices.ru (172.16.1.4) X-KSMG-Rule-ID: 4 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Status: not scanned, disabled by settings X-KSMG-AntiSpam-Interceptor-Info: not scanned X-KSMG-AntiPhishing: not scanned, disabled by settings X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 1.1.2.30, bases: 2022/12/01 20:49:00 #20634374 X-KSMG-AntiVirus-Status: Clean, skipped X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751054537387225684?= X-GMAIL-MSGID: =?utf-8?q?1751054537387225684?= Summary changes: - fixed up clk_summary kernel panic due to missing a1_pad_ctrl clk_regmap definition - supported meson-a1-clkc common driver - aligned CLKID-related definitions with CLKID list from order perspective to remove holes and permutations - corrected Kconfig dependencies and types - provided correct MODULE_AUTHORs() and MODULE_LICENSE() - optimized and fix up some clock relationships and parents references - removed unused register offset definitions Signed-off-by: Dmitry Rokosov --- drivers/clk/meson/Kconfig | 7 +- drivers/clk/meson/a1.c | 591 ++++++++++++++++++-------------------- drivers/clk/meson/a1.h | 16 +- 3 files changed, 292 insertions(+), 322 deletions(-) diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index deb273673ec1..cabe63bf23f5 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -114,13 +114,14 @@ config COMMON_CLK_A1_PLL aka a1. Say Y if you want PLL to work. config COMMON_CLK_A1 - bool - depends on ARCH_MESON + tristate "Meson A1 SoC clock controller support" + depends on ARM64 select COMMON_CLK_MESON_DUALDIV select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_A1_CLKC help Support for the Peripheral clock controller on Amlogic A113L device, - aka a1. Say Y if you want Peripherals to work. + aka a1. Say Y if you want clock peripherals controller to work. config COMMON_CLK_G12A tristate "G12 and SM1 SoC clock controllers support" diff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c index 2cf20ae1db75..c9b7f09823f8 100644 --- a/drivers/clk/meson/a1.c +++ b/drivers/clk/meson/a1.c @@ -2,6 +2,9 @@ /* * Copyright (c) 2019 Amlogic, Inc. All rights reserved. * Author: Jian Hu + * + * Copyright (c) 2022, SberDevices. All Rights Reserved. + * Author: Dmitry Rokosov */ #include @@ -10,6 +13,7 @@ #include "a1.h" #include "clk-dualdiv.h" #include "clk-regmap.h" +#include "meson-a1-clkc.h" static struct clk_regmap a1_xtal_clktree = { .data = &(struct clk_regmap_gate_data){ @@ -116,11 +120,128 @@ static struct clk_regmap a1_xtal_dds = { }, }; +static struct clk_regmap a1_rtc_32k_clkin = { + .data = &(struct clk_regmap_gate_data){ + .offset = RTC_BY_OSCIN_CTRL0, + .bit_idx = 31, + }, + .hw.init = &(struct clk_init_data) { + .name = "rtc_32k_clkin", + .ops = &clk_regmap_gate_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + }, + .num_parents = 1, + }, +}; + +static const struct meson_clk_dualdiv_param a1_32k_div_table[] = { + { + .dual = 1, + .n1 = 733, + .m1 = 8, + .n2 = 732, + .m2 = 11, + }, + {} +}; + +static struct clk_regmap a1_rtc_32k_div = { + .data = &(struct meson_clk_dualdiv_data){ + .n1 = { + .reg_off = RTC_BY_OSCIN_CTRL0, + .shift = 0, + .width = 12, + }, + .n2 = { + .reg_off = RTC_BY_OSCIN_CTRL0, + .shift = 12, + .width = 12, + }, + .m1 = { + .reg_off = RTC_BY_OSCIN_CTRL1, + .shift = 0, + .width = 12, + }, + .m2 = { + .reg_off = RTC_BY_OSCIN_CTRL1, + .shift = 12, + .width = 12, + }, + .dual = { + .reg_off = RTC_BY_OSCIN_CTRL0, + .shift = 28, + .width = 1, + }, + .table = a1_32k_div_table, + }, + .hw.init = &(struct clk_init_data){ + .name = "rtc_32k_div", + .ops = &meson_clk_dualdiv_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_rtc_32k_clkin.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap a1_rtc_32k_xtal = { + .data = &(struct clk_regmap_gate_data){ + .offset = RTC_BY_OSCIN_CTRL1, + .bit_idx = 24, + }, + .hw.init = &(struct clk_init_data) { + .name = "rtc_32k_xtal", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_rtc_32k_clkin.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap a1_rtc_32k_sel = { + .data = &(struct clk_regmap_mux_data) { + .offset = RTC_CTRL, + .mask = 0x3, + .shift = 0, + .flags = CLK_MUX_ROUND_CLOSEST, + }, + .hw.init = &(struct clk_init_data){ + .name = "rtc_32k_sel", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_rtc_32k_xtal.hw, + &a1_rtc_32k_div.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +struct clk_regmap a1_rtc_clk = { + .data = &(struct clk_regmap_gate_data){ + .offset = RTC_BY_OSCIN_CTRL0, + .bit_idx = 30, + }, + .hw.init = &(struct clk_init_data){ + .name = "rtc_clk", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &a1_rtc_32k_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static u32 mux_table_sys_clk[] = { 0, 1, 2, 3, 7 }; static const struct clk_parent_data sys_clk_parents[] = { { .fw_name = "xtal" }, { .fw_name = "fclk_div2" }, { .fw_name = "fclk_div3" }, { .fw_name = "fclk_div5" }, + { .hw = &a1_rtc_clk.hw }, }; static struct clk_regmap a1_sys_b_sel = { @@ -128,6 +249,7 @@ static struct clk_regmap a1_sys_b_sel = { .offset = SYS_CLK_CTRL0, .mask = 0x7, .shift = 26, + .table = mux_table_sys_clk, }, .hw.init = &(struct clk_init_data){ .name = "sys_b_sel", @@ -175,6 +297,7 @@ static struct clk_regmap a1_sys_a_sel = { .offset = SYS_CLK_CTRL0, .mask = 0x7, .shift = 10, + .table = mux_table_sys_clk, }, .hw.init = &(struct clk_init_data){ .name = "sys_a_sel", @@ -227,7 +350,8 @@ static struct clk_regmap a1_sys_clk = { .name = "sys_clk", .ops = &clk_regmap_mux_ro_ops, .parent_hws = (const struct clk_hw *[]) { - &a1_sys_a.hw, &a1_sys_b.hw, + &a1_sys_a.hw, + &a1_sys_b.hw, }, .num_parents = 2, /* @@ -243,121 +367,6 @@ static struct clk_regmap a1_sys_clk = { }, }; -static struct clk_regmap a1_rtc_32k_clkin = { - .data = &(struct clk_regmap_gate_data){ - .offset = RTC_BY_OSCIN_CTRL0, - .bit_idx = 31, - }, - .hw.init = &(struct clk_init_data) { - .name = "rtc_32k_clkin", - .ops = &clk_regmap_gate_ops, - .parent_data = &(const struct clk_parent_data) { - .fw_name = "xtal", - }, - .num_parents = 1, - }, -}; - -static const struct meson_clk_dualdiv_param a1_32k_div_table[] = { - { - .dual = 1, - .n1 = 733, - .m1 = 8, - .n2 = 732, - .m2 = 11, - }, - {} -}; - -static struct clk_regmap a1_rtc_32k_div = { - .data = &(struct meson_clk_dualdiv_data){ - .n1 = { - .reg_off = RTC_BY_OSCIN_CTRL0, - .shift = 0, - .width = 12, - }, - .n2 = { - .reg_off = RTC_BY_OSCIN_CTRL0, - .shift = 12, - .width = 12, - }, - .m1 = { - .reg_off = RTC_BY_OSCIN_CTRL1, - .shift = 0, - .width = 12, - }, - .m2 = { - .reg_off = RTC_BY_OSCIN_CTRL1, - .shift = 12, - .width = 12, - }, - .dual = { - .reg_off = RTC_BY_OSCIN_CTRL0, - .shift = 28, - .width = 1, - }, - .table = a1_32k_div_table, - }, - .hw.init = &(struct clk_init_data){ - .name = "rtc_32k_div", - .ops = &meson_clk_dualdiv_ops, - .parent_hws = (const struct clk_hw *[]) { - &a1_rtc_32k_clkin.hw - }, - .num_parents = 1, - }, -}; - -static struct clk_regmap a1_rtc_32k_xtal = { - .data = &(struct clk_regmap_gate_data){ - .offset = RTC_BY_OSCIN_CTRL1, - .bit_idx = 24, - }, - .hw.init = &(struct clk_init_data) { - .name = "rtc_32k_xtal", - .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &a1_rtc_32k_clkin.hw - }, - .num_parents = 1, - }, -}; - -static struct clk_regmap a1_rtc_32k_sel = { - .data = &(struct clk_regmap_mux_data) { - .offset = RTC_CTRL, - .mask = 0x3, - .shift = 0, - .flags = CLK_MUX_ROUND_CLOSEST, - }, - .hw.init = &(struct clk_init_data){ - .name = "rtc_32k_sel", - .ops = &clk_regmap_mux_ops, - .parent_hws = (const struct clk_hw *[]) { - &a1_rtc_32k_xtal.hw, - &a1_rtc_32k_div.hw, - }, - .num_parents = 2, - .flags = CLK_SET_RATE_PARENT, - }, -}; - -struct clk_regmap a1_rtc_clk = { - .data = &(struct clk_regmap_gate_data){ - .offset = RTC_BY_OSCIN_CTRL0, - .bit_idx = 30, - }, - .hw.init = &(struct clk_init_data){ - .name = "rtc_clk", - .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &a1_rtc_32k_sel.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - }, -}; - static u32 mux_table_dsp_ab[] = { 0, 1, 2, 3, 4, 7 }; static const struct clk_parent_data dsp_ab_clk_parent_data[] = { { .fw_name = "xtal", }, @@ -475,9 +484,9 @@ static struct clk_regmap a1_dspa_sel = { .hw.init = &(struct clk_init_data){ .name = "dspa_sel", .ops = &clk_regmap_mux_ops, - .parent_data = (const struct clk_parent_data []) { - { .hw = &a1_dspa_a.hw }, - { .hw = &a1_dspa_b.hw }, + .parent_hws = (const struct clk_hw *[]) { + &a1_dspa_a.hw, + &a1_dspa_b.hw, }, .num_parents = 2, .flags = CLK_SET_RATE_PARENT, @@ -624,7 +633,8 @@ static struct clk_regmap a1_dspb_sel = { .name = "dspb_sel", .ops = &clk_regmap_mux_ops, .parent_hws = (const struct clk_hw *[]) { - &a1_dspb_a.hw, &a1_dspb_b.hw, + &a1_dspb_a.hw, + &a1_dspb_b.hw, }, .num_parents = 2, .flags = CLK_SET_RATE_PARENT, @@ -852,6 +862,12 @@ static struct clk_regmap a1_saradc_clk = { }, }; +static const struct clk_parent_data pwm_abcd_parents[] = { + { .fw_name = "xtal", }, + { .hw = &a1_sys_clk.hw }, + { .hw = &a1_rtc_clk.hw }, +}; + static struct clk_regmap a1_pwm_a_sel = { .data = &(struct clk_regmap_mux_data){ .offset = PWM_CLK_AB_CTRL, @@ -861,11 +877,8 @@ static struct clk_regmap a1_pwm_a_sel = { .hw.init = &(struct clk_init_data){ .name = "pwm_a_sel", .ops = &clk_regmap_mux_ops, - .parent_data = (const struct clk_parent_data []) { - { .fw_name = "xtal", }, - { .hw = &a1_sys_clk.hw, }, - }, - .num_parents = 2, + .parent_data = pwm_abcd_parents, + .num_parents = ARRAY_SIZE(pwm_abcd_parents), }, }; @@ -918,11 +931,8 @@ static struct clk_regmap a1_pwm_b_sel = { .hw.init = &(struct clk_init_data){ .name = "pwm_b_sel", .ops = &clk_regmap_mux_ops, - .parent_data = (const struct clk_parent_data []) { - { .fw_name = "xtal", }, - { .hw = &a1_sys_clk.hw, }, - }, - .num_parents = 2, + .parent_data = pwm_abcd_parents, + .num_parents = ARRAY_SIZE(pwm_abcd_parents), }, }; @@ -968,11 +978,8 @@ static struct clk_regmap a1_pwm_c_sel = { .hw.init = &(struct clk_init_data){ .name = "pwm_c_sel", .ops = &clk_regmap_mux_ops, - .parent_data = (const struct clk_parent_data []) { - { .fw_name = "xtal", }, - { .hw = &a1_sys_clk.hw, }, - }, - .num_parents = 2, + .parent_data = pwm_abcd_parents, + .num_parents = ARRAY_SIZE(pwm_abcd_parents), }, }; @@ -1018,11 +1025,8 @@ static struct clk_regmap a1_pwm_d_sel = { .hw.init = &(struct clk_init_data){ .name = "pwm_d_sel", .ops = &clk_regmap_mux_ops, - .parent_data = (const struct clk_parent_data []) { - { .fw_name = "xtal", }, - { .hw = &a1_sys_clk.hw, }, - }, - .num_parents = 2, + .parent_data = pwm_abcd_parents, + .num_parents = ARRAY_SIZE(pwm_abcd_parents), }, }; @@ -1059,7 +1063,7 @@ static struct clk_regmap a1_pwm_d = { }, }; -static const struct clk_parent_data pwm_ef_parent_data[] = { +static const struct clk_parent_data pwm_ef_parents[] = { { .fw_name = "xtal", }, { .hw = &a1_sys_clk.hw }, { .fw_name = "fclk_div5", }, @@ -1075,8 +1079,8 @@ static struct clk_regmap a1_pwm_e_sel = { .hw.init = &(struct clk_init_data){ .name = "pwm_e_sel", .ops = &clk_regmap_mux_ops, - .parent_data = pwm_ef_parent_data, - .num_parents = ARRAY_SIZE(pwm_ef_parent_data), + .parent_data = pwm_ef_parents, + .num_parents = ARRAY_SIZE(pwm_ef_parents), }, }; @@ -1122,8 +1126,8 @@ static struct clk_regmap a1_pwm_f_sel = { .hw.init = &(struct clk_init_data){ .name = "pwm_f_sel", .ops = &clk_regmap_mux_ops, - .parent_data = pwm_ef_parent_data, - .num_parents = ARRAY_SIZE(pwm_ef_parent_data), + .parent_data = pwm_ef_parents, + .num_parents = ARRAY_SIZE(pwm_ef_parents), }, }; @@ -1169,7 +1173,7 @@ static struct clk_regmap a1_pwm_f = { * --------------------|/ * 24M */ -static const struct clk_parent_data spicc_parents[] = { +static const struct clk_parent_data spicc_spifc_parents[] = { { .fw_name = "fclk_div2"}, { .fw_name = "fclk_div3"}, { .fw_name = "fclk_div5"}, @@ -1185,8 +1189,8 @@ static struct clk_regmap a1_spicc_sel = { .hw.init = &(struct clk_init_data){ .name = "spicc_sel", .ops = &clk_regmap_mux_ops, - .parent_data = spicc_parents, - .num_parents = 4, + .parent_data = spicc_spifc_parents, + .num_parents = ARRAY_SIZE(spicc_spifc_parents), }, }; @@ -1282,9 +1286,8 @@ static struct clk_regmap a1_spifc_sel = { .hw.init = &(struct clk_init_data){ .name = "spifc_sel", .ops = &clk_regmap_mux_ops, - /* the same parent with spicc */ - .parent_data = spicc_parents, - .num_parents = 4, + .parent_data = spicc_spifc_parents, + .num_parents = ARRAY_SIZE(spicc_spifc_parents), }, }; @@ -1339,7 +1342,7 @@ static struct clk_regmap a1_spifc = { }, }; -static const struct clk_parent_data usb_bus_parent_data[] = { +static const struct clk_parent_data usb_bus_parents[] = { { .fw_name = "xtal", }, { .hw = &a1_sys_clk.hw }, { .fw_name = "fclk_div3", }, @@ -1355,8 +1358,8 @@ static struct clk_regmap a1_usb_bus_sel = { .hw.init = &(struct clk_init_data){ .name = "usb_bus_sel", .ops = &clk_regmap_mux_ops, - .parent_data = usb_bus_parent_data, - .num_parents = ARRAY_SIZE(usb_bus_parent_data), + .parent_data = usb_bus_parents, + .num_parents = ARRAY_SIZE(usb_bus_parents), .flags = CLK_SET_RATE_PARENT, }, }; @@ -1394,7 +1397,7 @@ static struct clk_regmap a1_usb_bus = { }, }; -static const struct clk_parent_data sd_emmc_parents[] = { +static const struct clk_parent_data sd_emmc_psram_dmc_parents[] = { { .fw_name = "fclk_div2", }, { .fw_name = "fclk_div3", }, { .fw_name = "fclk_div5", }, @@ -1410,8 +1413,8 @@ static struct clk_regmap a1_sd_emmc_sel = { .hw.init = &(struct clk_init_data){ .name = "sd_emmc_sel", .ops = &clk_regmap_mux_ops, - .parent_data = sd_emmc_parents, - .num_parents = 4, + .parent_data = sd_emmc_psram_dmc_parents, + .num_parents = ARRAY_SIZE(sd_emmc_psram_dmc_parents), }, }; @@ -1475,9 +1478,8 @@ static struct clk_regmap a1_psram_sel = { .hw.init = &(struct clk_init_data){ .name = "psram_sel", .ops = &clk_regmap_mux_ops, - /* the same parent with sd_emmc */ - .parent_data = sd_emmc_parents, - .num_parents = 4, + .parent_data = sd_emmc_psram_dmc_parents, + .num_parents = ARRAY_SIZE(sd_emmc_psram_dmc_parents), }, }; @@ -1541,8 +1543,8 @@ static struct clk_regmap a1_dmc_sel = { .hw.init = &(struct clk_init_data){ .name = "dmc_sel", .ops = &clk_regmap_mux_ops, - .parent_data = sd_emmc_parents, - .num_parents = 4, + .parent_data = sd_emmc_psram_dmc_parents, + .num_parents = ARRAY_SIZE(sd_emmc_psram_dmc_parents), }, }; @@ -1873,13 +1875,6 @@ static MESON_GATE(a1_prod_i2c, AXI_CLK_EN, 12); /* Array of all clocks provided by this provider */ static struct clk_hw_onecell_data a1_periphs_hw_onecell_data = { .hws = { - [CLKID_SYS_B_SEL] = &a1_sys_b_sel.hw, - [CLKID_SYS_B_DIV] = &a1_sys_b_div.hw, - [CLKID_SYS_B] = &a1_sys_b.hw, - [CLKID_SYS_A_SEL] = &a1_sys_a_sel.hw, - [CLKID_SYS_A_DIV] = &a1_sys_a_div.hw, - [CLKID_SYS_A] = &a1_sys_a.hw, - [CLKID_SYS_CLK] = &a1_sys_clk.hw, [CLKID_XTAL_CLKTREE] = &a1_xtal_clktree.hw, [CLKID_XTAL_FIXPLL] = &a1_xtal_fixpll.hw, [CLKID_XTAL_USB_PHY] = &a1_xtal_usb_phy.hw, @@ -1887,6 +1882,7 @@ static struct clk_hw_onecell_data a1_periphs_hw_onecell_data = { [CLKID_XTAL_HIFIPLL] = &a1_xtal_hifipll.hw, [CLKID_XTAL_SYSPLL] = &a1_xtal_syspll.hw, [CLKID_XTAL_DDS] = &a1_xtal_dds.hw, + [CLKID_SYS_CLK] = &a1_sys_clk.hw, [CLKID_CLKTREE] = &a1_clk_tree.hw, [CLKID_RESET_CTRL] = &a1_reset_ctrl.hw, [CLKID_ANALOG_CTRL] = &a1_analog_ctrl.hw, @@ -1940,93 +1936,99 @@ static struct clk_hw_onecell_data a1_periphs_hw_onecell_data = { [CLKID_CPU_CTRL] = &a1_cpu_ctrl.hw, [CLKID_ROM] = &a1_rom.hw, [CLKID_PROC_I2C] = &a1_prod_i2c.hw, + [CLKID_DSPA_SEL] = &a1_dspa_sel.hw, + [CLKID_DSPB_SEL] = &a1_dspb_sel.hw, + [CLKID_DSPA_EN] = &a1_dspa_en.hw, + [CLKID_DSPA_EN_NIC] = &a1_dspa_en_nic.hw, + [CLKID_DSPB_EN] = &a1_dspb_en.hw, + [CLKID_DSPB_EN_NIC] = &a1_dspb_en_nic.hw, + [CLKID_RTC_CLK] = &a1_rtc_clk.hw, + [CLKID_CECA_32K] = &a1_ceca_32k_clkout.hw, + [CLKID_CECB_32K] = &a1_cecb_32k_clkout.hw, + [CLKID_24M] = &a1_24m.hw, + [CLKID_12M] = &a1_12m.hw, + [CLKID_FCLK_DIV2_DIVN] = &a1_fclk_div2_divn.hw, + [CLKID_GEN] = &a1_gen.hw, + [CLKID_SARADC_SEL] = &a1_saradc_sel.hw, + [CLKID_SARADC_CLK] = &a1_saradc_clk.hw, + [CLKID_PWM_A] = &a1_pwm_a.hw, + [CLKID_PWM_B] = &a1_pwm_b.hw, + [CLKID_PWM_C] = &a1_pwm_c.hw, + [CLKID_PWM_D] = &a1_pwm_d.hw, + [CLKID_PWM_E] = &a1_pwm_e.hw, + [CLKID_PWM_F] = &a1_pwm_f.hw, + [CLKID_SPICC] = &a1_spicc.hw, + [CLKID_TS] = &a1_ts.hw, + [CLKID_SPIFC] = &a1_spifc.hw, + [CLKID_USB_BUS] = &a1_usb_bus.hw, + [CLKID_SD_EMMC] = &a1_sd_emmc.hw, + [CLKID_PSRAM] = &a1_psram.hw, + [CLKID_DMC] = &a1_dmc.hw, + [CLKID_SYS_A_SEL] = &a1_sys_a_sel.hw, + [CLKID_SYS_A_DIV] = &a1_sys_a_div.hw, + [CLKID_SYS_A] = &a1_sys_a.hw, + [CLKID_SYS_B_SEL] = &a1_sys_b_sel.hw, + [CLKID_SYS_B_DIV] = &a1_sys_b_div.hw, + [CLKID_SYS_B] = &a1_sys_b.hw, [CLKID_DSPA_A_SEL] = &a1_dspa_a_sel.hw, [CLKID_DSPA_A_DIV] = &a1_dspa_a_div.hw, [CLKID_DSPA_A] = &a1_dspa_a.hw, [CLKID_DSPA_B_SEL] = &a1_dspa_b_sel.hw, [CLKID_DSPA_B_DIV] = &a1_dspa_b_div.hw, [CLKID_DSPA_B] = &a1_dspa_b.hw, - [CLKID_DSPA_SEL] = &a1_dspa_sel.hw, [CLKID_DSPB_A_SEL] = &a1_dspb_a_sel.hw, [CLKID_DSPB_A_DIV] = &a1_dspb_a_div.hw, [CLKID_DSPB_A] = &a1_dspb_a.hw, [CLKID_DSPB_B_SEL] = &a1_dspb_b_sel.hw, [CLKID_DSPB_B_DIV] = &a1_dspb_b_div.hw, [CLKID_DSPB_B] = &a1_dspb_b.hw, - [CLKID_DSPB_SEL] = &a1_dspb_sel.hw, - [CLKID_DSPA_EN] = &a1_dspa_en.hw, - [CLKID_DSPA_EN_NIC] = &a1_dspa_en_nic.hw, - [CLKID_DSPB_EN] = &a1_dspb_en.hw, - [CLKID_DSPB_EN_NIC] = &a1_dspb_en_nic.hw, - [CLKID_24M] = &a1_24m.hw, - [CLKID_24M_DIV2] = &a1_24m_div2.hw, - [CLKID_12M] = &a1_12m.hw, + [CLKID_RTC_32K_CLKIN] = &a1_rtc_32k_clkin.hw, + [CLKID_RTC_32K_DIV] = &a1_rtc_32k_div.hw, + [CLKID_RTC_32K_XTAL] = &a1_rtc_32k_xtal.hw, + [CLKID_RTC_32K_SEL] = &a1_rtc_32k_sel.hw, + [CLKID_CECB_32K_CLKIN] = &a1_cecb_32k_clkin.hw, + [CLKID_CECB_32K_DIV] = &a1_cecb_32k_div.hw, + [CLKID_CECB_32K_SEL_PRE] = &a1_cecb_32k_sel_pre.hw, + [CLKID_CECB_32K_SEL] = &a1_cecb_32k_sel.hw, + [CLKID_CECA_32K_CLKIN] = &a1_ceca_32k_clkin.hw, + [CLKID_CECA_32K_DIV] = &a1_ceca_32k_div.hw, + [CLKID_CECA_32K_SEL_PRE] = &a1_ceca_32k_sel_pre.hw, + [CLKID_CECA_32K_SEL] = &a1_ceca_32k_sel.hw, [CLKID_DIV2_PRE] = &a1_fclk_div2_divn_pre.hw, - [CLKID_FCLK_DIV2_DIVN] = &a1_fclk_div2_divn.hw, + [CLKID_24M_DIV2] = &a1_24m_div2.hw, [CLKID_GEN_SEL] = &a1_gen_sel.hw, [CLKID_GEN_DIV] = &a1_gen_div.hw, - [CLKID_GEN] = &a1_gen.hw, - [CLKID_SARADC_SEL] = &a1_saradc_sel.hw, [CLKID_SARADC_DIV] = &a1_saradc_div.hw, - [CLKID_SARADC_CLK] = &a1_saradc_clk.hw, [CLKID_PWM_A_SEL] = &a1_pwm_a_sel.hw, [CLKID_PWM_A_DIV] = &a1_pwm_a_div.hw, - [CLKID_PWM_A] = &a1_pwm_a.hw, [CLKID_PWM_B_SEL] = &a1_pwm_b_sel.hw, [CLKID_PWM_B_DIV] = &a1_pwm_b_div.hw, - [CLKID_PWM_B] = &a1_pwm_b.hw, [CLKID_PWM_C_SEL] = &a1_pwm_c_sel.hw, [CLKID_PWM_C_DIV] = &a1_pwm_c_div.hw, - [CLKID_PWM_C] = &a1_pwm_c.hw, [CLKID_PWM_D_SEL] = &a1_pwm_d_sel.hw, [CLKID_PWM_D_DIV] = &a1_pwm_d_div.hw, - [CLKID_PWM_D] = &a1_pwm_d.hw, [CLKID_PWM_E_SEL] = &a1_pwm_e_sel.hw, [CLKID_PWM_E_DIV] = &a1_pwm_e_div.hw, - [CLKID_PWM_E] = &a1_pwm_e.hw, [CLKID_PWM_F_SEL] = &a1_pwm_f_sel.hw, [CLKID_PWM_F_DIV] = &a1_pwm_f_div.hw, - [CLKID_PWM_F] = &a1_pwm_f.hw, [CLKID_SPICC_SEL] = &a1_spicc_sel.hw, [CLKID_SPICC_DIV] = &a1_spicc_div.hw, [CLKID_SPICC_SEL2] = &a1_spicc_sel2.hw, - [CLKID_SPICC] = &a1_spicc.hw, [CLKID_TS_DIV] = &a1_ts_div.hw, - [CLKID_TS] = &a1_ts.hw, [CLKID_SPIFC_SEL] = &a1_spifc_sel.hw, [CLKID_SPIFC_DIV] = &a1_spifc_div.hw, [CLKID_SPIFC_SEL2] = &a1_spifc_sel2.hw, - [CLKID_SPIFC] = &a1_spifc.hw, [CLKID_USB_BUS_SEL] = &a1_usb_bus_sel.hw, [CLKID_USB_BUS_DIV] = &a1_usb_bus_div.hw, - [CLKID_USB_BUS] = &a1_usb_bus.hw, [CLKID_SD_EMMC_SEL] = &a1_sd_emmc_sel.hw, [CLKID_SD_EMMC_DIV] = &a1_sd_emmc_div.hw, [CLKID_SD_EMMC_SEL2] = &a1_sd_emmc_sel2.hw, - [CLKID_SD_EMMC] = &a1_sd_emmc.hw, [CLKID_PSRAM_SEL] = &a1_psram_sel.hw, [CLKID_PSRAM_DIV] = &a1_psram_div.hw, [CLKID_PSRAM_SEL2] = &a1_psram_sel2.hw, - [CLKID_PSRAM] = &a1_psram.hw, [CLKID_DMC_SEL] = &a1_dmc_sel.hw, [CLKID_DMC_DIV] = &a1_dmc_div.hw, [CLKID_DMC_SEL2] = &a1_dmc_sel2.hw, - [CLKID_DMC] = &a1_dmc.hw, - [CLKID_RTC_32K_CLKIN] = &a1_rtc_32k_clkin.hw, - [CLKID_RTC_32K_DIV] = &a1_rtc_32k_div.hw, - [CLKID_RTC_32K_XTAL] = &a1_rtc_32k_xtal.hw, - [CLKID_RTC_32K_SEL] = &a1_rtc_32k_sel.hw, - [CLKID_RTC_CLK] = &a1_rtc_clk.hw, - [CLKID_CECA_32K_CLKIN] = &a1_ceca_32k_clkin.hw, - [CLKID_CECA_32K_DIV] = &a1_ceca_32k_div.hw, - [CLKID_CECA_32K_SEL_PRE] = &a1_ceca_32k_sel_pre.hw, - [CLKID_CECA_32K_SEL] = &a1_ceca_32k_sel.hw, - [CLKID_CECA_32K] = &a1_ceca_32k_clkout.hw, - [CLKID_CECB_32K_CLKIN] = &a1_cecb_32k_clkin.hw, - [CLKID_CECB_32K_DIV] = &a1_cecb_32k_div.hw, - [CLKID_CECB_32K_SEL_PRE] = &a1_cecb_32k_sel_pre.hw, - [CLKID_CECB_32K_SEL] = &a1_cecb_32k_sel.hw, - [CLKID_CECB_32K] = &a1_cecb_32k_clkout.hw, [NR_CLKS] = NULL, }, .num = NR_CLKS, @@ -2041,10 +2043,12 @@ static struct clk_regmap *const a1_periphs_regmaps[] = { &a1_xtal_hifipll, &a1_xtal_syspll, &a1_xtal_dds, + &a1_sys_clk, &a1_clk_tree, &a1_reset_ctrl, &a1_analog_ctrl, &a1_pwr_ctrl, + &a1_pad_ctrl, &a1_sys_ctrl, &a1_temp_sensor, &a1_am2axi_dev, @@ -2093,157 +2097,126 @@ static struct clk_regmap *const a1_periphs_regmaps[] = { &a1_cpu_ctrl, &a1_rom, &a1_prod_i2c, + &a1_dspa_sel, + &a1_dspb_sel, + &a1_dspa_en, + &a1_dspa_en_nic, + &a1_dspb_en, + &a1_dspb_en_nic, + &a1_rtc_clk, + &a1_ceca_32k_clkout, + &a1_cecb_32k_clkout, + &a1_24m, + &a1_12m, + &a1_fclk_div2_divn, + &a1_gen, + &a1_saradc_sel, + &a1_saradc_clk, + &a1_pwm_a, + &a1_pwm_b, + &a1_pwm_c, + &a1_pwm_d, + &a1_pwm_e, + &a1_pwm_f, + &a1_spicc, + &a1_ts, + &a1_spifc, + &a1_usb_bus, + &a1_sd_emmc, + &a1_psram, + &a1_dmc, + &a1_sys_a_sel, + &a1_sys_a_div, + &a1_sys_a, + &a1_sys_b_sel, + &a1_sys_b_div, + &a1_sys_b, &a1_dspa_a_sel, &a1_dspa_a_div, &a1_dspa_a, &a1_dspa_b_sel, &a1_dspa_b_div, &a1_dspa_b, - &a1_dspa_sel, &a1_dspb_a_sel, &a1_dspb_a_div, &a1_dspb_a, &a1_dspb_b_sel, &a1_dspb_b_div, &a1_dspb_b, - &a1_dspb_sel, - &a1_dspa_en, - &a1_dspa_en_nic, - &a1_dspb_en, - &a1_dspb_en_nic, - &a1_24m, - &a1_12m, + &a1_rtc_32k_clkin, + &a1_rtc_32k_div, + &a1_rtc_32k_xtal, + &a1_rtc_32k_sel, + &a1_cecb_32k_clkin, + &a1_cecb_32k_div, + &a1_cecb_32k_sel_pre, + &a1_cecb_32k_sel, + &a1_ceca_32k_clkin, + &a1_ceca_32k_div, + &a1_ceca_32k_sel_pre, + &a1_ceca_32k_sel, &a1_fclk_div2_divn_pre, - &a1_fclk_div2_divn, &a1_gen_sel, &a1_gen_div, - &a1_gen, - &a1_saradc_sel, &a1_saradc_div, - &a1_saradc_clk, &a1_pwm_a_sel, &a1_pwm_a_div, - &a1_pwm_a, &a1_pwm_b_sel, &a1_pwm_b_div, - &a1_pwm_b, &a1_pwm_c_sel, &a1_pwm_c_div, - &a1_pwm_c, &a1_pwm_d_sel, &a1_pwm_d_div, - &a1_pwm_d, &a1_pwm_e_sel, &a1_pwm_e_div, - &a1_pwm_e, &a1_pwm_f_sel, &a1_pwm_f_div, - &a1_pwm_f, &a1_spicc_sel, &a1_spicc_div, &a1_spicc_sel2, - &a1_spicc, &a1_ts_div, - &a1_ts, &a1_spifc_sel, &a1_spifc_div, &a1_spifc_sel2, - &a1_spifc, &a1_usb_bus_sel, &a1_usb_bus_div, - &a1_usb_bus, &a1_sd_emmc_sel, &a1_sd_emmc_div, &a1_sd_emmc_sel2, - &a1_sd_emmc, &a1_psram_sel, &a1_psram_div, &a1_psram_sel2, - &a1_psram, &a1_dmc_sel, &a1_dmc_div, &a1_dmc_sel2, - &a1_dmc, - &a1_sys_b_sel, - &a1_sys_b_div, - &a1_sys_b, - &a1_sys_a_sel, - &a1_sys_a_div, - &a1_sys_a, - &a1_sys_clk, - &a1_rtc_32k_clkin, - &a1_rtc_32k_div, - &a1_rtc_32k_xtal, - &a1_rtc_32k_sel, - &a1_rtc_clk, - &a1_ceca_32k_clkin, - &a1_ceca_32k_div, - &a1_ceca_32k_sel_pre, - &a1_ceca_32k_sel, - &a1_ceca_32k_clkout, - &a1_cecb_32k_clkin, - &a1_cecb_32k_div, - &a1_cecb_32k_sel_pre, - &a1_cecb_32k_sel, - &a1_cecb_32k_clkout, }; -static struct regmap_config clkc_regmap_config = { - .reg_bits = 32, - .val_bits = 32, - .reg_stride = 4, +static const struct meson_a1_clkc_data a1_periphs_clkc __maybe_unused = { + .hw = &a1_periphs_hw_onecell_data, + .regs = a1_periphs_regmaps, + .num_regs = ARRAY_SIZE(a1_periphs_regmaps), }; -static int meson_a1_periphs_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct resource *res; - void __iomem *base; - struct regmap *map; - int ret, i; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - - base = devm_ioremap_resource(dev, res); - if (IS_ERR(base)) - return PTR_ERR(base); - - map = devm_regmap_init_mmio(dev, base, &clkc_regmap_config); - if (IS_ERR(map)) - return PTR_ERR(map); - - /* Populate regmap for the regmap backed clocks */ - for (i = 0; i < ARRAY_SIZE(a1_periphs_regmaps); i++) - a1_periphs_regmaps[i]->map = map; - - for (i = 0; i < a1_periphs_hw_onecell_data.num; i++) { - /* array might be sparse */ - if (!a1_periphs_hw_onecell_data.hws[i]) - continue; - - ret = devm_clk_hw_register(dev, - a1_periphs_hw_onecell_data.hws[i]); - if (ret) { - dev_err(dev, "Clock registration failed\n"); - return ret; - } - } - - return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, - &a1_periphs_hw_onecell_data); -} - -static const struct of_device_id clkc_match_table[] = { - { .compatible = "amlogic,a1-periphs-clkc", }, - {} +#ifdef CONFIG_OF +static const struct of_device_id a1_periphs_clkc_match_table[] = { + { + .compatible = "amlogic,a1-periphs-clkc", + .data = &a1_periphs_clkc, + }, + {}, }; +MODULE_DEVICE_TABLE(of, a1_periphs_clkc_match_table); +#endif /* CONFIG_OF */ -static struct platform_driver a1_periphs_driver = { - .probe = meson_a1_periphs_probe, - .driver = { - .name = "a1-periphs-clkc", - .of_match_table = clkc_match_table, +static struct platform_driver a1_periphs_clkc_driver = { + .probe = meson_a1_clkc_probe, + .driver = { + .name = "a1-periphs-clkc", + .of_match_table = of_match_ptr(a1_periphs_clkc_match_table), }, }; -builtin_platform_driver(a1_periphs_driver); +module_platform_driver(a1_periphs_clkc_driver); +MODULE_AUTHOR("Jian Hu "); +MODULE_AUTHOR("Dmitry Rokosov "); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/meson/a1.h b/drivers/clk/meson/a1.h index 1ae5e04848d6..94b155e33568 100644 --- a/drivers/clk/meson/a1.h +++ b/drivers/clk/meson/a1.h @@ -1,6 +1,12 @@ /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* + * Amlogic Meson-A1 Peripheral Clock Controller internals + * * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + * Author: Jian Hu + * + * Copyright (c) 2022, SberDevices. All Rights Reserved. + * Author: Dmitry Rokosov */ #ifndef __A1_H @@ -12,7 +18,6 @@ #define RTC_BY_OSCIN_CTRL1 0x8 #define RTC_CTRL 0xc #define SYS_CLK_CTRL0 0x10 -#define AXI_CLK_CTRL0 0x14 #define SYS_CLK_EN0 0x1c #define SYS_CLK_EN1 0x20 #define AXI_CLK_EN 0x24 @@ -22,13 +27,6 @@ #define DSPB_CLK_CTRL0 0x34 #define CLK12_24_CTRL 0x38 #define GEN_CLK_CTRL 0x3c -#define TIMESTAMP_CTRL0 0x40 -#define TIMESTAMP_CTRL1 0x44 -#define TIMESTAMP_CTRL2 0x48 -#define TIMESTAMP_VAL0 0x4c -#define TIMESTAMP_VAL1 0x50 -#define TIMEBASE_CTRL0 0x54 -#define TIMEBASE_CTRL1 0x58 #define SAR_ADC_CLK_CTRL 0xc0 #define PWM_CLK_AB_CTRL 0xc4 #define PWM_CLK_CD_CTRL 0xc8 @@ -44,8 +42,6 @@ #define CECB_CLK_CTRL1 0xf0 #define PSRAM_CLK_CTRL 0xf4 #define DMC_CLK_CTRL 0xf8 -#define FCLK_DIV1_SEL 0xfc -#define TST_CTRL 0x100 #define CLKID_XTAL_CLKTREE 0 #define CLKID_SYS_A_SEL 89 From patchwork Thu Dec 1 22:57:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Rokosov X-Patchwork-Id: 28579 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp528845wrr; Thu, 1 Dec 2022 15:00:24 -0800 (PST) X-Google-Smtp-Source: AA0mqf7HreZQo3UK0/DpjAxm5kFkHE+DkQ78WLR15RJXNEamle6Hz87i3OyHS8FZ6dg+ewq14FXq X-Received: by 2002:a17:906:5055:b0:78d:cdce:bc52 with SMTP id e21-20020a170906505500b0078dcdcebc52mr43601066ejk.469.1669935623922; Thu, 01 Dec 2022 15:00:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669935623; cv=none; d=google.com; s=arc-20160816; b=OPGKuuFOK2+gw4j4zeCmlsk+4P7hGVokPc/EMqf3U3JDYGd8OeLEfeideqwsKBYUVa Fm8qvJwKW5eXhPMG+SqfO1a1CBgE2CSmGanGkCbyRObmHa/4y9xFlWHYpPEes9Khf63B WcnMLAxCOU3+jB0qXJm4aAdP7rusFmtESjjwncQJ+raBFXuEvBef6b5Y0srxNwixgCmI WJdetv5eHIuYv28To+r/o5RD3OqByI+ppg+gQc5AA4/cuNHYE3gn+PKFgslXnvQqROg1 FD3JpFUPFsw3xgerh4p/5e7HDk4ryWD22p7vZNfA3ie7cP5Jlxzc6EHcfW2fc4cCURER 5RfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=su3raxn0OGsgB1AdUJiueQi3w/7b0lMP0lopP7rXXpY=; b=E3BFf65fW8+BnMe2Nd/iKV6co/xPu4gHYbK16O0H03IHNIfRAFeOt9lS5X5PFcC7v8 alIdIlSZIJNXMDYPxorVeHULct992noUe1XJbuOs1FzsQHJ7ss+/qNfeY4A03gggasAS iK4en+yEpwR+uaUmk71iP3mq+oRMxZDL27vUZcjJzOiWIxxSqX1mxdztxQ+d9VOzRoy9 NTZMSfZN0XCinoiszxqwQvehfJ/yYtD/i60Vm4FAt8nQir+p2p2Xi4y3zdyLrIxuqj9u Bz6R2TnTlIYM2n6/QKn4h47PnULg4HMSYfaucJmUR0skofqseCoucsM4fB5IoAtJ+8qu /pWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sberdevices.ru header.s=mail header.b=cNmnNR0W; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=sberdevices.ru Received: from out1.vger.email (out1.vger.email. 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Fri, 2 Dec 2022 01:57:37 +0300 (MSK) From: Dmitry Rokosov To: , , , , , , , CC: , , , , , , , , Dmitry Rokosov Subject: [PATCH v8 10/11] dt-bindings: clock: meson: fixup A1 peripherals clkc dtb_check errors Date: Fri, 2 Dec 2022 01:57:02 +0300 Message-ID: <20221201225703.6507-11-ddrokosov@sberdevices.ru> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20221201225703.6507-1-ddrokosov@sberdevices.ru> References: <20221201225703.6507-1-ddrokosov@sberdevices.ru> MIME-Version: 1.0 X-Originating-IP: [172.16.1.6] X-ClientProxiedBy: S-MS-EXCH02.sberdevices.ru (172.16.1.5) To S-MS-EXCH01.sberdevices.ru (172.16.1.4) X-KSMG-Rule-ID: 4 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Status: not scanned, disabled by settings X-KSMG-AntiSpam-Interceptor-Info: not scanned X-KSMG-AntiPhishing: not scanned, disabled by settings X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 1.1.2.30, bases: 2022/12/01 20:49:00 #20634374 X-KSMG-AntiVirus-Status: Clean, skipped X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751054416671142232?= X-GMAIL-MSGID: =?utf-8?q?1751054416671142232?= During running dtbs_check and dt_binding_check checkers the following problems were found and resolved: - $id is not correct, it has wrong url path - no base offset in the dt node definition - CLKIDs aren't applied by names, just magic int constants there - address and size cells are required for long reg definition - wrong indentations Signed-off-by: Dmitry Rokosov --- .../bindings/clock/amlogic,a1-clkc.yaml | 36 +++++++++++-------- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml index 7729850046cf..b0249ab21466 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml @@ -1,7 +1,7 @@ -#SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/amlogic,a1-clkc.yaml#" +$id: "http://devicetree.org/schemas/clock/amlogic,a1-clkc.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: Amlogic Meson A/C serials Peripheral Clock Control Unit Device Tree Bindings @@ -10,6 +10,7 @@ maintainers: - Neil Armstrong - Jerome Brunet - Jian Hu + - Dmitry Rokosov properties: compatible: @@ -50,16 +51,23 @@ additionalProperties: false examples: - | - clkc_periphs: periphs-clock-controller { - compatible = "amlogic,a1-periphs-clkc"; - reg = <0 0x800 0 0x104>; - #clock-cells = <1>; - clocks = <&clkc_pll 6>, - <&clkc_pll 7>, - <&clkc_pll 8>, - <&clkc_pll 9>, - <&clkc_pll 10>, - <&xtal>; - clock-names = "fclk_div2", "fclk_div3", "fclk_div5", - "fclk_div7", "hifi_pll", "xtal"; + #include + apb { + #address-cells = <2>; + #size-cells = <2>; + + clkc_periphs: periphs-clock-controller@800 { + compatible = "amlogic,a1-periphs-clkc"; + reg = <0 0x800 0 0x104>; + #clock-cells = <1>; + clocks = <&clkc_pll CLKID_FCLK_DIV2>, + <&clkc_pll CLKID_FCLK_DIV3>, + <&clkc_pll CLKID_FCLK_DIV5>, + <&clkc_pll CLKID_FCLK_DIV7>, + <&clkc_pll CLKID_HIFI_PLL>, + <&xtal>; + clock-names = "fclk_div2", "fclk_div3", + "fclk_div5", "fclk_div7", + "hifi_pll", "xtal"; + }; }; From patchwork Thu Dec 1 22:57:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Rokosov X-Patchwork-Id: 28584 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp529861wrr; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id bd32-20020a056a0027a000b0056cd91516b6si6265048pfb.325.2022.12.01.15.02.03; Thu, 01 Dec 2022 15:02:17 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@sberdevices.ru header.s=mail header.b=Sysgntah; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=sberdevices.ru Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231710AbiLAW6c (ORCPT + 99 others); Thu, 1 Dec 2022 17:58:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231695AbiLAW5m (ORCPT ); Thu, 1 Dec 2022 17:57:42 -0500 Received: from mx.sberdevices.ru (mx.sberdevices.ru [45.89.227.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7E455DF23; Thu, 1 Dec 2022 14:57:40 -0800 (PST) Received: from s-lin-edge02.sberdevices.ru (localhost [127.0.0.1]) by mx.sberdevices.ru (Postfix) with ESMTP id E67A95FD14; Fri, 2 Dec 2022 01:57:38 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sberdevices.ru; s=mail; t=1669935458; bh=bNlxstNU84ePp/QGlEFa5UnW4sFn/xynzmg1ch/OV9o=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type; b=Sysgntah8htYD/a6IF0x+iJffTAI+E6jOLImsQ4Xrpx5M0b9EaXeTXwtZbQ6dkWzD QPxSd65Ud6OAkCKM2M4S3VrxholSmDn7ffdGXgtEyO6rykXQ9QcyVS7LGby4rqr6jX tzYBqaH/YKuCZ1+YvbiofaO2xk+DqorAkAbboiXTyhhYJQ90rCuiJDkA1HGzgkYggz 5JZHwubT9Df6wa2HuCZH02LIMs9KshbOOAxTzwuFCQ946SeFZ1jwmVRv0b8rwjnz5y Vk58FSrd/Ru/NEtuSPmyg000uGzKPWeBLoGZXg1HOAFpAiE/rNCizH99TtLSr7Vp7p nfs3vVR8iJmZg== Received: from S-MS-EXCH01.sberdevices.ru (S-MS-EXCH01.sberdevices.ru [172.16.1.4]) by mx.sberdevices.ru (Postfix) with ESMTP; Fri, 2 Dec 2022 01:57:38 +0300 (MSK) From: Dmitry Rokosov To: , , , , , , , CC: , , , , , , , , Dmitry Rokosov Subject: [PATCH v8 11/11] arm64: dts: meson: a1: introduce PLL and Peripherals clk controllers Date: Fri, 2 Dec 2022 01:57:03 +0300 Message-ID: <20221201225703.6507-12-ddrokosov@sberdevices.ru> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20221201225703.6507-1-ddrokosov@sberdevices.ru> References: <20221201225703.6507-1-ddrokosov@sberdevices.ru> MIME-Version: 1.0 X-Originating-IP: [172.16.1.6] X-ClientProxiedBy: S-MS-EXCH02.sberdevices.ru (172.16.1.5) To S-MS-EXCH01.sberdevices.ru (172.16.1.4) X-KSMG-Rule-ID: 4 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Status: not scanned, disabled by settings X-KSMG-AntiSpam-Interceptor-Info: not scanned X-KSMG-AntiPhishing: not scanned, disabled by settings X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 1.1.2.30, bases: 2022/12/01 20:49:00 #20634374 X-KSMG-AntiVirus-Status: Clean, skipped X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751054535223523695?= X-GMAIL-MSGID: =?utf-8?q?1751054535223523695?= This patch adds clkc_periphs and clkc_pll dts nodes to A1 SoC main dtsi. The first one clk controller is responsible for all SoC peripherals clocks excluding audio clocks. The second one clk controller is used by A1 SoC PLLs. Actually, there are two different APB heads, so we have two different drivers. Signed-off-by: Dmitry Rokosov --- arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 27 ++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index b4000cf65a9a..38e6517c603c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -6,6 +6,8 @@ #include #include #include +#include +#include / { compatible = "amlogic,a1"; @@ -81,7 +83,6 @@ apb: bus@fe000000 { #size-cells = <2>; ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>; - reset: reset-controller@0 { compatible = "amlogic,meson-a1-reset"; reg = <0x0 0x0 0x0 0x8c>; @@ -124,6 +125,30 @@ uart_AO_B: serial@2000 { clock-names = "xtal", "pclk", "baud"; status = "disabled"; }; + + clkc_periphs: periphs-clock-controller@800 { + compatible = "amlogic,a1-periphs-clkc"; + reg = <0 0x800 0 0x104>; + #clock-cells = <1>; + clocks = <&clkc_pll CLKID_FCLK_DIV2>, + <&clkc_pll CLKID_FCLK_DIV3>, + <&clkc_pll CLKID_FCLK_DIV5>, + <&clkc_pll CLKID_FCLK_DIV7>, + <&clkc_pll CLKID_HIFI_PLL>, + <&xtal>; + clock-names = "fclk_div2", "fclk_div3", + "fclk_div5", "fclk_div7", + "hifi_pll", "xtal"; + }; + + clkc_pll: pll-clock-controller@7c80 { + compatible = "amlogic,a1-pll-clkc"; + reg = <0 0x7c80 0 0x18c>; + #clock-cells = <1>; + clocks = <&clkc_periphs CLKID_XTAL_FIXPLL>, + <&clkc_periphs CLKID_XTAL_HIFIPLL>; + clock-names = "xtal_fixpll", "xtal_hifipll"; + }; }; gic: interrupt-controller@ff901000 {