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[2620:137:e000::1:20]) by mx.google.com with ESMTP id r8-20020aa7d148000000b0046775f92f19si4342633edo.50.2022.12.01.12.01.40; Thu, 01 Dec 2022 12:02:03 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=ewe8Su+z; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230487AbiLAT5T (ORCPT + 99 others); Thu, 1 Dec 2022 14:57:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229723AbiLAT5R (ORCPT ); Thu, 1 Dec 2022 14:57:17 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8ACB892A10 for ; Thu, 1 Dec 2022 11:57:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669924636; x=1701460636; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=26LDl5gEfOUK1vLXLl8rkZu+pPxLEfyA+JmOQyiRqI0=; b=ewe8Su+ziWIjDThDstqvbRndTrLthYJqI01YCDbAdVC9V46w5WFisPXM 20V1c4bBbZ/SFt52n2mi5Rs0sHfjIfSiVi0l0OLVVYxEWOhgYmO0GGPwR 5YdXh3ztdQMroGBvBk1NBcIC0QH77pa9t7WrA7a7c1CUcEZTywgEwaRa2 dZWK3z5fmr2gZpjxFEvzYq2nEZR/Zw4+/ctJeL+TRmleQUGOcfr7fX0or Vsm8/ZW87yYvCnawADJMe32MZsetNoVboZBAw9AtTnNLrx7Md9OoWFhFD 3oclwOQmqW7y2+aqHAgnfMhZ6IryVO0Oi2bmVHIOFT3vPmo8FH13MLof7 g==; X-IronPort-AV: E=McAfee;i="6500,9779,10548"; a="303391852" X-IronPort-AV: E=Sophos;i="5.96,210,1665471600"; d="scan'208";a="303391852" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Dec 2022 11:57:15 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10548"; a="708205026" X-IronPort-AV: E=Sophos;i="5.96,210,1665471600"; d="scan'208";a="708205026" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by fmsmga008.fm.intel.com with ESMTP; 01 Dec 2022 11:57:15 -0800 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-kernel@vger.kernel.org Cc: ak@linux.intel.com, eranian@google.com, irogers@google.com, Kan Liang Subject: [PATCH 1/9] perf: Add PMU_FORMAT_ATTR_SHOW Date: Thu, 1 Dec 2022 11:56:56 -0800 Message-Id: <20221201195704.2330866-1-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751043196863647894?= X-GMAIL-MSGID: =?utf-8?q?1751043196863647894?= From: Kan Liang The macro PMU_FORMAT_ATTR facilitates the definition of both the "show" function and "format_attr". But it only works for a non-hybrid platform. For a hybrid platform, the name "format_attr_hybrid_" is used. The definition of the "show" function can be shared between a non-hybrid platform and a hybrid platform. Add a new macro PMU_FORMAT_ATTR_SHOW. No functional change. The PMU_FORMAT_ATTR_SHOW will be used in the following patch. Signed-off-by: Kan Liang --- include/linux/perf_event.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 0031f7b4d9ab..ab251c737f97 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -1661,7 +1661,7 @@ static struct perf_pmu_events_attr _var = { \ .id = _id, } \ })[0].attr.attr) -#define PMU_FORMAT_ATTR(_name, _format) \ +#define PMU_FORMAT_ATTR_SHOW(_name, _format) \ static ssize_t \ _name##_show(struct device *dev, \ struct device_attribute *attr, \ @@ -1670,6 +1670,9 @@ _name##_show(struct device *dev, \ BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \ return sprintf(page, _format "\n"); \ } \ + +#define PMU_FORMAT_ATTR(_name, _format) \ + PMU_FORMAT_ATTR_SHOW(_name, _format) \ \ static struct device_attribute format_attr_##_name = __ATTR_RO(_name) From patchwork Thu Dec 1 19:56:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liang, Kan" X-Patchwork-Id: 28533 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp458151wrr; Thu, 1 Dec 2022 12:01:16 -0800 (PST) X-Google-Smtp-Source: AA0mqf4zgryUlKemgipgT8Q+Sxm+aikHNyr+sZstmvO2aD4bHxs7kbBhmRFGIoWGJE2x/vlOHBSp X-Received: by 2002:aa7:d1c5:0:b0:46b:a536:e8d0 with SMTP id g5-20020aa7d1c5000000b0046ba536e8d0mr9438083edp.261.1669924876290; Thu, 01 Dec 2022 12:01:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669924876; cv=none; d=google.com; s=arc-20160816; b=ngKuJ4gIf2+tjBiaxKra/wRoCPDejZxIIbC4erUKk5w/B/9lXOoO04kQnbNZCtyD0h w3mi2yJwa9w8tFMSKQXvM3jpau2pE+bLAFwbaiyZ3DQPJkenJq9auKJNk/VCGSu/36VL HEWcNdYhV6xkyEoyt0U6Mp/fvKIsKc7VVSJfLDTj/hZc0s+ycm3VLj4P6FaAJEiFh12w R9nMKp4pb/JBfEwRs4lWWeGIbfgzfE4Yao2OZGPQmiGaEGQD7W5ATmGxGAO4SaA11DAm HzShhP4xQj9ND5IwqPQqPeuT6yNwtAThtga6+deTmOCIGzxzdBpf+vMWk4IL+Zem0g+i j4xw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=KTWj/gu2+xOqYfq6hhf94+Tv4TU9OWgMb0c88q/oJF0=; b=1AqUs0yhpoY2w3pkj8hl9AcZ46ufYZZMpoVdgP2HbSTvRTaNrMFcJmE+stYly6oeu2 WJ+6ugckU4AQmPHnLHevIypUt8LJLw6hOnNaLFeisYa/GTL6y2GKLU2Ze+bl+y39SKOQ dk5PhM/WjwoIZdl43J6QXquIDkzIgwSEbVApGsqrkVb9HAvJxWEbEM3ZoG7Spw5NCbXi DZhOzYQetfDUpgmIoeQn3gcjA8nJbxr5DI5g6bHp3tGSpbWIclumv89j4dlqk9v/+IrB JDBjxZLdkyy/7903mSOX21I6brai/IP4ccevMCus8enPGeo2k0HudhDOsJ3sMPU/+vfy U7IA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=H2USqtpE; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id qa10-20020a170907868a00b00773db351c39si2600872ejc.64.2022.12.01.12.00.53; Thu, 01 Dec 2022 12:01:16 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=H2USqtpE; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231148AbiLAT5X (ORCPT + 99 others); Thu, 1 Dec 2022 14:57:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52580 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230020AbiLAT5S (ORCPT ); Thu, 1 Dec 2022 14:57:18 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58EE3BA602 for ; Thu, 1 Dec 2022 11:57:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669924637; x=1701460637; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Zyr6BKpBUBlQL+Bko4ULKP40A+CIBCdrhSKXQp4xYYk=; b=H2USqtpECECAQtwtye1H1uqzj8NXpqtSeMgykf9f6kIyTTTnNDGTl2+H xf/qzeQwdT0IywNeuG8/j8XTio8M5o/CpBkmSxtRSWQwVHM5mWdURNe44 lz5RXivmJDhYM+uUa0fdwiLOsnhf3RZcYHMjxh+P5ahW0vHN8kStcL8Q6 Mt87WPNtO2cgt7dsQlVF9RDiXG/l+u8z2CnlG/OM/h5fcj2kGk1m3sYBO I5riabR1mDjZ09QZkMCoWw2TAu5Cs6GbPfsA5Tgn+St5E9CGVe2n/RRuA OvgBjsVb5x9ARoe5FDdGPnUB8v2O0TUCitIb6fdVXus74QKhLQa/1dOZj Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10548"; a="303391857" X-IronPort-AV: E=Sophos;i="5.96,210,1665471600"; d="scan'208";a="303391857" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Dec 2022 11:57:16 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10548"; a="708205042" X-IronPort-AV: E=Sophos;i="5.96,210,1665471600"; d="scan'208";a="708205042" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by fmsmga008.fm.intel.com with ESMTP; 01 Dec 2022 11:57:15 -0800 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-kernel@vger.kernel.org Cc: ak@linux.intel.com, eranian@google.com, irogers@google.com, Kan Liang Subject: [PATCH 2/9] perf/x86: Add Meteor Lake support Date: Thu, 1 Dec 2022 11:56:57 -0800 Message-Id: <20221201195704.2330866-2-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221201195704.2330866-1-kan.liang@linux.intel.com> References: <20221201195704.2330866-1-kan.liang@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751043146898915106?= X-GMAIL-MSGID: =?utf-8?q?1751043146898915106?= From: Kan Liang From PMU's perspective, Meteor Lake is similar to Alder Lake. Both are hybrid platforms, with e-core and p-core. The key differences include: - The e-core supports 2 PDIST GP counters (GP0 & GP1) - New MSRs for the Module Snoop Response Events on the e-core. - New Data Source fields are introduced for the e-core. - There are 8 GP counters for the e-core. - The load latency AUX event is not required for the p-core anymore. - Retire Latency (Support in a separate patch) for both cores. Since most of the code in the intel_pmu_init() should be the same as Alder Lake, to avoid code duplication, share the path with Alder Lake. Add new specific functions of extra_regs, and get_event_constraints to support the OCR events, Module Snoop Response Events and 2 PDIST GP counters on e-core. Add new MTL specific mem_attrs which drops the load latency AUX event. The Data Source field is extended to 4:0, which can contains max 32 sources. The Retire Latency is implemented with a separate patch. Reviewed-by: Andi Kleen Signed-off-by: Kan Liang --- arch/x86/events/intel/core.c | 141 ++++++++++++++++++++++++++++--- arch/x86/events/intel/ds.c | 70 ++++++++++++--- arch/x86/events/perf_event.h | 21 +++-- arch/x86/include/asm/msr-index.h | 3 + 4 files changed, 203 insertions(+), 32 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 1b92bf05fd65..50d42c848eba 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -2119,6 +2119,16 @@ static struct extra_reg intel_grt_extra_regs[] __read_mostly = { EVENT_EXTRA_END }; +static struct extra_reg intel_cmt_extra_regs[] __read_mostly = { + /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ + INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff3ffffffffffull, RSP_0), + INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff3ffffffffffull, RSP_1), + INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), + INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0), + INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1), + EVENT_EXTRA_END +}; + #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ #define KNL_MCDRAM_LOCAL BIT_ULL(21) @@ -4182,6 +4192,12 @@ static int hsw_hw_config(struct perf_event *event) static struct event_constraint counter0_constraint = INTEL_ALL_EVENT_CONSTRAINT(0, 0x1); +static struct event_constraint counter1_constraint = + INTEL_ALL_EVENT_CONSTRAINT(0, 0x2); + +static struct event_constraint counter0_1_constraint = + INTEL_ALL_EVENT_CONSTRAINT(0, 0x3); + static struct event_constraint counter2_constraint = EVENT_CONSTRAINT(0, 0x4, 0); @@ -4191,6 +4207,9 @@ static struct event_constraint fixed0_constraint = static struct event_constraint fixed0_counter0_constraint = INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL); +static struct event_constraint fixed0_counter0_1_constraint = + INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000003ULL); + static struct event_constraint * hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, struct perf_event *event) @@ -4322,6 +4341,54 @@ adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, return &emptyconstraint; } +static struct event_constraint * +cmt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, + struct perf_event *event) +{ + struct event_constraint *c; + + c = intel_get_event_constraints(cpuc, idx, event); + + /* + * The :ppp indicates the Precise Distribution (PDist) facility, which + * is only supported on the GP counter 0 & 1 and Fixed counter 0. + * If a :ppp event which is not available on the above eligible counters, + * error out. + */ + if (event->attr.precise_ip == 3) { + /* Force instruction:ppp on PMC0, 1 and Fixed counter 0 */ + if (constraint_match(&fixed0_constraint, event->hw.config)) + return &fixed0_counter0_1_constraint; + + switch (c->idxmsk64 & 0x3ull) { + case 0x1: + return &counter0_constraint; + case 0x2: + return &counter1_constraint; + case 0x3: + return &counter0_1_constraint; + } + return &emptyconstraint; + } + + return c; +} + +static struct event_constraint * +mtl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, + struct perf_event *event) +{ + struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); + + if (pmu->cpu_type == hybrid_big) + return spr_get_event_constraints(cpuc, idx, event); + if (pmu->cpu_type == hybrid_small) + return cmt_get_event_constraints(cpuc, idx, event); + + WARN_ON(1); + return &emptyconstraint; +} + static int adl_hw_config(struct perf_event *event) { struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); @@ -5466,6 +5533,12 @@ static struct attribute *adl_hybrid_mem_attrs[] = { NULL, }; +static struct attribute *mtl_hybrid_mem_attrs[] = { + EVENT_PTR(mem_ld_adl), + EVENT_PTR(mem_st_adl), + NULL +}; + EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=0xc9,umask=0x1", hybrid_big); EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=0xc9,umask=0x2", hybrid_big); EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=0xc9,umask=0x4", hybrid_big); @@ -5493,20 +5566,40 @@ FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small); FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small); FORMAT_ATTR_HYBRID(frontend, hybrid_big); +#define ADL_HYBRID_RTM_FORMAT_ATTR \ + FORMAT_HYBRID_PTR(in_tx), \ + FORMAT_HYBRID_PTR(in_tx_cp) + +#define ADL_HYBRID_FORMAT_ATTR \ + FORMAT_HYBRID_PTR(offcore_rsp), \ + FORMAT_HYBRID_PTR(ldlat), \ + FORMAT_HYBRID_PTR(frontend) + static struct attribute *adl_hybrid_extra_attr_rtm[] = { - FORMAT_HYBRID_PTR(in_tx), - FORMAT_HYBRID_PTR(in_tx_cp), - FORMAT_HYBRID_PTR(offcore_rsp), - FORMAT_HYBRID_PTR(ldlat), - FORMAT_HYBRID_PTR(frontend), - NULL, + ADL_HYBRID_RTM_FORMAT_ATTR, + ADL_HYBRID_FORMAT_ATTR, + NULL }; static struct attribute *adl_hybrid_extra_attr[] = { - FORMAT_HYBRID_PTR(offcore_rsp), - FORMAT_HYBRID_PTR(ldlat), - FORMAT_HYBRID_PTR(frontend), - NULL, + ADL_HYBRID_FORMAT_ATTR, + NULL +}; + +PMU_FORMAT_ATTR_SHOW(snoop_rsp, "config1:0-63"); +FORMAT_ATTR_HYBRID(snoop_rsp, hybrid_small); + +static struct attribute *mtl_hybrid_extra_attr_rtm[] = { + ADL_HYBRID_RTM_FORMAT_ATTR, + ADL_HYBRID_FORMAT_ATTR, + FORMAT_HYBRID_PTR(snoop_rsp), + NULL +}; + +static struct attribute *mtl_hybrid_extra_attr[] = { + ADL_HYBRID_FORMAT_ATTR, + FORMAT_HYBRID_PTR(snoop_rsp), + NULL }; static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr) @@ -5728,6 +5821,12 @@ static void intel_pmu_check_hybrid_pmus(u64 fixed_mask) } } +static __always_inline bool is_mtl(u8 x86_model) +{ + return (x86_model == INTEL_FAM6_METEORLAKE) || + (x86_model == INTEL_FAM6_METEORLAKE_L); +} + __init int intel_pmu_init(void) { struct attribute **extra_skl_attr = &empty_attrs; @@ -6384,6 +6483,8 @@ __init int intel_pmu_init(void) case INTEL_FAM6_RAPTORLAKE: case INTEL_FAM6_RAPTORLAKE_P: case INTEL_FAM6_RAPTORLAKE_S: + case INTEL_FAM6_METEORLAKE: + case INTEL_FAM6_METEORLAKE_L: /* * Alder Lake has 2 types of CPU, core and atom. * @@ -6403,9 +6504,7 @@ __init int intel_pmu_init(void) x86_pmu.flags |= PMU_FL_HAS_RSP_1; x86_pmu.flags |= PMU_FL_NO_HT_SHARING; x86_pmu.flags |= PMU_FL_INSTR_LATENCY; - x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; x86_pmu.lbr_pt_coexist = true; - intel_pmu_pebs_data_source_adl(); x86_pmu.pebs_latency_data = adl_latency_data_small; x86_pmu.num_topdown_events = 8; static_call_update(intel_pmu_update_topdown_event, @@ -6492,8 +6591,22 @@ __init int intel_pmu_init(void) pmu->event_constraints = intel_slm_event_constraints; pmu->pebs_constraints = intel_grt_pebs_event_constraints; pmu->extra_regs = intel_grt_extra_regs; - pr_cont("Alderlake Hybrid events, "); - name = "alderlake_hybrid"; + if (is_mtl(boot_cpu_data.x86_model)) { + x86_pmu.pebs_latency_data = mtl_latency_data_small; + extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? + mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; + mem_attr = mtl_hybrid_mem_attrs; + intel_pmu_pebs_data_source_mtl(); + x86_pmu.get_event_constraints = mtl_get_event_constraints; + pmu->extra_regs = intel_cmt_extra_regs; + pr_cont("Meteorlake Hybrid events, "); + name = "meteorlake_hybrid"; + } else { + x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; + intel_pmu_pebs_data_source_adl(); + pr_cont("Alderlake Hybrid events, "); + name = "alderlake_hybrid"; + } break; default: diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 446d2833efa7..aba6ee03fe26 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -53,6 +53,13 @@ union intel_x86_pebs_dse { unsigned int st_lat_locked:1; unsigned int ld_reserved3:26; }; + struct { + unsigned int mtl_dse:5; + unsigned int mtl_locked:1; + unsigned int mtl_stlb_miss:1; + unsigned int mtl_fwd_blk:1; + unsigned int ld_reserved4:24; + }; }; @@ -135,6 +142,29 @@ void __init intel_pmu_pebs_data_source_adl(void) __intel_pmu_pebs_data_source_grt(data_source); } +static void __init intel_pmu_pebs_data_source_cmt(u64 *data_source) +{ + data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD); + data_source[0x08] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); + data_source[0x0a] = OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, NONE); + data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE); + data_source[0x0c] = OP_LH | LEVEL(RAM) | REM | P(SNOOPX, FWD); + data_source[0x0d] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, HITM); +} + +void __init intel_pmu_pebs_data_source_mtl(void) +{ + u64 *data_source; + + data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].pebs_data_source; + memcpy(data_source, pebs_data_source, sizeof(pebs_data_source)); + __intel_pmu_pebs_data_source_skl(false, data_source); + + data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX].pebs_data_source; + memcpy(data_source, pebs_data_source, sizeof(pebs_data_source)); + intel_pmu_pebs_data_source_cmt(data_source); +} + static u64 precise_store_data(u64 status) { union intel_x86_pebs_dse dse; @@ -219,24 +249,19 @@ static inline void pebs_set_tlb_lock(u64 *val, bool tlb, bool lock) } /* Retrieve the latency data for e-core of ADL */ -u64 adl_latency_data_small(struct perf_event *event, u64 status) +static u64 __adl_latency_data_small(struct perf_event *event, u64 status, + u8 dse, bool tlb, bool lock, bool blk) { - union intel_x86_pebs_dse dse; u64 val; WARN_ON_ONCE(hybrid_pmu(event->pmu)->cpu_type == hybrid_big); - dse.val = status; - - val = hybrid_var(event->pmu, pebs_data_source)[dse.ld_dse]; + dse &= PERF_PEBS_DATA_SOURCE_MASK; + val = hybrid_var(event->pmu, pebs_data_source)[dse]; - /* - * For the atom core on ADL, - * bit 4: lock, bit 5: TLB access. - */ - pebs_set_tlb_lock(&val, dse.ld_locked, dse.ld_stlb_miss); + pebs_set_tlb_lock(&val, tlb, lock); - if (dse.ld_data_blk) + if (blk) val |= P(BLK, DATA); else val |= P(BLK, NA); @@ -244,6 +269,29 @@ u64 adl_latency_data_small(struct perf_event *event, u64 status) return val; } +u64 adl_latency_data_small(struct perf_event *event, u64 status) +{ + union intel_x86_pebs_dse dse; + + dse.val = status; + + return __adl_latency_data_small(event, status, dse.ld_dse, + dse.ld_locked, dse.ld_stlb_miss, + dse.ld_data_blk); +} + +/* Retrieve the latency data for e-core of MTL */ +u64 mtl_latency_data_small(struct perf_event *event, u64 status) +{ + union intel_x86_pebs_dse dse; + + dse.val = status; + + return __adl_latency_data_small(event, status, dse.mtl_dse, + dse.mtl_stlb_miss, dse.mtl_locked, + dse.mtl_fwd_blk); +} + static u64 load_latency_data(struct perf_event *event, u64 status) { union intel_x86_pebs_dse dse; diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 332d2e6d8ae4..109453cc1a61 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -35,15 +35,17 @@ * per-core reg tables. */ enum extra_reg_type { - EXTRA_REG_NONE = -1, /* not used */ + EXTRA_REG_NONE = -1, /* not used */ - EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */ - EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */ - EXTRA_REG_LBR = 2, /* lbr_select */ - EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */ - EXTRA_REG_FE = 4, /* fe_* */ + EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */ + EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */ + EXTRA_REG_LBR = 2, /* lbr_select */ + EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */ + EXTRA_REG_FE = 4, /* fe_* */ + EXTRA_REG_SNOOP_0 = 5, /* snoop response 0 */ + EXTRA_REG_SNOOP_1 = 6, /* snoop response 1 */ - EXTRA_REG_MAX /* number of entries needed */ + EXTRA_REG_MAX /* number of entries needed */ }; struct event_constraint { @@ -647,6 +649,7 @@ enum { }; #define PERF_PEBS_DATA_SOURCE_MAX 0x10 +#define PERF_PEBS_DATA_SOURCE_MASK (PERF_PEBS_DATA_SOURCE_MAX - 1) struct x86_hybrid_pmu { struct pmu pmu; @@ -1489,6 +1492,8 @@ int intel_pmu_drain_bts_buffer(void); u64 adl_latency_data_small(struct perf_event *event, u64 status); +u64 mtl_latency_data_small(struct perf_event *event, u64 status); + extern struct event_constraint intel_core2_pebs_event_constraints[]; extern struct event_constraint intel_atom_pebs_event_constraints[]; @@ -1600,6 +1605,8 @@ void intel_pmu_pebs_data_source_adl(void); void intel_pmu_pebs_data_source_grt(void); +void intel_pmu_pebs_data_source_mtl(void); + int intel_pmu_setup_lbr_filter(struct perf_event *event); void intel_pt_interrupt(void); diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 4a2af82553e4..7c2f9b442f73 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -194,6 +194,9 @@ #define MSR_TURBO_RATIO_LIMIT1 0x000001ae #define MSR_TURBO_RATIO_LIMIT2 0x000001af +#define MSR_SNOOP_RSP_0 0x00001328 +#define MSR_SNOOP_RSP_1 0x00001329 + #define MSR_LBR_SELECT 0x000001c8 #define MSR_LBR_TOS 0x000001c9 From patchwork Thu Dec 1 19:56:58 2022 Content-Type: text/plain; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id s11-20020a170906a18b00b007317ad1f9a4si3683856ejy.310.2022.12.01.12.01.08; Thu, 01 Dec 2022 12:01:34 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=EPpKUM9O; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231134AbiLAT51 (ORCPT + 99 others); Thu, 1 Dec 2022 14:57:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52574 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230016AbiLAT5S (ORCPT ); Thu, 1 Dec 2022 14:57:18 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8AB26BA605 for ; Thu, 1 Dec 2022 11:57:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669924637; x=1701460637; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=m3p7dA7XIEh6S+36fU37C74NxJONdFP779x53nQtVkA=; b=EPpKUM9O+ubJiMB0Zfj2M9VV59TfM91HbVd50uhOJnl93e176oU9sDVk Mcgt38qblSmJLacDQg85Wzz+g/WrHm7VtrTeFoMK11ViHwDTSYWyewry0 /Ot1BtQRKWbG523VZhLGcyU2K3OgGuWYEu4Sa8f0zlSQrAMbHaNEWMrde VXybRPWFruBoJIJQciD5OqHZ9RzC7d/j4KZN9LCg6UuYMa7y6RmHpAmoF NJwmCoqyxt4LALDBloejT5HUj12ZHPW91oSYF1Z2jKNR6+2ObeVcm5TTJ RjacQF8HVkWiD8nH/EQsqTR7sM0dgdbgFhMKC89WxohaCQSGTGtFpBZz8 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10548"; a="303391864" X-IronPort-AV: E=Sophos;i="5.96,210,1665471600"; d="scan'208";a="303391864" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Dec 2022 11:57:16 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10548"; a="708205064" X-IronPort-AV: E=Sophos;i="5.96,210,1665471600"; d="scan'208";a="708205064" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by fmsmga008.fm.intel.com with ESMTP; 01 Dec 2022 11:57:16 -0800 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-kernel@vger.kernel.org Cc: ak@linux.intel.com, eranian@google.com, irogers@google.com, Kan Liang Subject: [PATCH 3/9] perf/x86: Support Retire Latency Date: Thu, 1 Dec 2022 11:56:58 -0800 Message-Id: <20221201195704.2330866-3-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221201195704.2330866-1-kan.liang@linux.intel.com> References: <20221201195704.2330866-1-kan.liang@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751043166323944655?= X-GMAIL-MSGID: =?utf-8?q?1751043166323944655?= From: Kan Liang Retire Latency reports the number of elapsed core clocks between the retirement of the instruction indicated by the Instruction Pointer field of the PEBS record and the retirement of the prior instruction. It's enumerated by the IA32_PERF_CAPABILITIES.PEBS_TIMING_INFO[17]. Add flag PMU_FL_RETIRE_LATENCY to indicate the availability of the feature. The Retire Latency is not supported by the fixed counter 0 on p-core of MTL. Reviewed-by: Andi Kleen Signed-off-by: Kan Liang --- arch/x86/events/intel/core.c | 32 +++++++++++++++++++++++++++++++- arch/x86/events/intel/ds.c | 4 ++++ arch/x86/events/perf_event.h | 2 ++ 3 files changed, 37 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 50d42c848eba..b97eb3bff6ae 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -4210,6 +4210,9 @@ static struct event_constraint fixed0_counter0_constraint = static struct event_constraint fixed0_counter0_1_constraint = INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000003ULL); +static struct event_constraint counters_1_7_constraint = + INTEL_ALL_EVENT_CONSTRAINT(0, 0xfeULL); + static struct event_constraint * hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, struct perf_event *event) @@ -4374,6 +4377,30 @@ cmt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, return c; } +static struct event_constraint * +rwc_get_event_constraints(struct cpu_hw_events *cpuc, int idx, + struct perf_event *event) +{ + struct event_constraint *c; + + c = spr_get_event_constraints(cpuc, idx, event); + + /* The Retire Latency is not supported by the fixed counter 0. */ + if (event->attr.precise_ip && + (event->attr.sample_type & PERF_SAMPLE_WEIGHT_TYPE) && + constraint_match(&fixed0_constraint, event->hw.config)) { + /* + * The Instruction PDIR is only available + * on the fixed counter 0. Error out for this case. + */ + if (event->attr.precise_ip == 3) + return &emptyconstraint; + return &counters_1_7_constraint; + } + + return c; +} + static struct event_constraint * mtl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, struct perf_event *event) @@ -4381,7 +4408,7 @@ mtl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); if (pmu->cpu_type == hybrid_big) - return spr_get_event_constraints(cpuc, idx, event); + return rwc_get_event_constraints(cpuc, idx, event); if (pmu->cpu_type == hybrid_small) return cmt_get_event_constraints(cpuc, idx, event); @@ -6721,6 +6748,9 @@ __init int intel_pmu_init(void) if (is_hybrid()) intel_pmu_check_hybrid_pmus((u64)fixed_mask); + if (x86_pmu.intel_cap.pebs_timing_info) + x86_pmu.flags |= PMU_FL_RETIRE_LATENCY; + intel_aux_output_init(); return 0; diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index aba6ee03fe26..6df10be6630e 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -1753,6 +1753,7 @@ static void adaptive_pebs_save_regs(struct pt_regs *regs, #define PEBS_LATENCY_MASK 0xffff #define PEBS_CACHE_LATENCY_OFFSET 32 +#define PEBS_RETIRE_LATENCY_OFFSET 32 /* * With adaptive PEBS the layout depends on what fields are configured. @@ -1804,6 +1805,9 @@ static void setup_pebs_adaptive_sample_data(struct perf_event *event, set_linear_ip(regs, basic->ip); regs->flags = PERF_EFLAGS_EXACT; + if ((sample_type & PERF_SAMPLE_WEIGHT_STRUCT) && (x86_pmu.flags & PMU_FL_RETIRE_LATENCY)) + data->weight.var3_w = format_size >> PEBS_RETIRE_LATENCY_OFFSET & PEBS_LATENCY_MASK; + /* * The record for MEMINFO is in front of GP * But PERF_SAMPLE_TRANSACTION needs gprs->ax. diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 109453cc1a61..e325673722b6 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -608,6 +608,7 @@ union perf_capabilities { u64 pebs_baseline:1; u64 perf_metrics:1; u64 pebs_output_pt_available:1; + u64 pebs_timing_info:1; u64 anythread_deprecated:1; }; u64 capabilities; @@ -1003,6 +1004,7 @@ do { \ #define PMU_FL_PAIR 0x40 /* merge counters for large incr. events */ #define PMU_FL_INSTR_LATENCY 0x80 /* Support Instruction Latency in PEBS Memory Info Record */ #define PMU_FL_MEM_LOADS_AUX 0x100 /* Require an auxiliary event for the complete memory info */ +#define PMU_FL_RETIRE_LATENCY 0x200 /* Support Retire Latency in PEBS */ #define EVENT_VAR(_id) event_attr_##_id #define EVENT_PTR(_id) &event_attr_##_id.attr.attr From patchwork Thu Dec 1 19:56:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liang, Kan" X-Patchwork-Id: 28535 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp458385wrr; Thu, 1 Dec 2022 12:01:38 -0800 (PST) X-Google-Smtp-Source: AA0mqf4tLFcx1ienMpH6+LhHFDWFJgJVwww6rvZqoZGwVi7kCQVy3EwH7rqEIXoe0PMaKe+/T78m X-Received: by 2002:a17:907:a4c3:b0:7c0:7c22:d70d with SMTP id vq3-20020a170907a4c300b007c07c22d70dmr16403595ejc.707.1669924898118; Thu, 01 Dec 2022 12:01:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669924898; cv=none; d=google.com; s=arc-20160816; b=BVoKT2H38zD1LeDcNE1pf7ER1yKAoM4G1gt+7lSOWQITC9T33rKGJAKuCclERXzSSW +8d795ILSYmMAfqdMUoo8S0eg9C5ictlzPC5tkMflPPecOnwhRhNZwz6r1WqC1rTKEzw BdkDlecSxxFkuutAba5aoRtsnQa6p9XAMj+eOlwm41FTK51ncimw0CQHoGWPNpZF9L+u hOgtrAI1mFpplGZiUhjfCyqGBvIIgCKzcFYUeH5u284t4cRgv/XFG9ED93MxXH4ZlFTD CrM0Yfs4TNt4ykmU7sp0WrC6v9FMlyrWBGccXzFzlaGqlrSlKokniXtcndR56Et3ccjC nClQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=voBRxBch1E+FCzHfieNS2hTMJbJQiF7kuN8ZSH8fML4=; b=kTJNL3Jjom4tEEIDHIsKl1rKsSR1+ZlLCt2/5qe92xJwvrVGypBoIrygQWWJbSFzSw 7oqE+80gDKZzm9iOJvgri4XQM3XeNaJo1m3sxq+g7YerzYXviu1yBQBqD9+U1vCkPcd5 pTn0bitQyVzW1eEpuFCUNauDrYVfGbP0Z5ZG8Z2fs9mkDLnrQt+k7sp9jO+KJmPyUuqO tQTLiHeCNCSi1OHrQpeF5r4IE18dtpnt0jbcBl0DfkQGChJCfAYLac/KJ1/lMvZhT5Xz X3wlAfsXBSvWuT7cbK3NMEolSJ02bVBhzHpWMUQ24pPnnxgkq/hIeZNr79bmMKw6YKO6 huhg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="Ze8ep/Ul"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id qb20-20020a1709077e9400b007c08a2c23f7si4616904ejc.84.2022.12.01.12.01.12; Thu, 01 Dec 2022 12:01:38 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="Ze8ep/Ul"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231164AbiLAT5c (ORCPT + 99 others); Thu, 1 Dec 2022 14:57:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230321AbiLAT5S (ORCPT ); Thu, 1 Dec 2022 14:57:18 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D61092A10 for ; Thu, 1 Dec 2022 11:57:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669924638; x=1701460638; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FuioOk9lkJV3UqTyerhKrNp8li4XyFOaJM/neBGnO78=; b=Ze8ep/UlnqH4qh7kzQh7aTefBmzGmkoARBgBLw0MOKm1gd8KzD4I835v dXtkrtAE90m35K2wupMiKpuvnR5hirGjhg+md0zlvfvWP8RswrAKxdhsq i3hnUCvb+RB21QXhyiKlAIIHdHimXi+A3xkZb9ugNVOZZn49ceRHZeXEd RqaXvauAPyL5BzVfTDMTKyJjsea+Qb+mQ5ojq7EVqTBT/Do86sJTsGd6f J36BraxTrr66IY0uwo44E9aV5FKzuwm/UiSfoB4yJu57ZspD89qWWcMRx OPakwsBKPO7J9NPcHjssU15rLbZoGTHC45Exiu/eSBupNiGZzmvldKoHD w==; X-IronPort-AV: E=McAfee;i="6500,9779,10548"; a="303391872" X-IronPort-AV: E=Sophos;i="5.96,210,1665471600"; d="scan'208";a="303391872" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Dec 2022 11:57:17 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10548"; a="708205083" X-IronPort-AV: E=Sophos;i="5.96,210,1665471600"; d="scan'208";a="708205083" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by fmsmga008.fm.intel.com with ESMTP; 01 Dec 2022 11:57:16 -0800 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-kernel@vger.kernel.org Cc: ak@linux.intel.com, eranian@google.com, irogers@google.com, Kan Liang Subject: [PATCH 4/9] x86/cpufeatures: Add Architectural PerfMon Extension bit Date: Thu, 1 Dec 2022 11:56:59 -0800 Message-Id: <20221201195704.2330866-4-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221201195704.2330866-1-kan.liang@linux.intel.com> References: <20221201195704.2330866-1-kan.liang@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751043169922066366?= X-GMAIL-MSGID: =?utf-8?q?1751043169922066366?= From: Kan Liang CPUID.(EAX=07H, ECX=1):EAX[8] indicates whether the Architectural PerfMon Extension leaf (CPUID leaf 23) is supported. The "X86_FEATURE_..., word 12" is already mirrored from CPUID "0x00000007:1 (EAX)". Add X86_FEATURE_ARCH_PERFMON_EXT under the "word 12" section. The new Architectural PerfMon Extension leaf (CPUID leaf 23) will be supported in the perf_events subsystem later. The feature will not appear in /proc/cpuinfo. Signed-off-by: Kan Liang --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index b71f4f2ecdd5..9f05a0bb93ca 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -308,6 +308,7 @@ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ +#define X86_FEATURE_ARCH_PERFMON_EXT (12*32+ 8) /* "" Intel Architectural PerfMon Extension */ /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ From patchwork Thu Dec 1 19:57:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liang, Kan" X-Patchwork-Id: 28536 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp458486wrr; Thu, 1 Dec 2022 12:01:48 -0800 (PST) X-Google-Smtp-Source: AA0mqf5RcbrD+wrnkDUkUyeWg8pjfGDOiEFuFYQiYeGKlfLO3sGsRBPtL2Z5KpnZBtifKRCXnhTZ X-Received: by 2002:a17:907:77d6:b0:78d:e26f:bfd8 with SMTP id kz22-20020a17090777d600b0078de26fbfd8mr57717969ejc.482.1669924908723; Thu, 01 Dec 2022 12:01:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669924908; cv=none; d=google.com; s=arc-20160816; b=sWo2xIQhkix+CJj/JKuMBHbRL89O2hHasfEBKl9ExF1ZGEh0qfesK22HVcj1MFcb0+ PQVyfqroi38YHw5CWiK5x1nXsCqYTWRpWgTiDWt4YewErwl59MZWOYzDkA4ol/eJjRfP EEzAy5TmVnl0WaVpWLWk9S9OEeGoLlvqWdBg4Pb/qiGDeeAmo5KjXJlRMuTTbIQb2mtH S1SluwJ0CRDNnGYPTlWIMutNfCox8NbrOTqwlPn/INxNyibSJ5JstvUYNwn2lHXKwWRt tnSYP8rmvd7W+ks2VdNDhOn9JY4rTh2aQVLCrGYYdoJ9hhJp1xT8J+mYjPlO9IrGl6F6 OJig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=RnctwFO59RDhjMAW0dXmnNFb39uXxC4XxPi4Cp1f8js=; b=aNBLRe3565U2Ilv/JlpNMyU3I/OUmg8BLFHjETMul9ScwAgZtfau+5kFUT4EScllzy fwB2ICyd3ZHDoJNEXR0QRTNh5pEc73+0yed13Mtm+Fv2DxylVM1zAFLZdFk8H/S4WsxG i7Vh7ocaMty/hJP7GyWRrQ8u7c9JVeZjB8HNv/Lw+H61SDr+8ogFEf3+8Rolc6Apm9OG Ltw6moPSbTa1Tl1qN3uS/3YO4sphTzkvxbSdiKg9oAuSFZPt0x90qySPbkjwm//4wFmF z5HYpTvbw786HqKQzgmkbZDWipg7MyCuKdjIOO5tffb+CPbAEjosLq4CrR4Vnh8vAboo 1lNw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=OWANBxHg; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id y5-20020a50eb85000000b00467960d3013si4389937edr.43.2022.12.01.12.01.25; Thu, 01 Dec 2022 12:01:48 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=OWANBxHg; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231186AbiLAT5g (ORCPT + 99 others); Thu, 1 Dec 2022 14:57:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52592 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230457AbiLAT5T (ORCPT ); Thu, 1 Dec 2022 14:57:19 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D65FFBA602 for ; Thu, 1 Dec 2022 11:57:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669924638; x=1701460638; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=I7uBgAnaB7CJhvzOf++h2sYTBFzxqutPFL074As47JI=; b=OWANBxHgxBh+/zMe8oobzcekc60aUCvJ8RGjDRLAxswhpCaKawLmZn/R v+cd5MkOZmn6NWZuOhOC6ZqMTLnFOFwlJqLDUCCKTWjvMSJ7VxwDrPYPg rLGGIUT1dka+FMZ28gdwqkIWXrfRPYaRpL4vMIfQNC1DqZVSirg7+Xdgf 7kzqXwQbz8q5KjigMqDmxrMxjWl1RkZkLHCY6LI1NncYWQLBPVjBwReWR YA+vl8clSi0VDitvss2KRSpZAtM6ZtROzBHKWjMXJBrhRWgRjJZMGRpHH lPPWD4YWG3/uj4hyciFe0ca6dQd5efdzbanA8GcNkU7zoaPj0U0VsYIF3 A==; X-IronPort-AV: E=McAfee;i="6500,9779,10548"; a="303391877" X-IronPort-AV: E=Sophos;i="5.96,210,1665471600"; d="scan'208";a="303391877" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Dec 2022 11:57:17 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10548"; a="708205109" X-IronPort-AV: E=Sophos;i="5.96,210,1665471600"; d="scan'208";a="708205109" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by fmsmga008.fm.intel.com with ESMTP; 01 Dec 2022 11:57:17 -0800 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-kernel@vger.kernel.org Cc: ak@linux.intel.com, eranian@google.com, irogers@google.com, Kan Liang Subject: [PATCH 5/9] perf/x86/intel: Support Architectural PerfMon Extension leaf Date: Thu, 1 Dec 2022 11:57:00 -0800 Message-Id: <20221201195704.2330866-5-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221201195704.2330866-1-kan.liang@linux.intel.com> References: <20221201195704.2330866-1-kan.liang@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751043181362821671?= X-GMAIL-MSGID: =?utf-8?q?1751043181362821671?= From: Kan Liang The new CPUID leaf 0x23 reports the "true view" of PMU resources. The sub-leaf 1 reports the available general-purpose counters and fixed counters. Update the number of counters and fixed counters when the sub-leaf is detected. Signed-off-by: Kan Liang --- arch/x86/events/intel/core.c | 22 ++++++++++++++++++++++ arch/x86/include/asm/perf_event.h | 8 ++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index b97eb3bff6ae..9d49c6db40d3 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -4588,6 +4588,25 @@ static void flip_smm_bit(void *data) } } +static void intel_pmu_check_num_counters(int *num_counters, + int *num_counters_fixed, + u64 *intel_ctrl, u64 fixed_mask); + +static void update_pmu_cap(struct x86_hybrid_pmu *pmu) +{ + unsigned int sub_bitmaps = cpuid_eax(ARCH_PERFMON_EXT_LEAF); + unsigned int eax, ebx, ecx, edx; + + if (sub_bitmaps & ARCH_PERFMON_NUM_COUNTER_LEAF_BIT) { + cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF, + &eax, &ebx, &ecx, &edx); + pmu->num_counters = fls(eax); + pmu->num_counters_fixed = fls(ebx); + intel_pmu_check_num_counters(&pmu->num_counters, &pmu->num_counters_fixed, + &pmu->intel_ctrl, ebx); + } +} + static bool init_hybrid_pmu(int cpu) { struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); @@ -4613,6 +4632,9 @@ static bool init_hybrid_pmu(int cpu) if (!cpumask_empty(&pmu->supported_cpus)) goto end; + if (this_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT)) + update_pmu_cap(pmu); + if (!check_hw_exists(&pmu->pmu, pmu->num_counters, pmu->num_counters_fixed)) return false; diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 9ac46dbe57d4..98efe1d4005b 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -159,6 +159,14 @@ union cpuid10_edx { unsigned int full; }; +/* + * Intel "Architectural Performance Monitoring extension" CPUID + * detection/enumeration details: + */ +#define ARCH_PERFMON_EXT_LEAF 0x00000023 +#define ARCH_PERFMON_NUM_COUNTER_LEAF_BIT 0x1 +#define ARCH_PERFMON_NUM_COUNTER_LEAF 0x1 + /* * Intel Architectural LBR CPUID detection/enumeration details: */ From patchwork Thu Dec 1 19:57:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liang, Kan" X-Patchwork-Id: 28538 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp458722wrr; Thu, 1 Dec 2022 12:02:11 -0800 (PST) X-Google-Smtp-Source: AA0mqf4p4tW/mYkUFnaq9NjCT8uAsjMqjUtMc7D7v6niXe3UNpBWegxnIJiF0bRFrSKl0VhPW7YF X-Received: by 2002:aa7:db90:0:b0:459:aa70:d4fd with SMTP id u16-20020aa7db90000000b00459aa70d4fdmr59144901edt.162.1669924930753; Thu, 01 Dec 2022 12:02:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669924930; cv=none; d=google.com; s=arc-20160816; b=lIkLLM5UEXEL7ZsfAQPoV6JPHnMQLcAO9OzSViLdW3CLk/2r6AFTVNSzU5groxDZEK +LlAvLkWDWyyy8Um9v915flqsqvhyIuN2c2Q2KEchgtGN0+Bkl55vbF9BOi8HKOvm1xy rmmpQoClZ0Oat3A/oJjyE7RHA0hc0yW0GOCiLryTAJK3a/1qEuN+kmVCDK9jQTeQQT9H M0/DF5WfyxPKVoBkjilvJqis2WlCTB/nAL2W9wsV1MatRUVpKAKN+Gl7NkxPLFhXKXED +m4cRGekJLDQhMa7IzIKSgDDPRt2VaKB35NgIwb2AruoIDQqKiAPJPnVm2wUV4Oe/CPJ qKAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=rpfh17W3Fsw+/QHUWbUn6fVxTg7O1AdjSaH0RYa6TIQ=; b=jHEabwIiNt3SlkwYSIdXBOlN7SSv0hT1DaOIXTuEuH6JuyFxN3SD18+zIu9XDJRe6s uJPHgyIxMU00SfI5iqaFmtuhi1xWFbJAkTuDHJof8QmCk3+vzLC4V3t3hP750Nl5V5aT x597qXF1HauFDvN+YNicDVWC7mHmnOMIHSkqLUIxdnO8gzlrDeg10p0HA/TxFU55qEPW XegSE4ZqMLcLQtDtA3x6Y2FvkeFxcqsg1JKOGy63W/POr23dh6Mh9C71hJMFE9oLHyVK qnsP7vsgEtgfFlz1yCGwolw6qy7pdV7FN0NxmvQg6RmfSyDB6wXQxKtDJxSF8tHb9ccM QNLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=fnRZI99L; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id v5-20020a50d585000000b00458d1c48708si4174578edi.303.2022.12.01.12.01.26; Thu, 01 Dec 2022 12:02:10 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=fnRZI99L; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231274AbiLAT5l (ORCPT + 99 others); Thu, 1 Dec 2022 14:57:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52594 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230469AbiLAT5T (ORCPT ); Thu, 1 Dec 2022 14:57:19 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E33C8BA605 for ; Thu, 1 Dec 2022 11:57:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669924638; x=1701460638; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fKB/9fd1T4ldG6F8XD4RYHrEodmKy4TFikEQOjDIV3o=; b=fnRZI99LjN/+XmwhmDvCRJhiyFM0gxvA19NUKh2JrzIPhRErLtH617Iw j27ks7hgkJJjw9BSBViQaKinnRkR1D3CXduA7WV0h+CTWtyn2/rSg6mrE F5P4Oj1ick4Dfht/pBfHmIXXiSpKtR+AQ4MPw9uJicyiuzD18AiwpqVVn 8qlPo1UfwWB+wzCb0KjAqx6jwn6s4fcKJZnyBMBTGBdHBzsx0JAIP54s4 Yhln4+edGeaMPFr7/jrf0rZfQxdt5jrdeDm03XkngKgEBJyieyc36hkKk vFI0S7UgZG/0j8htu+nyTxvBjghydDiMe0kPafJ72f6xN5Ptaw2uRvby6 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10548"; a="303391882" X-IronPort-AV: E=Sophos;i="5.96,210,1665471600"; d="scan'208";a="303391882" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Dec 2022 11:57:18 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10548"; a="708205126" X-IronPort-AV: E=Sophos;i="5.96,210,1665471600"; d="scan'208";a="708205126" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by fmsmga008.fm.intel.com with ESMTP; 01 Dec 2022 11:57:17 -0800 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-kernel@vger.kernel.org Cc: ak@linux.intel.com, eranian@google.com, irogers@google.com, Kan Liang Subject: [PATCH 6/9] perf/x86/cstate: Add Meteor Lake support Date: Thu, 1 Dec 2022 11:57:01 -0800 Message-Id: <20221201195704.2330866-6-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221201195704.2330866-1-kan.liang@linux.intel.com> References: <20221201195704.2330866-1-kan.liang@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751043204167250914?= X-GMAIL-MSGID: =?utf-8?q?1751043204167250914?= From: Kan Liang Meteor Lake is Intel's successor to Raptor lake. From the perspective of Intel cstate residency counters, there is nothing changed compared with Raptor lake. Share adl_cstates with Raptor lake. Update the comments for Meteor Lake. Reviewed-by: Andi Kleen Signed-off-by: Kan Liang --- arch/x86/events/intel/cstate.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c index a2834bc93149..3019fb1926e3 100644 --- a/arch/x86/events/intel/cstate.c +++ b/arch/x86/events/intel/cstate.c @@ -41,6 +41,7 @@ * MSR_CORE_C1_RES: CORE C1 Residency Counter * perf code: 0x00 * Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL + * MTL * Scope: Core (each processor core has a MSR) * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter * perf code: 0x01 @@ -51,50 +52,50 @@ * perf code: 0x02 * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, * SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX, - * TGL,TNT,RKL,ADL,RPL,SPR + * TGL,TNT,RKL,ADL,RPL,SPR,MTL * Scope: Core * MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter * perf code: 0x03 * Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML, - * ICL,TGL,RKL,ADL,RPL + * ICL,TGL,RKL,ADL,RPL,MTL * Scope: Core * MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter. * perf code: 0x00 * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL, * KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL, - * RPL,SPR + * RPL,SPR,MTL * Scope: Package (physical package) * MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter. * perf code: 0x01 * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL, * GLM,CNL,KBL,CML,ICL,TGL,TNT,RKL, - * ADL,RPL + * ADL,RPL,MTL * Scope: Package (physical package) * MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter. * perf code: 0x02 * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, * SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX, - * TGL,TNT,RKL,ADL,RPL,SPR + * TGL,TNT,RKL,ADL,RPL,SPR,MTL * Scope: Package (physical package) * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter. * perf code: 0x03 * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL, - * KBL,CML,ICL,TGL,RKL,ADL,RPL + * KBL,CML,ICL,TGL,RKL,ADL,RPL,MTL * Scope: Package (physical package) * MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter. * perf code: 0x04 * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL, - * ADL,RPL + * ADL,RPL,MTL * Scope: Package (physical package) * MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter. * perf code: 0x05 * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL, - * ADL,RPL + * ADL,RPL,MTL * Scope: Package (physical package) * MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter. * perf code: 0x06 * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL, - * TNT,RKL,ADL,RPL + * TNT,RKL,ADL,RPL,MTL * Scope: Package (physical package) * */ @@ -686,6 +687,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, &adl_cstates), X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, &adl_cstates), X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, &adl_cstates), + X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE, &adl_cstates), + X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, &adl_cstates), { }, }; MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match); From patchwork Thu Dec 1 19:57:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liang, Kan" X-Patchwork-Id: 28539 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp458957wrr; Thu, 1 Dec 2022 12:02:33 -0800 (PST) X-Google-Smtp-Source: AA0mqf6e3C0jYP0iF8JHWwO+rlVkCcVbjluW36BPSIqaP09aSAU5MlnAn972tmXqsUW2DjYdKvcZ X-Received: by 2002:a17:906:392:b0:7b5:a9df:d83e with SMTP id b18-20020a170906039200b007b5a9dfd83emr46857097eja.358.1669924953711; Thu, 01 Dec 2022 12:02:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669924953; cv=none; d=google.com; s=arc-20160816; b=nGgEWLeHhZuAOCP3IhibaflMI5Pi7Kru/7+GzUKjOfHX+SZrOmMW32XkX2UG3fBlrv FBxXXQVPHMX2XJ8lydPfdTq3oqruSYPEPg8WyjYRCz3Cqp7tttbiAzVLwb3KEbdwNy7w b6OiTHGTs4rg+whWvhZzxHZa9yjAVtuM7PDPsmvVPKUMmaoTj01JfGfvSKbsTrkoExwm X8096OesLT78sZq0G+/bldtKL+SiVNVuDN3FtQGXOtVYhxXlWSTXN6KzCZHMRzIF9zj1 z89eNO6qca78xmBkRsA9nXsA8DyA4dtMx5omH8tydQBluuKIfaG+xvNuTst38USVLFvv xGzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=biJe7bnOr4HIC/8hMgV17HOcIehGfjRivsMR/X9XyI4=; b=EQhEi+nqJ8IYVamb9DgTKKktTGSzsiUDDLW+Yi4w7uqAgWSda4+YKGIMWc/x51RO6a /NIWmRMndDtCMQ5hAiBA1iToaAxeB3cNNWy2pboXTqCobZCUhVP9jMiNiqneqRGeYzoD wnU/cO0gFp5LSwazIwd/Vo+Psap4caWgjAbiVTjY7IQtHXAOG36Eva7VtQjdKdMr8OAi mNVI3DVjVaUyMu2FcNFlCz/LQI9ynLJdCLvuKWucRyJJmy/+nblzUJQtBqrQiiu1A46V bjcqOUNqtvZJ72dXhsN/UPeSFimqPRsF93ZXo43+uMQCLozPTa17Y05wNi4fej/kXgny DC8A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=iPklKJSG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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PPERF and SMI_COUNT MSRs are also supported. Reviewed-by: Andi Kleen Signed-off-by: Kan Liang --- arch/x86/events/msr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index ecced3a52668..074150d28fa8 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -107,6 +107,8 @@ static bool test_intel(int idx, void *data) case INTEL_FAM6_RAPTORLAKE: case INTEL_FAM6_RAPTORLAKE_P: case INTEL_FAM6_RAPTORLAKE_S: + case INTEL_FAM6_METEORLAKE: + case INTEL_FAM6_METEORLAKE_L: if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF) return true; break; From patchwork Thu Dec 1 19:57:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liang, Kan" X-Patchwork-Id: 28542 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp460031wrr; Thu, 1 Dec 2022 12:04:21 -0800 (PST) X-Google-Smtp-Source: AA0mqf6rAi2FWh3V2nSrz5FaFjOKFjnb/1msCmhtnIIXYzHQEO89gA2PBLshOP04IbtQzRkIJv1w X-Received: by 2002:a17:906:698f:b0:78d:93b1:b3ba with SMTP id i15-20020a170906698f00b0078d93b1b3bamr59066458ejr.66.1669925061359; Thu, 01 Dec 2022 12:04:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669925061; cv=none; d=google.com; s=arc-20160816; b=a5/aKmu6E3WMify+WVidzBAVbPEgXGMGGgW0ziPPHA29xZCruDuUakFmrHvd2Zds6A NzmSI1BLfUPyZHH03Qs1isw5LBkzLxOAwildMna6v334hy19hpV6+rkM6JVLVg+sfsEX 51K2FqaNo+yFn7GUHyyQ0OzJI5ZwS2CxnP5kl64zHpFw71mYxpv0TfOXU8uBMtG8brsT C4nKyb3X/NejLNcsUO7iGjOWG1W6krW48czhcTa39jV/RYwDORfI5DOBSRflFZpI3NuF p1gpQTB3bLqqKLnr+PgY1+XkI1CrdYxib1JMgElPOUfbO0szKXP5PfaBnO6+ouC4E12J T0bg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=gc20cfYBMUD5BKGzJlB/SU3dEYX5sShTz3aMcwmRh2I=; b=ZbYRPpUlE3dgEtLbMJmpTFDj/ZBMlafpqgmcLR+0EFyUtm5hU1dr6MHPhOuwr/qElo ZZh5hIRCZHm5hE/qX8zwYyRO45Q9aIq11maBPNePm/qFNpPtxAZZptg3xLtbAQ6txgQ2 liwjc6V40i8ApB4hAHW3hTuLZWWLNbrdBkNy5WG9NVmmNFGh4995ipjHiQkKEimLh7k/ R7xyUvsjR+A61kn8817K773+yebLjQNLwmpdrn5DE1a257Dzid2jwk6Z1fwvDEvJg0TB ND8oKYVAXBzcybBjs+pOISCIKQ72pJEgrCjzbygEpuur7OLPOC5fIyNuL+3yS6K+5w1x R84w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="Twx/sewl"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id xg2-20020a170907320200b00781d302d5e9si962500ejb.166.2022.12.01.12.03.56; Thu, 01 Dec 2022 12:04:21 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="Twx/sewl"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231303AbiLAT5s (ORCPT + 99 others); Thu, 1 Dec 2022 14:57:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52610 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231128AbiLAT5U (ORCPT ); Thu, 1 Dec 2022 14:57:20 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 91E64BA608 for ; Thu, 1 Dec 2022 11:57:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669924639; x=1701460639; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8EH0h7IkhRrGkxUHjtqjdslz6xr6JL2LMam/qGZ9N70=; b=Twx/sewlEKDzKrHcsosw3QNs/0HyUIvPb6KJJp4Qb/vrFIB0vr7kuKVw HDnXCtp242rRILpw1WlVU1bHwAk+h77hfFP4f+LvuKrA9ZfAFWYntWrI5 eYljLOOMVoNwcm9xpvCQOribvB2e+T58J3FgJZTK9W6f04QGGJrpiJSV3 0bvS7rLHecwd8bmuZoS6yhll939JXr5Yo92SyYbUn67MFqQ37bTKebm0e sHdmWuwqGox3bn7ZTLa03vCqE1tCjEQdc+Eid0m5TEwxrxr82xH1aDULK dQuzl0pGfx007fORz+6oHg8RzZcjtUmpVullrqT5qSeYhWEUH+rHbYEwC Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10548"; a="303391896" X-IronPort-AV: E=Sophos;i="5.96,210,1665471600"; d="scan'208";a="303391896" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Dec 2022 11:57:19 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10548"; a="708205157" X-IronPort-AV: E=Sophos;i="5.96,210,1665471600"; d="scan'208";a="708205157" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by fmsmga008.fm.intel.com with ESMTP; 01 Dec 2022 11:57:18 -0800 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-kernel@vger.kernel.org Cc: ak@linux.intel.com, eranian@google.com, irogers@google.com, Kan Liang Subject: [PATCH 8/9] perf report: Support Retire Latency Date: Thu, 1 Dec 2022 11:57:03 -0800 Message-Id: <20221201195704.2330866-8-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221201195704.2330866-1-kan.liang@linux.intel.com> References: <20221201195704.2330866-1-kan.liang@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751043341118625432?= X-GMAIL-MSGID: =?utf-8?q?1751043341118625432?= From: Kan Liang The Retire Latency field is added in the var3_w of the PERF_SAMPLE_WEIGHT_STRUCT. The Retire Latency reports pipeline stall of this instruction compared to the previous instruction in cycles. That's quite useful to display the information with perf mem report. The p_stage_cyc for Power is also from the var3_w. Union the p_stage_cyc and retire_lat to share the code. Implement X86 specific codes to display the X86 specific header. Add a new sort key retire_lat for the Retire Latency. Reviewed-by: Andi Kleen Signed-off-by: Kan Liang --- tools/perf/Documentation/perf-report.txt | 2 ++ tools/perf/arch/x86/util/event.c | 20 ++++++++++++++++++++ tools/perf/util/event.h | 5 ++++- tools/perf/util/sort.c | 2 ++ tools/perf/util/sort.h | 2 ++ 5 files changed, 30 insertions(+), 1 deletion(-) diff --git a/tools/perf/Documentation/perf-report.txt b/tools/perf/Documentation/perf-report.txt index 4533db2ee56b..711396cd3a52 100644 --- a/tools/perf/Documentation/perf-report.txt +++ b/tools/perf/Documentation/perf-report.txt @@ -115,6 +115,8 @@ OPTIONS - p_stage_cyc: On powerpc, this presents the number of cycles spent in a pipeline stage. And currently supported only on powerpc. - addr: (Full) virtual address of the sampled instruction + - retire_lat: On X86, this reports pipeline stall of this instruction compared + to the previous instruction in cycles. And currently supported only on X86 By default, comm, dso and symbol keys are used. (i.e. --sort comm,dso,symbol) diff --git a/tools/perf/arch/x86/util/event.c b/tools/perf/arch/x86/util/event.c index e670f3547581..5f3a5c95f04f 100644 --- a/tools/perf/arch/x86/util/event.c +++ b/tools/perf/arch/x86/util/event.c @@ -87,6 +87,7 @@ void arch_perf_parse_sample_weight(struct perf_sample *data, else { data->weight = weight.var1_dw; data->ins_lat = weight.var2_w; + data->retire_lat = weight.var3_w; } } @@ -100,3 +101,22 @@ void arch_perf_synthesize_sample_weight(const struct perf_sample *data, *array |= ((u64)data->ins_lat << 32); } } + +const char *arch_perf_header_entry(const char *se_header) +{ + if (!strcmp(se_header, "Local Pipeline Stage Cycle")) + return "Local Retire Latency"; + else if (!strcmp(se_header, "Pipeline Stage Cycle")) + return "Retire Latency"; + + return se_header; +} + +int arch_support_sort_key(const char *sort_key) +{ + if (!strcmp(sort_key, "p_stage_cyc")) + return 1; + if (!strcmp(sort_key, "local_p_stage_cyc")) + return 1; + return 0; +} diff --git a/tools/perf/util/event.h b/tools/perf/util/event.h index 12eae6917022..ff3f2892b1e3 100644 --- a/tools/perf/util/event.h +++ b/tools/perf/util/event.h @@ -173,7 +173,10 @@ struct perf_sample { u8 cpumode; u16 misc; u16 ins_lat; - u16 p_stage_cyc; + union { + u16 p_stage_cyc; + u16 retire_lat; + }; bool no_hw_idx; /* No hw_idx collected in branch_stack */ char insn[MAX_INSN]; void *raw_data; diff --git a/tools/perf/util/sort.c b/tools/perf/util/sort.c index 2e7330867e2e..89aee5affe76 100644 --- a/tools/perf/util/sort.c +++ b/tools/perf/util/sort.c @@ -2035,6 +2035,8 @@ static struct sort_dimension common_sort_dimensions[] = { DIM(SORT_LOCAL_PIPELINE_STAGE_CYC, "local_p_stage_cyc", sort_local_p_stage_cyc), DIM(SORT_GLOBAL_PIPELINE_STAGE_CYC, "p_stage_cyc", sort_global_p_stage_cyc), DIM(SORT_ADDR, "addr", sort_addr), + DIM(SORT_LOCAL_RETIRE_LAT, "local_retire_lat", sort_local_p_stage_cyc), + DIM(SORT_GLOBAL_RETIRE_LAT, "retire_lat", sort_global_p_stage_cyc), }; #undef DIM diff --git a/tools/perf/util/sort.h b/tools/perf/util/sort.h index 04ff8b61a2a7..a4aff8437b85 100644 --- a/tools/perf/util/sort.h +++ b/tools/perf/util/sort.h @@ -237,6 +237,8 @@ enum sort_type { SORT_LOCAL_PIPELINE_STAGE_CYC, SORT_GLOBAL_PIPELINE_STAGE_CYC, SORT_ADDR, + SORT_LOCAL_RETIRE_LAT, + SORT_GLOBAL_RETIRE_LAT, /* branch stack specific sort keys */ __SORT_BRANCH_STACK, From patchwork Thu Dec 1 19:57:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liang, Kan" X-Patchwork-Id: 28543 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp460102wrr; Thu, 1 Dec 2022 12:04:29 -0800 (PST) X-Google-Smtp-Source: AA0mqf755HWWdTxxQRi9oVUkrdh6/ODWyW6/j7wQe2HCz8Oq/wtPJiI5EI8Cuq8ywm+9oIU0kv0H X-Received: by 2002:a17:906:3510:b0:781:b7f2:bce9 with SMTP id r16-20020a170906351000b00781b7f2bce9mr58609837eja.269.1669925068985; Thu, 01 Dec 2022 12:04:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669925068; cv=none; d=google.com; s=arc-20160816; b=ebdwqPx27ZioCCEVGrBrTuCSvnSA4v5ijjJfftSzK+xUMZGnJs+CeHWL8I8Pb7qqB3 w2QdNew7cvc25fo55jPBN4WL0SMi1Zh2ZdT/xobO/CnLKSLbbf71fEWowsjeYhjuKjbA eDWL75YKTLFNBZ5WrZXyw3G4xPmenFWCVbAa65Kbgd0xM1IGRkt4WrGkBff5Xqf+LVKB /Xq16gcEiqruncNL3yeyUrdIMSbR5OuQlHG+njHjpY7dpt2418WIYkuJDHR7ayP/xVP9 V30TyVkPa4kC4ydEF0vBUQMQa5cXJp5T+OKaBJk+mr8+FeRwgYVBSUviCNiyqaWCkQ4v Xsjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=CInjWc4Zn/qn1zjefO/qMfJPNe8mAjld2NvB1vVSXdE=; b=CMU7O1CveIKIcQjHohfqmM0/Qxg92PGfwDDIDQp9w6h8rh2wHCBjZx2JBitKYgLACd BDo5e/wfEWfGdj/fopebGTrXQI/4uhGCI6A3+hZZiqZiYuEUPbOwkItjI+Bqa5fq8WcD jq2RTi49HqMyMPLrznSjOMtOCQ3HZNTfzucsmnI666BdZ8BYVeP1Z7Waan1b7a7Ya00f pvzUkwPgJoyVml4mpDtyE/JelA9LOdU4xRm2gjG6rwiPKSlMe5pMU3RISPf7DIcmTcPf CvLYByKmzOXK1ne4KXRKagE9He2pGg/cvTNy4qRG2h6wKRaPogRzw6PfYNSDaoqhhIrC /Atw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=BGYQ8AXS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id nc41-20020a1709071c2900b0073d9c412570si4545308ejc.785.2022.12.01.12.04.02; Thu, 01 Dec 2022 12:04:28 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=BGYQ8AXS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231319AbiLAT5w (ORCPT + 99 others); Thu, 1 Dec 2022 14:57:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52622 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229723AbiLAT5U (ORCPT ); Thu, 1 Dec 2022 14:57:20 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F3B56BA602 for ; Thu, 1 Dec 2022 11:57:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669924640; x=1701460640; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=psXZMKbJQ3yGAryg57Kdkp4DtQsybo7dhx1r47nzioo=; b=BGYQ8AXSleZJ/QFFUN2Bu5ZbDXrHd9U6Znf4aPnoHJFp9H2AshJ/j5+G dbUiEkOflH1H32DZne69qM0ZNIQobgnf/AiyQOjo0AsZ2b8qebDKCoQzn swVQwvkYENr0DyxWlqsmq09HZOSIAYnXFKLs4WUeqCM0cL8aHHIOwuXu7 f6o51/wkg5p3tfy15fqTysC6S7HyMSTc5fb7MQy+IOWsd/I5lATrykiwT 6EliA7w/+yfHQ/w1D9Xv96sfoOiydObA7TPP9NrNlr0mqIbUJVvpsMHHH Bv/pZWhinXCA0aKcrEJtR9bbeVG6IF1RnfrLaEnefv7eB5yolq+g4o1MF Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10548"; a="303391902" X-IronPort-AV: E=Sophos;i="5.96,210,1665471600"; d="scan'208";a="303391902" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Dec 2022 11:57:19 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10548"; a="708205170" X-IronPort-AV: E=Sophos;i="5.96,210,1665471600"; d="scan'208";a="708205170" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by fmsmga008.fm.intel.com with ESMTP; 01 Dec 2022 11:57:19 -0800 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-kernel@vger.kernel.org Cc: ak@linux.intel.com, eranian@google.com, irogers@google.com, Kan Liang Subject: [PATCH 9/9] perf script: Support Retire Latency Date: Thu, 1 Dec 2022 11:57:04 -0800 Message-Id: <20221201195704.2330866-9-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221201195704.2330866-1-kan.liang@linux.intel.com> References: <20221201195704.2330866-1-kan.liang@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751043349030275232?= X-GMAIL-MSGID: =?utf-8?q?1751043349030275232?= From: Kan Liang The Retire Latency field is added in the var3_w of the PERF_SAMPLE_WEIGHT_STRUCT. The Retire Latency reports the number of elapsed core clocks between the retirement of the instruction indicated by the Instruction Pointer field of the PEBS record and the retirement of the prior instruction. That's quite useful to display the information with perf script. Add a new field retire_lat for the Retire Latency information. Reviewed-by: Andi Kleen Signed-off-by: Kan Liang --- tools/perf/builtin-script.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c index 7ca238277d83..071ffdff1980 100644 --- a/tools/perf/builtin-script.c +++ b/tools/perf/builtin-script.c @@ -127,6 +127,7 @@ enum perf_output_field { PERF_OUTPUT_BRSTACKINSNLEN = 1ULL << 36, PERF_OUTPUT_MACHINE_PID = 1ULL << 37, PERF_OUTPUT_VCPU = 1ULL << 38, + PERF_OUTPUT_RETIRE_LAT = 1ULL << 39, }; struct perf_script { @@ -197,6 +198,7 @@ struct output_option { {.str = "brstackinsnlen", .field = PERF_OUTPUT_BRSTACKINSNLEN}, {.str = "machine_pid", .field = PERF_OUTPUT_MACHINE_PID}, {.str = "vcpu", .field = PERF_OUTPUT_VCPU}, + {.str = "retire_lat", .field = PERF_OUTPUT_RETIRE_LAT}, }; enum { @@ -272,7 +274,7 @@ static struct { PERF_OUTPUT_ADDR | PERF_OUTPUT_DATA_SRC | PERF_OUTPUT_WEIGHT | PERF_OUTPUT_PHYS_ADDR | PERF_OUTPUT_DATA_PAGE_SIZE | PERF_OUTPUT_CODE_PAGE_SIZE | - PERF_OUTPUT_INS_LAT, + PERF_OUTPUT_INS_LAT | PERF_OUTPUT_RETIRE_LAT, .invalid_fields = PERF_OUTPUT_TRACE | PERF_OUTPUT_BPF_OUTPUT, }, @@ -539,6 +541,10 @@ static int evsel__check_attr(struct evsel *evsel, struct perf_session *session) evsel__check_stype(evsel, PERF_SAMPLE_WEIGHT_STRUCT, "WEIGHT_STRUCT", PERF_OUTPUT_INS_LAT)) return -EINVAL; + if (PRINT_FIELD(RETIRE_LAT) && + evsel__check_stype(evsel, PERF_SAMPLE_WEIGHT_STRUCT, "WEIGHT_STRUCT", PERF_OUTPUT_RETIRE_LAT)) + return -EINVAL; + return 0; } @@ -2175,6 +2181,9 @@ static void process_event(struct perf_script *script, if (PRINT_FIELD(INS_LAT)) fprintf(fp, "%16" PRIu16, sample->ins_lat); + if (PRINT_FIELD(RETIRE_LAT)) + fprintf(fp, "%16" PRIu16, sample->retire_lat); + if (PRINT_FIELD(IP)) { struct callchain_cursor *cursor = NULL; @@ -3849,7 +3858,7 @@ int cmd_script(int argc, const char **argv) "brstacksym,flags,data_src,weight,bpf-output,brstackinsn," "brstackinsnlen,brstackoff,callindent,insn,insnlen,synth," "phys_addr,metric,misc,srccode,ipc,tod,data_page_size," - "code_page_size,ins_lat", + "code_page_size,ins_lat,retire_lat", parse_output_fields), OPT_BOOLEAN('a', "all-cpus", &system_wide, "system-wide collection from all CPUs"),