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[8.43.85.97]) by mx.google.com with ESMTPS id gn16-20020a1709070d1000b0077ce17dac95si17694864ejc.120.2022.09.19.09.06.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Sep 2022 09:06:08 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=Yn9vcyHQ; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DAB67385841F for ; Mon, 19 Sep 2022 16:06:07 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DAB67385841F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1663603567; bh=oLC4LSBQCIcZHeMkU+BwvDAK9n7bNEXqE65kOmawMl8=; h=Subject:To:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=Yn9vcyHQBQjl2Z8dCAwb3j+uc2jkn3qheUhYCPonx15osKJ8QOgqMTvRukXT86/zg JprJORW0SpFb/cwfAzw698Hm79rkx3qJ92u2urNt9Rxol48mTMA2ruD6u9qH2nTkLv jm2iy6taKph8ZGLbotl8UndYtgLUylatjOKUEdCU= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id D93683858D28 for ; Mon, 19 Sep 2022 16:05:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D93683858D28 Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 28JFfuJf029969; Mon, 19 Sep 2022 16:05:21 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3jpu9s0tng-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 19 Sep 2022 16:05:21 +0000 Received: from m0098410.ppops.net (m0098410.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 28JFh96b002410; Mon, 19 Sep 2022 16:05:21 GMT Received: from ppma02dal.us.ibm.com (a.bd.3ea9.ip4.static.sl-reverse.com [169.62.189.10]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3jpu9s0tmh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 19 Sep 2022 16:05:21 +0000 Received: from pps.filterd (ppma02dal.us.ibm.com [127.0.0.1]) by ppma02dal.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 28JFowId007975; Mon, 19 Sep 2022 16:05:20 GMT Received: from b03cxnp08026.gho.boulder.ibm.com (b03cxnp08026.gho.boulder.ibm.com [9.17.130.18]) by ppma02dal.us.ibm.com with ESMTP id 3jn5v9j23j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 19 Sep 2022 16:05:20 +0000 Received: from b03ledav006.gho.boulder.ibm.com (b03ledav006.gho.boulder.ibm.com [9.17.130.237]) by b03cxnp08026.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 28JG5KNp51249446 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 19 Sep 2022 16:05:20 GMT Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BFB11C605F; Mon, 19 Sep 2022 16:05:17 +0000 (GMT) Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 04A3CC605D; Mon, 19 Sep 2022 16:05:16 +0000 (GMT) Received: from sig-9-77-144-60.ibm.com (unknown [9.77.144.60]) by b03ledav006.gho.boulder.ibm.com (Postfix) with ESMTP; Mon, 19 Sep 2022 16:05:16 +0000 (GMT) Message-ID: Subject: [PATCH, rs6000] Tests of ARCH_PWR8 and -mno-vsx option. (1/2) To: GCC patches Date: Mon, 19 Sep 2022 11:05:17 -0500 X-Mailer: Evolution 3.28.5 (3.28.5-18.el8) Mime-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: FUW314PwqlLIrf06qH2lJqNQcrjO4vfx X-Proofpoint-ORIG-GUID: dDyaWYsAAEgOzsLZeZrYMfRB2jaJtpDr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-19_05,2022-09-16_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 phishscore=0 mlxlogscore=810 bulkscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 adultscore=0 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2209190108 X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: will schmidt via Gcc-patches From: will schmidt Reply-To: will schmidt Cc: David Edelsohn , Segher Boessenkool Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1744414775713881650?= X-GMAIL-MSGID: =?utf-8?q?1744414775713881650?= [PATCH, rs6000] Tests of ARCH_PWR8 and -mno-vsx option. Hi, This adds an assortment of tests to exercise the -mno-vsx option and confirm the impacts on the ARCH_PWR8 define. These are based on and inspired by PR 101865, which reports that _ARCH_PWR8 is disabled when -mno-vsx is passed on the commandline. There are a small number of failures introduced by these tests, those are resolved with the changes in part 2. OK for trunk? Thanks, -Will gcc/testsuite: * gcc.target/powerpc/predefine_p7-novsx.c: New test. * gcc.target/powerpc/predefine_p8-noaltivec-novsx.c: New test. * gcc.target/powerpc/predefine_p8-novsx.c: New test. * gcc.target/powerpc/predefine_p9-novsx.c: New test. * gcc.target/powerpc/predefine_pragma_vsx.c: New test. diff --git a/gcc/testsuite/gcc.target/powerpc/predefine_p7-novsx.c b/gcc/testsuite/gcc.target/powerpc/predefine_p7-novsx.c new file mode 100644 index 000000000000..e842025b4d3c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/predefine_p7-novsx.c @@ -0,0 +1,9 @@ +/* { dg-do preprocess } */ +/* Test whether the ARCH_PWR7 and ARCH_PWR8 defines gets set + * when we specify power7, plus options. +/* This is a variation of the test at issue in GCC PR 101865 */ +/* { dg-options "-dM -E -mdejagnu-cpu=power7 -mno-vsx" } */ +/* { dg-final { scan-file predefine_p7-novsx.i "(^|\\n)#define _ARCH_PWR7 1($|\\n)" } } */ +/* { dg-final { scan-file-not predefine_p7-novsx.i "(^|\\n)#define _ARCH_PWR8 1($|\\n)" } } */ +/* { dg-final { scan-file-not predefine_p7-novsx.i "(^|\\n)#define __VSX__ 1($|\\n)" } } */ +/* { dg-final { scan-file predefine_p7-novsx.i "(^|\\n)#define __ALTIVEC__ 1($|\\n)" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/predefine_p8-noaltivec-novsx.c b/gcc/testsuite/gcc.target/powerpc/predefine_p8-noaltivec-novsx.c new file mode 100644 index 000000000000..c3b705ca3d48 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/predefine_p8-noaltivec-novsx.c @@ -0,0 +1,7 @@ +/* { dg-do preprocess } */ +/* Test whether the ARCH_PWR8 define remains set after disabling both altivec and vsx. */ +/* { dg-options "-dM -E -mdejagnu-cpu=power8 -mno-altivec -mno-vsx" } */ +/* { dg-final { scan-file predefine_p8-noaltivec-novsx.i "(^|\\n)#define _ARCH_PWR8 1($|\\n)" } } */ +/* { dg-final { scan-file-not predefine_p8-noaltivec-novsx.i "(^|\\n)#define _ARCH_PWR9 1($|\\n)" } } */ +/* { dg-final { scan-file-not predefine_p8-noaltivec-novsx.i "(^|\\n)#define __VSX__ 1($|\\n)" } } */ +/* { dg-final { scan-file-not predefine_p8-noaltivec-novsx.i "(^|\\n)#define __ALTIVEC__ 1($|\\n)" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/predefine_p8-novsx.c b/gcc/testsuite/gcc.target/powerpc/predefine_p8-novsx.c new file mode 100644 index 000000000000..8b6c69b20104 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/predefine_p8-novsx.c @@ -0,0 +1,8 @@ +/* { dg-do preprocess } */ +/* Test whether the ARCH_PWR8 define remains set after disabling vsx. + This also confirms __ALTIVEC__ remains set when VSX is disabled. */ +/* This is the primary test at issue in GCC PR 101865 */ +/* { dg-options "-dM -E -mdejagnu-cpu=power8 -mno-vsx" } */ +/* { dg-final { scan-file predefine_p8-novsx.i "(^|\\n)#define _ARCH_PWR8 1($|\\n)" } } */ +/* { dg-final { scan-file-not predefine_p8-novsx.i "(^|\\n)#define __VSX__ 1($|\\n)" } } */ +/* { dg-final { scan-file predefine_p8-novsx.i "(^|\\n)#define __ALTIVEC__ 1($|\\n)" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/predefine_p9-novsx.c b/gcc/testsuite/gcc.target/powerpc/predefine_p9-novsx.c new file mode 100644 index 000000000000..eef42c111663 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/predefine_p9-novsx.c @@ -0,0 +1,10 @@ +/* { dg-do preprocess } */ +/* Test whether the ARCH_PWR8 define remains set after disabling vsx. + This also confirms __ALTIVEC__ remains set when VSX is disabled. */ +/* This is the primary test at issue in GCC PR 101865 */ +/* { dg-options "-dM -E -mdejagnu-cpu=power9 -mno-vsx" } */ +/* {xfail *-*-*} */ +/* { dg-final { scan-file predefine_p9-novsx.i "(^|\\n)#define _ARCH_PWR8 1($|\\n)" } } */ +/* { dg-final { scan-file predefine_p9-novsx.i "(^|\\n)#define _ARCH_PWR9 1($|\\n)" } } */ +/* { dg-final { scan-file-not predefine_p9-novsx.i "(^|\\n)#define __VSX__ 1($|\\n)" } } */ +/* { dg-final { scan-file predefine_p9-novsx.i "(^|\\n)#define __ALTIVEC__ 1($|\\n)" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/predefine_pragma_vsx.c b/gcc/testsuite/gcc.target/powerpc/predefine_pragma_vsx.c new file mode 100644 index 000000000000..b300600af999 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/predefine_pragma_vsx.c @@ -0,0 +1,83 @@ +/* { dg-do run } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ + +/* Ensure that if we set a pragma gcc target for an + older processor, we do not compile builtins that + the older target does not support. */ + +#include +#include +#include + +volatile int power8_set; +volatile int vsx_set; + +void reset_values() { + vsx_set=0; + power8_set=0; +} + +void test_default() { + reset_values(); +#ifdef _ARCH_PWR8 + power8_set=1; +#endif +#ifdef __VSX__ + vsx_set=1; +#endif +} + +#pragma GCC target "no-vsx" +void test_no_vsx() { + reset_values(); +#ifdef _ARCH_PWR8 + power8_set=1; +#endif +#ifdef __VSX__ + vsx_set=1; +#endif +} + +#pragma GCC reset_options +void test_reset_options() { + reset_values(); +#ifdef _ARCH_PWR8 + power8_set=1; +#endif +#ifdef __VSX__ + vsx_set=1; +#endif +} + +int main (int argc, char *argv []) { + test_default(); + if (!power8_set) { + printf("_ARCH_PWR8 is not set.\n"); + abort(); + } + if (!vsx_set) { + printf("__VSX__ is not set.\n"); + abort(); + } + test_no_vsx(); + if (!power8_set) { + printf("_ARCH_PWR8 is not set.\n"); + abort(); + } + if (vsx_set) { + printf("__VSX__ is unexpectedly set.\n"); + abort(); + } + test_reset_options(); + if (!power8_set) { + printf("_ARCH_PWR8 is not set.\n"); + abort(); + } + if (!vsx_set) { + printf("__VSX__ is not set.\n"); + abort(); + } +} +