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[2620:137:e000::1:20]) by mx.google.com with ESMTP id 140-20020a621692000000b0056ae8f6df38si4222119pfw.180.2022.12.01.04.30.00; Thu, 01 Dec 2022 04:30:14 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=IbIBAuYc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231339AbiLAMPn (ORCPT + 99 others); Thu, 1 Dec 2022 07:15:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229671AbiLAMPk (ORCPT ); Thu, 1 Dec 2022 07:15:40 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2EB94A3234; Thu, 1 Dec 2022 04:15:33 -0800 (PST) X-UUID: 0561e8f6b4514d44a45d504d8f1b01a9-20221201 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=zwCnPW0NbYvNEoaTQBbhYwyaePWVmhmcxuF1yC02UB0=; b=IbIBAuYc9TMXt0jzHOuWkAtpaNd9kchUYcOAxNmspN7IYCN77khC0puJuuz6aI9JCoLFoHJ/9sJKQhmBWUAZetyGe2H/b8Tj+0bibO9a3vDHtgcaktImcfxgjyAs7+c1+mIiG7YoYT7V7LOguCivWAjQIJ7VVAoOFnE/bwhRCbc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:339b82df-2751-4142-8483-ebb76f9a5dba,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:dcaaed0,CLOUDID:1785df1e-5e1d-4ab5-ab8e-3e04efc02b30,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 0561e8f6b4514d44a45d504d8f1b01a9-20221201 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 811997823; Thu, 01 Dec 2022 20:15:28 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 1 Dec 2022 20:15:27 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 1 Dec 2022 20:15:26 +0800 From: Yunfei Dong To: Yunfei Dong , Rob Herring , Chen-Yu Tsai , Hans Verkuil , AngeloGioacchino Del Regno , Benjamin Gaignard , Tiffany Lin CC: Mauro Carvalho Chehab , Matthias Brugger , Hsin-Yi Wang , Daniel Vetter , Steve Cho , , , , , , Subject: [PATCH v3,1/3] media: dt-bindings: media: mediatek: vcodec: Fix clock num not correctly Date: Thu, 1 Dec 2022 20:15:22 +0800 Message-ID: <20221201121525.30777-1-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, T_SPF_TEMPERROR,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751014770433151202?= X-GMAIL-MSGID: =?utf-8?q?1751014770433151202?= From: Yunfei Dong mt8195 and mt8192 have different clock numbers, can't write 'clocks' and 'clock-names' with const value. Signed-off-by: Yunfei Dong --- Reference series: [1]: v5 of this series is presend by Allen-KH Cheng. message-id: 20221128143832.25584-4-allen-kh.cheng@mediatek.com --- .../bindings/media/mediatek,vcodec-subdev-decoder.yaml | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml index 7c5b4a91c59b..09781ef02193 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml @@ -110,15 +110,12 @@ patternProperties: Refer to bindings/iommu/mediatek,iommu.yaml. clocks: + minItems: 1 maxItems: 5 clock-names: - items: - - const: sel - - const: soc-vdec - - const: soc-lat - - const: vdec - - const: top + minItems: 1 + maxItems: 5 assigned-clocks: maxItems: 1 From patchwork Thu Dec 1 12:15:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?WXVuZmVpIERvbmcgKOiRo+S6kemjnik=?= X-Patchwork-Id: 28347 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp232492wrr; Thu, 1 Dec 2022 04:30:47 -0800 (PST) X-Google-Smtp-Source: AA0mqf6JpINgsGdMusV2xQvXn7rZA4+xq9weocUZ8oP6pTtfAmvV+zaK9+6dp5xVwvYeMOZMhSYW X-Received: by 2002:a17:903:32cd:b0:178:32b9:6f4f with SMTP id i13-20020a17090332cd00b0017832b96f4fmr47548313plr.94.1669897847439; Thu, 01 Dec 2022 04:30:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669897847; cv=none; d=google.com; s=arc-20160816; b=oQL1BA7X11xfOWO+Q6kX8XEO0K5Q5ZbMPMXDNyOG7Mb+frDZUtbv9FKftUCsOtpOcq +sfw4y2Ahvq5R7MOr2uGS2JNeSgPTi3Nh2/z7175iCLRSWkrneZYCjuUeEZGntrVmcYb HX4ZX72TNCTqzsSzsvgz+4fEcUnUqKJwSPXUHhT4mh4Mt4mtUckFAeS/Ji4fFpYWFu4s Zx7JR5Lko/dqSGIhaCNvjSXzk+mpA1jxmwWHMkc1YuHib6Dmo4Ut9tJasC0UgHLLHWim XYeJYPdsCniZUeHGFKcMCk59C2sfTk6lTC/k8dN+OiJ1y3EJl9bAdRHGIpthhRA/Ucjl 63hg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=v3BHYtdynVQ1ED8tKvYbtEtKnY+thsCLl4FMBWcFSww=; b=U48oCqAlDbNPkehv+d5zp1KGnEdqNM4h0oWWgpQGOqw8FYpwwT3kp9//mcwtELlVRp 0IK+9dPH/vic4UXIsArU4HFOsRzUYwpOgw8jaVgORjGdLoeAkzq00q9EYmnO2t6fEOef N4uGGaoKc0m8RRcAac44GvuAOzXY7loYMBF8rlSPSDKpCqFs+BLCcHdxWLscYmMtDbpz cyRVW/U1GK+lOmO9VhXdbKBsSdq54rXomX31wsklJ6rtUiZwXUhir4DL3tSq4X99Pc9K MNgCXIz19rNdK3eZ/rC2HXhC+mtBbyU2XrPT1OTOqXLo3eManneRlm2tDfFGeeWAWTAs dtWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=Bhblt4lU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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Changing the max reg value from 1 to 2. Signed-off-by: Yunfei Dong Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring --- .../bindings/media/mediatek,vcodec-subdev-decoder.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml index 09781ef02193..d20ef15147a4 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml @@ -61,7 +61,10 @@ properties: - mediatek,mt8195-vcodec-dec reg: - maxItems: 1 + minItems: 1 + items: + - description: VDEC_SYS register space + - description: VDEC_RACING_CTRL register space iommus: minItems: 1 @@ -98,6 +101,7 @@ patternProperties: reg: maxItems: 1 + description: VDEC_MISC register space interrupts: maxItems: 1 From patchwork Thu Dec 1 12:15:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?WXVuZmVpIERvbmcgKOiRo+S6kemjnik=?= X-Patchwork-Id: 28348 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp232717wrr; Thu, 1 Dec 2022 04:31:12 -0800 (PST) X-Google-Smtp-Source: AA0mqf5HlezcpuqDvXlcUMF0LPWuWsPHbew4shPeKISlsui5REr+u3jRRWY6HHJEilXgFjqnON8k X-Received: by 2002:a63:5a48:0:b0:478:5981:69e6 with SMTP id k8-20020a635a48000000b00478598169e6mr7987973pgm.398.1669897871803; Thu, 01 Dec 2022 04:31:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669897871; cv=none; d=google.com; s=arc-20160816; b=m3pNw28J24LAmxulZnXsf57CA0jY2kUqvfmt0p/j/NOLz2jFnFHi+JLXK2tqi7RY1N nFsrojyHwZ3tGqMQYtEX3ndm2M9nHBeCgJpRV8arSNJs6tn3VERvk3OyiaCApIm+EVm6 9DeSpiiqaJ+fixJhWCzogQzbPjF2EjEdNCTwc6xLG91MzEASYCVZKpkQ9ZtWjW8uWegV xwsKo21bHS9UuutnI73/YvNrdbTIGLutnu3p2Bj18EI1ZAJfXjhLUrmV8kvpmJspxoc3 MGWYVzorBioEradkRTNElwf6z9SXAhHOc5L3VPqB5kLZbAGtrTEkktsBEHVz5nSinx2d VG1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=RxbOQ6p3JJB3+Vds4c+Jn49mpu7Mr7VeBd2xkXe4ZDo=; b=JOyEFEtgx4XBVWjjVky2EQ7tNHsxbWvW5OmycJ5Z/1ws8ZeDRbw+oIPvABvKN/NTkH v48Own3FLAb+wlDsH4lqsEM4cB8dX/ohtAhPzrWAjt60fQ2TkhoFlK3Oq/LTX64v0tlP nV3VFZ47eYHVbAFUAKGToIDB8uiZAMPNvcfTW3ogd+zZE417RoRyI0W2pqOaBMTZbbt/ zvo3YZ7dCHQvsKzU1zTVB/BIAXNuzLS8NWOFAPPt/rCPYH47NnEuDNPEHMXgpNxH9wdc 8e75SjYJ4HfhYtl5z7/r7b9NlDV+AtG8ViASWq6wX3lH9IKzS8NUGKB+0ydTa/goQA6b TtNw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=uqAOUFs2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id z12-20020aa785cc000000b0056b86567ce9si3993076pfn.347.2022.12.01.04.30.56; Thu, 01 Dec 2022 04:31:11 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=uqAOUFs2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231365AbiLAMPs (ORCPT + 99 others); Thu, 1 Dec 2022 07:15:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55962 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229617AbiLAMPn (ORCPT ); Thu, 1 Dec 2022 07:15:43 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75111A323C; Thu, 1 Dec 2022 04:15:38 -0800 (PST) X-UUID: a6a40983785b42de9f34123721743fbd-20221201 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=RxbOQ6p3JJB3+Vds4c+Jn49mpu7Mr7VeBd2xkXe4ZDo=; b=uqAOUFs2qz3cX7mOxvwYStHnOGqy/TnAB0xKdXhKGC3+PEmd8pReZyeKTXof6j+EtmDbiDE9jev1tzRYYnjAzxfgTXH6w0viBtY0Y/KjDfSeNsEvLdaNNd/B1BS93yuPz2PYKMFuMJPGusshI4puuH4gUnrn6HBO0v+hipt6Gtc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:ff539a9f-9e93-457d-a979-86f0faa48cf4,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:dcaaed0,CLOUDID:dee0466c-41fe-47b6-8eb4-ec192dedaf7d,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: a6a40983785b42de9f34123721743fbd-20221201 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1976456684; Thu, 01 Dec 2022 20:15:30 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 1 Dec 2022 20:15:29 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 1 Dec 2022 20:15:28 +0800 From: Yunfei Dong To: Yunfei Dong , Rob Herring , Chen-Yu Tsai , Hans Verkuil , AngeloGioacchino Del Regno , Benjamin Gaignard , Tiffany Lin CC: Mauro Carvalho Chehab , Matthias Brugger , Hsin-Yi Wang , Daniel Vetter , Steve Cho , , , , , , Subject: [PATCH v3,3/3] arm64: dts: mt8195: Add video decoder node Date: Thu, 1 Dec 2022 20:15:24 +0800 Message-ID: <20221201121525.30777-3-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221201121525.30777-1-yunfei.dong@mediatek.com> References: <20221201121525.30777-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751014830549259314?= X-GMAIL-MSGID: =?utf-8?q?1751014830549259314?= From: Yunfei Dong Add video decoder node to mt8195 device tree. Signed-off-by: Yunfei Dong Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 70 ++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 905d1a90b406..2f6f87a8e90b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1874,6 +1874,76 @@ power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; }; + video-codec@18000000 { + compatible = "mediatek,mt8195-vcodec-dec"; + mediatek,scp = <&scp>; + iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>; + #address-cells = <2>; + #size-cells = <2>; + reg = <0 0x18000000 0 0x1000>, + <0 0x18004000 0 0x1000>; + ranges = <0 0 0 0x18000000 0 0x26000>; + + video-codec@2000 { + compatible = "mediatek,mtk-vcodec-lat-soc"; + reg = <0 0x2000 0 0x800>; + iommus = <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>, + <&iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT>; + clocks = <&topckgen CLK_TOP_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D4>; + clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", "vdec-top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; + }; + + video-codec@10000 { + compatible = "mediatek,mtk-vcodec-lat"; + reg = <0 0x10000 0 0x800>; + interrupts = ; + iommus = <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>; + clocks = <&topckgen CLK_TOP_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D4>; + clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", "vdec-top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; + }; + + video-codec@25000 { + compatible = "mediatek,mtk-vcodec-core"; + reg = <0 0x25000 0 0x1000>; /* VDEC_CORE_MISC */ + interrupts = ; + iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_UFO_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PP_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PRED_RD_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PRED_WR_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PPWRAP_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_TILE_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_VLD_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_VLD2_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_AVC_MV_EXT>; + clocks = <&topckgen CLK_TOP_VDEC>, + <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D4>; + clock-names = "vdec-sel", "vdec-vdec", "vdec-lat", "vdec-top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; + }; + }; + larb24: larb@1800d000 { compatible = "mediatek,mt8195-smi-larb"; reg = <0 0x1800d000 0 0x1000>;