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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id dn15-20020a17090794cf00b0078d148dafa3si3003925ejc.329.2022.11.30.19.05.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Nov 2022 19:05:42 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=kxVoorzf; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id EA9D63858417 for ; Thu, 1 Dec 2022 03:05:40 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org EA9D63858417 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1669863941; bh=4pjxNSmozlnOR0zMBf8WIw1VXNo261GtNL6SocRWHCE=; h=To:CC:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=kxVoorzfY3ZUJTpY4ShmGofb3JsHqIikttT0baWu1Xiacj8yeX9zjzVMbeU1xEMqM p8hYXvOY5cq91kHw29lZwWFLdhQOw2Z38lv3UDjmrop2yu7ikXAzBlrQbNSm9SMhC/ hhTVMgdSjGY4v+5ekYMCbcf7isx0uEz/18mSWFFY= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtp-fw-9103.amazon.com (smtp-fw-9103.amazon.com [207.171.188.200]) by sourceware.org (Postfix) with ESMTPS id 1A7323858C54 for ; Thu, 1 Dec 2022 03:04:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 1A7323858C54 X-Amazon-filename: 0001-AArch64-Add-UNSPECV_PATCHABLE_AREA-PR98776.patch X-IronPort-AV: E=Sophos;i="5.96,207,1665446400"; d="scan'208,217,223";a="1079125799" Received: from pdx4-co-svc-p1-lb2-vlan3.amazon.com (HELO email-inbound-relay-pdx-2b-m6i4x-cadc3fbd.us-west-2.amazon.com) ([10.25.36.214]) by smtp-border-fw-9103.sea19.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Dec 2022 03:04:53 +0000 Received: from EX13MTAUWC002.ant.amazon.com (pdx1-ws-svc-p6-lb9-vlan2.pdx.amazon.com [10.236.137.194]) by email-inbound-relay-pdx-2b-m6i4x-cadc3fbd.us-west-2.amazon.com (Postfix) with ESMTPS id E469DA0B77; Thu, 1 Dec 2022 03:04:52 +0000 (UTC) Received: from EX19D001UWB002.ant.amazon.com (10.13.138.54) by EX13MTAUWC002.ant.amazon.com (10.43.162.240) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 1 Dec 2022 03:04:52 +0000 Received: from EX19D001UWB002.ant.amazon.com (10.13.138.54) by EX19D001UWB002.ant.amazon.com (10.13.138.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA) id 15.2.1118.20; Thu, 1 Dec 2022 03:04:52 +0000 Received: from EX19D001UWB002.ant.amazon.com ([fe80::228:5f96:8949:28b8]) by EX19D001UWB002.ant.amazon.com ([fe80::228:5f96:8949:28b8%7]) with mapi id 15.02.1118.020; Thu, 1 Dec 2022 03:04:52 +0000 To: "gcc-patches@gcc.gnu.org" CC: "sebpop@gmail.com" , Kyrylo Tkachov , Richard Sandiford Subject: AArch64: Add UNSPECV_PATCHABLE_AREA [PR98776] Thread-Topic: AArch64: Add UNSPECV_PATCHABLE_AREA [PR98776] Thread-Index: AQHZBTCTBfQC3+DIFk6eavlOh3NJyw== Date: Thu, 1 Dec 2022 03:04:52 +0000 Message-ID: <3b2be13be3534681af5a64b8163a3c8c@amazon.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: x-originating-ip: [10.43.162.134] MIME-Version: 1.0 X-Spam-Status: No, score=-17.9 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, HTML_MESSAGE, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Pop, Sebastian via Gcc-patches" From: "Li, Pan2 via Gcc-patches" Reply-To: "Pop, Sebastian" Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750979252468526602?= X-GMAIL-MSGID: =?utf-8?q?1750979252468526602?= Hi, Currently patchable area is at the wrong place on AArch64. It is placed immediately after function label, before .cfi_startproc. This patch adds UNSPECV_PATCHABLE_AREA for pseudo patchable area instruction and modifies aarch64_print_patchable_function_entry to avoid placing patchable area before .cfi_startproc. The patch passed bootstrap and regression test on aarch64-linux. Ok to commit to trunk and backport to active release branches? Thanks, Sebastian gcc/ PR target/93492 * config/aarch64/aarch64-protos.h (aarch64_output_patchable_area): Declared. * config/aarch64/aarch64.cc (aarch64_print_patchable_function_entry): Emit an UNSPECV_PATCHABLE_AREA pseudo instruction. (aarch64_output_patchable_area): New. * config/aarch64/aarch64.md (UNSPECV_PATCHABLE_AREA): New. (patchable_area): Define. gcc/testsuite/ PR target/93492 * gcc.target/aarch64/pr98776.c: New. From b9cf87bcdf65f515b38f1851eb95c18aaa180253 Mon Sep 17 00:00:00 2001 From: Sebastian Pop Date: Wed, 30 Nov 2022 19:45:24 +0000 Subject: [PATCH] AArch64: Add UNSPECV_PATCHABLE_AREA [PR98776] Currently patchable area is at the wrong place on AArch64. It is placed immediately after function label, before .cfi_startproc. This patch adds UNSPECV_PATCHABLE_AREA for pseudo patchable area instruction and modifies aarch64_print_patchable_function_entry to avoid placing patchable area before .cfi_startproc. gcc/ PR target/93492 * config/aarch64/aarch64-protos.h (aarch64_output_patchable_area): Declared. * config/aarch64/aarch64.cc (aarch64_print_patchable_function_entry): Emit an UNSPECV_PATCHABLE_AREA pseudo instruction. (aarch64_output_patchable_area): New. * config/aarch64/aarch64.md (UNSPECV_PATCHABLE_AREA): New. (patchable_area): Define. gcc/testsuite/ PR target/93492 * gcc.target/aarch64/pr98776.c: New. --- gcc/config/aarch64/aarch64-protos.h | 2 ++ gcc/config/aarch64/aarch64.cc | 24 +++++++++++++++++++++- gcc/config/aarch64/aarch64.md | 14 +++++++++++++ gcc/testsuite/gcc.target/aarch64/pr98776.c | 11 ++++++++++ 4 files changed, 50 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/pr98776.c diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index 4be93c93c26..2fba24d947d 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -1074,4 +1074,6 @@ const char *aarch64_indirect_call_asm (rtx); extern bool aarch64_harden_sls_retbr_p (void); extern bool aarch64_harden_sls_blr_p (void); +extern void aarch64_output_patchable_area (unsigned int, bool); + #endif /* GCC_AARCH64_PROTOS_H */ diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index e97f3b32f7c..e84b33b958c 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -22684,7 +22684,29 @@ aarch64_print_patchable_function_entry (FILE *file, asm_fprintf (file, "\thint\t34 // bti c\n"); } - default_print_patchable_function_entry (file, patch_area_size, record_p); + if (cfun->machine->label_is_assembled) + { + rtx pa = gen_patchable_area (GEN_INT (patch_area_size), + GEN_INT (record_p)); + basic_block bb = ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb; + rtx_insn *insn = emit_insn_before (pa, BB_HEAD (bb)); + INSN_ADDRESSES_NEW (insn, -1); + } + else + { + default_print_patchable_function_entry (file, patch_area_size, + record_p); + } +} + +/* Output patchable area. */ + +void +aarch64_output_patchable_area (unsigned int patch_area_size, bool record_p) +{ + default_print_patchable_function_entry (asm_out_file, + patch_area_size, + record_p); } /* Implement ASM_OUTPUT_DEF_FROM_DECLS. Output .variant_pcs for aliases. */ diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 76b6898ca04..6501503eb25 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -303,6 +303,7 @@ UNSPEC_TAG_SPACE ; Translate address to MTE tag address space. UNSPEC_LD1RO UNSPEC_SALT_ADDR + UNSPECV_PATCHABLE_AREA ]) (define_c_enum "unspecv" [ @@ -7821,6 +7822,19 @@ [(set_attr "type" "ls64")] ) +(define_insn "patchable_area" + [(unspec_volatile [(match_operand 0 "const_int_operand") + (match_operand 1 "const_int_operand")] + UNSPECV_PATCHABLE_AREA)] + "" +{ + aarch64_output_patchable_area (INTVAL (operands[0]), + INTVAL (operands[1]) != 0); + return ""; +} + [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))] +) + ;; AdvSIMD Stuff (include "aarch64-simd.md") diff --git a/gcc/testsuite/gcc.target/aarch64/pr98776.c b/gcc/testsuite/gcc.target/aarch64/pr98776.c new file mode 100644 index 00000000000..b075b8f75ef --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr98776.c @@ -0,0 +1,11 @@ +/* { dg-do "compile" } */ +/* { dg-options "-O1 -fpatchable-function-entry=1 -fasynchronous-unwind-tables" } */ + +/* Test the placement of the .LPFE0 label. */ + +void +foo (void) +{ +} + +/* { dg-final { scan-assembler "\t\.cfi_startproc\n.*\.LPFE0:\n\tnop\n\tret\n" } } */ -- 2.37.1