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Peter Anvin" Subject: [PATCH kernel 1/3] x86/amd/dr_addr_mask: Cache values in percpu variables Date: Thu, 1 Dec 2022 13:19:46 +1100 Message-ID: <20221201021948.9259-2-aik@amd.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221201021948.9259-1-aik@amd.com> References: <20221201021948.9259-1-aik@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT115:EE_|CY8PR12MB7610:EE_ X-MS-Office365-Filtering-Correlation-Id: 9d418dcf-13e6-4d0d-99af-08dad342a645 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: JbPmWF9OQ4dUoAh6eLdQ+K9rrflc7V3sN3hR5FFUn6Mkk30Y/4Cuc6noMV9yMqqBEI4OacR4rOQMhmTwmWBfLsQUuF8JDPuJAUxdHo8dWv7b3jWOKJcmOkgCTtb3y0yL7/tyIiw0hS3NrDm/lV05oCHSGXu75ChXS0fdiLPKt9aVFncQYMVQWECj9M9hxibxcggT0BEFirhEGGwc92GIwXzXcpe+NRy0IRBC8jYUmOg6+4U6NQu7TLirIJD4yhkc336//dGU78/M5Qztjoa4JOamIclDJi4VaS2Djh9HzFhVL/pKNWFUmtEQPyyeYwK8mchESUoDB6sFOu8gwcezhEh5ruZfgwWXJU/GB9S27XlTjM0oudZYG9pxNn1fmcA495sL+3SSoDstYKyBjTTOMi2DkDtILF1gL5DHk1UTgtQjNQC6DXY5fxvMsDRj3OYuDUBqkfHxEENm4BdEWCj68dauyQMCmYp4O0N4keXOvZwcYE1u4EWzp7Fm51w+ouvVCV6OazyHvgThO6xgqSG/1LgFx588+2bWKTt8BJDIirn5DqxVcJFvcjgRcYVvV0M0rx/YDq7Gk4SKNEGkcBiepx2kDf2tFHf0IqGKjNe58tDnxEptFkEb9VNCSrP6wsxBsu+d0egCK5Web3zgDcJi14YD4EQHw0BRjdTNUvGQjHgqUCK/NkFoxVcsdy32FnWg43hqFTf3QpuA+jW1xqemxiAREeUh6azOVAgrmu5rDQA= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(376002)(346002)(136003)(396003)(451199015)(40470700004)(36840700001)(46966006)(7049001)(7416002)(5660300002)(26005)(54906003)(8936002)(316002)(6862004)(8676002)(4326008)(36756003)(37006003)(36860700001)(70586007)(41300700001)(83380400001)(40460700003)(40480700001)(81166007)(356005)(47076005)(82740400003)(478600001)(6666004)(2616005)(426003)(70206006)(82310400005)(336012)(186003)(16526019)(1076003)(2906002)(6200100001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2022 02:20:43.6759 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9d418dcf-13e6-4d0d-99af-08dad342a645 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT115.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7610 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750976564670500730?= X-GMAIL-MSGID: =?utf-8?q?1750976564670500730?= Reading DR[0-3]_ADDR_MASK MSRs takes about 250 cycles which is going to be noticeable when the AMD KVM SEV-ES's DebugSwap feature is enabled and KVM needs to store these before switching to a guest; the DebugSwitch hardware support restores them as type B swap. This stores MSR values from set_dr_addr_mask() in percpu values and returns them via new get_dr_addr_mask(). The gain here is about 10x. Signed-off-by: Alexey Kardashevskiy --- arch/x86/include/asm/debugreg.h | 1 + arch/x86/kernel/cpu/amd.c | 32 ++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/arch/x86/include/asm/debugreg.h b/arch/x86/include/asm/debugreg.h index cfdf307ddc01..c4324d0205b5 100644 --- a/arch/x86/include/asm/debugreg.h +++ b/arch/x86/include/asm/debugreg.h @@ -127,6 +127,7 @@ static __always_inline void local_db_restore(unsigned long dr7) #ifdef CONFIG_CPU_SUP_AMD extern void set_dr_addr_mask(unsigned long mask, int dr); +extern unsigned long get_dr_addr_mask(int dr); #else static inline void set_dr_addr_mask(unsigned long mask, int dr) { } #endif diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index c75d75b9f11a..ec7efcef4e14 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -1158,6 +1158,11 @@ static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) return false; } +DEFINE_PER_CPU_READ_MOSTLY(unsigned long, dr0_addr_mask); +DEFINE_PER_CPU_READ_MOSTLY(unsigned long, dr1_addr_mask); +DEFINE_PER_CPU_READ_MOSTLY(unsigned long, dr2_addr_mask); +DEFINE_PER_CPU_READ_MOSTLY(unsigned long, dr3_addr_mask); + void set_dr_addr_mask(unsigned long mask, int dr) { if (!boot_cpu_has(X86_FEATURE_BPEXT)) @@ -1166,17 +1171,44 @@ void set_dr_addr_mask(unsigned long mask, int dr) switch (dr) { case 0: wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0); + per_cpu(dr0_addr_mask, smp_processor_id()) = mask; break; case 1: + wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0); + per_cpu(dr1_addr_mask, smp_processor_id()) = mask; + break; case 2: + wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0); + per_cpu(dr2_addr_mask, smp_processor_id()) = mask; + break; case 3: wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0); + per_cpu(dr3_addr_mask, smp_processor_id()) = mask; break; default: break; } } +unsigned long get_dr_addr_mask(int dr) +{ + if (!boot_cpu_has(X86_FEATURE_BPEXT)) + return 0; + + switch (dr) { + case 0: + return per_cpu(dr0_addr_mask, smp_processor_id()); + case 1: + return per_cpu(dr1_addr_mask, smp_processor_id()); + case 2: + return per_cpu(dr2_addr_mask, smp_processor_id()); + case 3: + return per_cpu(dr3_addr_mask, smp_processor_id()); + } + return 0; +} +EXPORT_SYMBOL_GPL(get_dr_addr_mask); + u32 amd_get_highest_perf(void) { struct cpuinfo_x86 *c = &boot_cpu_data; From patchwork Thu Dec 1 02:19:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Kardashevskiy X-Patchwork-Id: 28157 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp35892wrr; Wed, 30 Nov 2022 18:43:41 -0800 (PST) X-Google-Smtp-Source: AA0mqf7uNZRi1psQUtN2h+70eAJBj3oQTZ3PbmNnG+eqjnIyfsX7eX1XTqRGubT7eJ0Dw3usJPN0 X-Received: by 2002:a17:906:1c8c:b0:7c0:a864:5b0f with SMTP id g12-20020a1709061c8c00b007c0a8645b0fmr2764192ejh.105.1669862621185; Wed, 30 Nov 2022 18:43:41 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1669862621; cv=pass; d=google.com; s=arc-20160816; b=d8/TGHGmy8XPQwf5G2zYOWGdoAihhR37i84BuBU2WlfpWcD7Yb2WvQ23cXYwh5ha61 9pjxFG9jV3swj3VwSs3Sl5VF6n8jDMLKsOP+y+ZkrSB9Q5WTWGbvm4rAAmzlM/LV1LqO tIiJCzEPMywSWVOH5tKuP83V7C+FJ1WtFX9DpMfikINj3Vd+vdxQVWla8Jzhh8Tz3eWa a7Z2gm+ao2fp1QfP+TX1OC+fkYcHPTqQh2D3frFny1D04KPflWlHovb+PaIwviupTeDL iayzPQbuqYMW4jld0sT3C4/NUI8KauuXUVDHrz4lwe2mPn5JOTsinTfY4jE/YXcFQzm8 WnwA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=vvpsGEy0dTdwjyf//mnuhS0A9/wySxSByVe+FFVMqvQ=; b=ZTbL4VjZVezgr64Bpd2QXNrlYO5H1FtYY8Gm9bhW0b/gpMeDqQTzG5iwQ1wcub27G6 46PKTPD8qgJzp5qekw3lo3rBfx0hOdG9R7OxYIDkWdkTychlnseW+D4uFWT2AEdaJ/2e XlZNHKIEhMSa/TSXwZLMNXh5S4HhzgVD+brbpgxSoa9F72EDdxfGkh+ac03HYxoaF5Jw oWxbGuDcFxeK4AMNoEo3R2/McbCxbI9KV2TfDgAx1JGDofa+U5Ca3sbuHD8Oumm2DMJ7 Wbay2VnXBypvLCbX7bma1JtI7JzG9jeKOWK632XZhZDcdf7NFSDRpNU7tMHYYm93UF8V v4cw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=UxoZqmAL; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" Subject: [PATCH kernel 2/3] KVM: SEV: Enable DebugSwap Date: Thu, 1 Dec 2022 13:19:47 +1100 Message-ID: <20221201021948.9259-3-aik@amd.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221201021948.9259-1-aik@amd.com> References: <20221201021948.9259-1-aik@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT055:EE_|DM6PR12MB4563:EE_ X-MS-Office365-Filtering-Correlation-Id: 934911da-7f8b-42a5-bcc4-08dad342bb92 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rvMkPOgMT+iZdjrRbrdE5fdv8QKyVvWPO6G5+U9ZzS9R6PfwGmDpZpnaFRgRu7thaizuXp4n6UywoFboMphUjTEXrVlDrYEYzZq4/HOUOmmsmb+iiBu8kBHlo0xOKrv6O8d1WjuDovdmu16WAS3nmuTDxSChrdqlYzZB5qzX5E43q2CE1GevnyJSoREUB5VvCLZt714l4xTZyVjVkclUIvr1bbqTioLTz8H5E5S30xfepF1d+BXs59QNwKNk4euonesCdRJG7yqqcZzvvbEdpDPBcU4OXSGQFcPOC1vTk8YnEWWPtHq1ohGD1DMhlY0HhoAPlMkYPIAU6BuemWFUws3dEslebyUfgJo/lqGYj/Nr5QJk6CF/+R6RYJBuAct0C3jMKOt9M3rIhIb8/lsEPV2fwcFK2FkWPbIERPO4axWN3/y6+/vi4q9/G4r6xaNzR1O4W95cd8Ut3bn7M1ZrDjDIb0j5jJV91KsdauoDyQU3j+mhUm62aasOlowGTecj4V8cA64AqFZRHjUuOXhBKiqhqpz+8WtYwTsMTWIQ4gch4hSu9yWNp7WtIi4SOUgbAYRQzJfgTRRx2I6/e7jm9ksOhHrQw1yng1LwCTUcI7rN+6ufSebqZcJ8vBsgeAWDtS+3U345nBvs5HL6zkG19ahMauSNLJjrLb3dImCvyH2TrrFnHjJJLn8cxADxAYPVbtdMW3Y7Q4BPnGdZbvpqBUxOYACaGfTXHZi5yWtd9RM= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(39860400002)(376002)(346002)(396003)(451199015)(40470700004)(46966006)(36840700001)(356005)(81166007)(40480700001)(7049001)(36756003)(40460700003)(6200100001)(478600001)(26005)(6666004)(7416002)(5660300002)(41300700001)(8936002)(4326008)(6862004)(54906003)(37006003)(2906002)(316002)(70586007)(70206006)(8676002)(36860700001)(82310400005)(82740400003)(336012)(16526019)(186003)(1076003)(2616005)(83380400001)(426003)(47076005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2022 02:21:19.4136 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 934911da-7f8b-42a5-bcc4-08dad342bb92 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT055.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4563 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750977867539478938?= X-GMAIL-MSGID: =?utf-8?q?1750977867539478938?= AMD Milan introduces support for the swapping, as type 'B', of DR[0-3] and DR[0-3]_ADDR_MASK registers. It requires that SEV_FEATURES[5] be set in the VMSA. This requires the KVM to eliminate the intercept of #DB. However, because of the infinite #DB loop DoS that a malicious guest can do, it can only be eliminated based if CPUID Fn80000021_EAX[0] (NoNestedDataBp) is set in the host/HV. This eliminates #DB intercept, DR7 intercept for SEV-ES/SEV-SNP guest. This saves DR[0-3] / DR[0-3]_ADDR_MASK in the host save area before VMRUN. This sets SEV_FEATURES[5] in VMSA. Signed-off-by: Alexey Kardashevskiy --- arch/x86/include/asm/svm.h | 1 + arch/x86/kvm/svm/svm.h | 18 +++++++++++----- arch/x86/kvm/svm/sev.c | 22 +++++++++++++++++++- arch/x86/kvm/svm/svm.c | 6 ++++-- 4 files changed, 39 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index 0361626841bc..373a0edda588 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -273,6 +273,7 @@ enum avic_ipi_failure_cause { #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF) #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL +#define SVM_SEV_FEAT_DEBUG_SWAP BIT(5) struct vmcb_seg { u16 selector; diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 199a2ecef1ce..4d75b14bffab 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -83,6 +83,7 @@ enum { struct kvm_sev_info { bool active; /* SEV enabled guest */ bool es_active; /* SEV-ES enabled guest */ + bool debug_swap; /* SEV-ES Debug swap enabled */ unsigned int asid; /* ASID used for this guest */ unsigned int handle; /* SEV firmware handle */ int fd; /* SEV device fd */ @@ -388,6 +389,7 @@ static inline bool vmcb12_is_intercept(struct vmcb_ctrl_area_cached *control, u3 static inline void set_dr_intercepts(struct vcpu_svm *svm) { + struct kvm_sev_info *sev = &to_kvm_svm(svm->vcpu.kvm)->sev_info; struct vmcb *vmcb = svm->vmcb01.ptr; if (!sev_es_guest(svm->vcpu.kvm)) { @@ -407,20 +409,26 @@ static inline void set_dr_intercepts(struct vcpu_svm *svm) vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_WRITE); } - vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ); - vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE); + if (!sev->debug_swap) { + vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ); + vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE); + } recalc_intercepts(svm); } static inline void clr_dr_intercepts(struct vcpu_svm *svm) { + struct kvm_sev_info *sev = &to_kvm_svm(svm->vcpu.kvm)->sev_info; struct vmcb *vmcb = svm->vmcb01.ptr; vmcb->control.intercepts[INTERCEPT_DR] = 0; - /* DR7 access must remain intercepted for an SEV-ES guest */ - if (sev_es_guest(svm->vcpu.kvm)) { + /* + * DR7 access must remain intercepted for an SEV-ES guest unless + * the DebugSwap feature is set + */ + if (sev_es_guest(svm->vcpu.kvm) && !sev->debug_swap) { vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ); vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE); } @@ -677,7 +685,7 @@ int sev_handle_vmgexit(struct kvm_vcpu *vcpu); int sev_es_string_io(struct vcpu_svm *svm, int size, unsigned int port, int in); void sev_es_vcpu_reset(struct vcpu_svm *svm); void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); -void sev_es_prepare_switch_to_guest(struct sev_es_save_area *hostsa); +void sev_es_prepare_switch_to_guest(struct kvm_vcpu *vcpu, struct sev_es_save_area *hostsa); void sev_es_unmap_ghcb(struct vcpu_svm *svm); /* vmenter.S */ diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index efaaef2b7ae1..fac8b48e3162 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -21,6 +21,7 @@ #include #include #include +#include #include "mmu.h" #include "x86.h" @@ -253,6 +254,7 @@ static int sev_guest_init(struct kvm *kvm, struct kvm_sev_cmd *argp) if (asid < 0) goto e_no_asid; sev->asid = asid; + sev->debug_swap = sev->es_active && kvm_cpu_cap_get(KVM_X86_FEATURE_NO_NESTED_DATA_BP); ret = sev_platform_init(&argp->error); if (ret) @@ -564,6 +566,7 @@ static int sev_launch_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp) static int sev_es_sync_vmsa(struct vcpu_svm *svm) { struct sev_es_save_area *save = svm->sev_es.vmsa; + struct kvm_sev_info *sev = &to_kvm_svm(svm->vcpu.kvm)->sev_info; /* Check some debug related fields before encrypting the VMSA */ if (svm->vcpu.guest_debug || (svm->vmcb->save.dr7 & ~DR7_FIXED_1)) @@ -604,6 +607,9 @@ static int sev_es_sync_vmsa(struct vcpu_svm *svm) save->xss = svm->vcpu.arch.ia32_xss; save->dr6 = svm->vcpu.arch.dr6; + if (sev->debug_swap) + save->sev_features |= SVM_SEV_FEAT_DEBUG_SWAP; + pr_debug("Virtual Machine Save Area (VMSA):\n"); print_hex_dump_debug("", DUMP_PREFIX_NONE, 16, 1, save, sizeof(*save), false); @@ -3010,8 +3016,10 @@ void sev_es_vcpu_reset(struct vcpu_svm *svm) sev_enc_bit)); } -void sev_es_prepare_switch_to_guest(struct sev_es_save_area *hostsa) +void sev_es_prepare_switch_to_guest(struct kvm_vcpu *vcpu, struct sev_es_save_area *hostsa) { + struct kvm_sev_info *sev = &to_kvm_svm(vcpu->kvm)->sev_info; + /* * As an SEV-ES guest, hardware will restore the host state on VMEXIT, * of which one step is to perform a VMLOAD. KVM performs the @@ -3027,6 +3035,18 @@ void sev_es_prepare_switch_to_guest(struct sev_es_save_area *hostsa) /* MSR_IA32_XSS is restored on VMEXIT, save the currnet host value */ hostsa->xss = host_xss; + + /* The DebugSwap SEV feature does Type B swaps of DR[0-3] */ + if (sev->debug_swap) { + hostsa->dr0 = native_get_debugreg(0); + hostsa->dr1 = native_get_debugreg(1); + hostsa->dr2 = native_get_debugreg(2); + hostsa->dr3 = native_get_debugreg(3); + hostsa->dr0_addr_mask = get_dr_addr_mask(0); + hostsa->dr1_addr_mask = get_dr_addr_mask(1); + hostsa->dr2_addr_mask = get_dr_addr_mask(2); + hostsa->dr3_addr_mask = get_dr_addr_mask(3); + } } void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index ce362e88a567..ee0e56521d26 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -1173,6 +1173,7 @@ static void init_vmcb(struct kvm_vcpu *vcpu) struct vmcb *vmcb = svm->vmcb01.ptr; struct vmcb_control_area *control = &vmcb->control; struct vmcb_save_area *save = &vmcb->save; + struct kvm_sev_info *sev = &to_kvm_svm(vcpu->kvm)->sev_info; svm_set_intercept(svm, INTERCEPT_CR0_READ); svm_set_intercept(svm, INTERCEPT_CR3_READ); @@ -1189,7 +1190,8 @@ static void init_vmcb(struct kvm_vcpu *vcpu) set_exception_intercept(svm, UD_VECTOR); set_exception_intercept(svm, MC_VECTOR); set_exception_intercept(svm, AC_VECTOR); - set_exception_intercept(svm, DB_VECTOR); + if (!sev->debug_swap) + set_exception_intercept(svm, DB_VECTOR); /* * Guest access to VMware backdoor ports could legitimately * trigger #GP because of TSS I/O permission bitmap. @@ -1461,7 +1463,7 @@ static void svm_prepare_switch_to_guest(struct kvm_vcpu *vcpu) struct sev_es_save_area *hostsa; hostsa = (struct sev_es_save_area *)(page_address(sd->save_area) + 0x400); - sev_es_prepare_switch_to_guest(hostsa); + sev_es_prepare_switch_to_guest(vcpu, hostsa); } if (tsc_scaling) From patchwork Thu Dec 1 02:19:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Kardashevskiy X-Patchwork-Id: 28165 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp42344wrr; Wed, 30 Nov 2022 19:03:28 -0800 (PST) X-Google-Smtp-Source: AA0mqf6UUbZMZfLg0BgwTeHpSuakYbPmuv9eWJ8sR2PNHVKaCopNc3d1qSrlS+tmg3M/Lzr0I7Fq X-Received: by 2002:a63:465f:0:b0:477:c889:cb33 with SMTP id v31-20020a63465f000000b00477c889cb33mr31629858pgk.12.1669863808232; Wed, 30 Nov 2022 19:03:28 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1669863808; cv=pass; d=google.com; s=arc-20160816; b=UtRvg4xLSzgIgRJynhd6UvhT8EAhscn0JRNtVfkqjRRE+sDQxz1rz3pQC4Tdo42Qi9 7or39dfvEn0SPxgvpO75FEYjvzYn3WkCaH63UtdvsqJbGsNF3Kwsh7XPNy1gPYrktDAO bdsu4hssYqtOXO8imZ7THom6qhGrsVI1/I9JemX0B1O5nlIsT07rgKwM+kn3ha5Nnti3 58erpUL6Nz4Dh7wek58S8cFALxsNzKp+HQu1gaa5mRrWRuhmO1j3w6Ft0NDTPvvU5W2K LzkVSVH8YuIUVk7ZJAwBRc4o8TJcxzwrYmQlp22bEkO6k+IlmNZTYEUqGeBBU2U8OmEM deuw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=EQAjlAPKNRKc521/wzfFqzadKeyxrglYxiNICeUux10=; b=MXn3AcyerlFm7p19rM3DzsYgZtlsZuoCAmOFXlqYttEeKth7GGkBZIPxGdarFxtl6G WN1wczKfaxW/ZpT4MM5e6GP7tHnDRYP+Ur5D9NXoQJEzT0/ZthQHSj/hqJxZLE7cvvOs aPqz5tWQtItHfA3PbdZs55N9gY0FgzQgvpk5Z1kO/vZu0IinpR5CmJcOQiNMxdHhhjeU Gtg0BHjcuqna61FXeFDkjtZf3muK/y89kEqXUjLYsNVT7YFSzRRXQACrBQGDZMXM7isS sDmTtozCd25mjxLwuf0meBk7M0MYzhND492zjbvRLAR5w7AwVteSTJeD2ymL5Cz3hMoe 12pA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=wX5bzKRs; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" Subject: [PATCH kernel 3/3] x86/sev: Do not handle #VC for DR7 read/write Date: Thu, 1 Dec 2022 13:19:48 +1100 Message-ID: <20221201021948.9259-4-aik@amd.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221201021948.9259-1-aik@amd.com> References: <20221201021948.9259-1-aik@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT038:EE_|MW4PR12MB7214:EE_ X-MS-Office365-Filtering-Correlation-Id: c81b5452-bf0a-4fc0-3408-08dad342d409 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Zheap7xYOfCbmkLtVg9HUZdNaYmGapmYz7Cn9Rs1RK9fPbHGAjyQprLZItWGppGxGQFZT8dDxsOv7ykO8JdgOEg7TMncNxu6Bo6fd5byTH20alVgDWuB2gAG23NQppqRUkR7boqrUObmfq/XXNLhMNCnvisf/kLL87EEz7lf95bxUTHVjKGcbp+IGkNA7XpFtD2PVxAh/WdNofsoQ6Hu57QpPu5mAr1D7yI+dz5Ictw/Jwx5ozhkrhDgyFXYcy62U2h0Geb2MEUcxGxwJGX1pLiiBrcZ06/sXqWrw4Pb2gwsqWfj/o/EfcvfOBAFkiyX5Li1TeFFmUD5wS6qL3PW3unX61SdrcoElZgu+JKkFvbKiwAZejSoXdlH22Kxb6yH5hoo51ViTFz7w12L/em31bAu5OHVp4sa6ul8B6DqisoV9lsuAbZ19W2xoapE8mW+oAbkNc+wRzJE0D3BsLLEh23z0bQYXMVoaUSR/9xyi7+LmICVx4POSEXdYCdnB2/HqFvK25czYeOvQV5GzoCj0sv9n+INGUnxgp2rj8hYxY7/2qe45NemyQn2qKoo3T3aXov4viV7OZR1AoRr+vvX9VqmJn2AyBrYxzGxU2o8GyB4lecZZzc84XSGX9DvsJ+uFdBrSwy7kTkHA7N8vSyEQyuWmsd8aTCijyC3Pq/wIMjKdhUGhLYl0DlvBR6989+oQ7NvuuCWiJB1Jb4voND6wCe+88T/LpOYnjP/FeQVmFw= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(376002)(136003)(39860400002)(396003)(451199015)(46966006)(40470700004)(36840700001)(36860700001)(478600001)(2906002)(6200100001)(6666004)(37006003)(7416002)(356005)(54906003)(81166007)(82740400003)(5660300002)(4744005)(40460700003)(426003)(82310400005)(47076005)(36756003)(8936002)(41300700001)(7049001)(1076003)(6862004)(2616005)(8676002)(336012)(4326008)(26005)(40480700001)(316002)(16526019)(186003)(70586007)(70206006)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2022 02:22:00.4240 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c81b5452-bf0a-4fc0-3408-08dad342d409 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT038.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7214 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750979112497283677?= X-GMAIL-MSGID: =?utf-8?q?1750979112497283677?= With SVM_SEV_FEAT_DEBUG_SWAP enabled, the VM should not get #VC events for DR7 read/write which it rather avoided. Signed-off-by: Alexey Kardashevskiy --- arch/x86/kernel/sev.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index a428c62330d3..4e91b9f8742c 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -1618,6 +1618,9 @@ static enum es_result vc_handle_dr7_write(struct ghcb *ghcb, long val, *reg = vc_insn_get_rm(ctxt); enum es_result ret; + if ((sev_status >> 2) & SVM_SEV_FEAT_DEBUG_SWAP) + return ES_VMM_ERROR; + if (!reg) return ES_DECODE_FAILED; @@ -1655,6 +1658,9 @@ static enum es_result vc_handle_dr7_read(struct ghcb *ghcb, struct sev_es_runtime_data *data = this_cpu_read(runtime_data); long *reg = vc_insn_get_rm(ctxt); + if ((sev_status >> 2) & SVM_SEV_FEAT_DEBUG_SWAP) + return ES_VMM_ERROR; + if (!reg) return ES_DECODE_FAILED;