From patchwork Tue Nov 29 14:47:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 27289 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp384968wrr; Tue, 29 Nov 2022 06:51:55 -0800 (PST) X-Google-Smtp-Source: AA0mqf7ymvMxGQTZWnQmpTRF9DjkPmwlP/oO6NQHODO+2PnScIWekT9tfHy0YsN7F5imNm1iMKpf X-Received: by 2002:aa7:8487:0:b0:56c:3bb4:28a8 with SMTP id u7-20020aa78487000000b0056c3bb428a8mr37909235pfn.83.1669733515633; Tue, 29 Nov 2022 06:51:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669733515; cv=none; d=google.com; s=arc-20160816; b=NRhokKgPFWujIttU6dFyWBLTPAeYuhdntodTnGSiVlqCeR+3qJKHvbg+D5KMHavKBa 8QnhGlSbmfqKJRmjTyau1JMEUPPxI2ugaRrx/OUCJ/7xzHjljO5yM8tVQXx6t2+Kx2az FzlMdwFPagkZFRiW8Ft8X+OyLE6K20qsSzvFFHgRmyD37hQjb+FTREwLKEDWmu57i7Oy vWq09snndo4sqbDQ+sx7ckRJENvEqMsWNxyyUN2EKoZMIOKIeAywQfM+EH3NVeuENuMc rfR8gyHI5KYOwGb7cU67XSgyoSJDRkg7A8SbDQHIoD6qXl7C4PL+/bNjjE+XkPLAgJmJ Xa0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=GNhUEoy7zRdvGClbIlTELmRqWqiCMdOHmfixX/cCHP4=; b=fYUgfZRz10XrMEcSGyTcUWz8shiCBkaVkMd59nebv99IAmK+i4dVZaylEAUbZZgvkL QHUHRhzr6Rf6qDJJKK5jkx70Izif2qysIuNwgXlwwKxHbtB6CbNyKjdSbLnlNjxrqznn NlSzSvZDSiYdzpSkVi4q0Nn/4xRb9rfoNGubjH4gD0E/UgvKhUj6x7u0X6F03nlStumy 11g++WkxSwpzFY1vzM/ULfqhQKPuNy5gXlyvWbv3nJLV0keWeotgfwvnO0srvSj0U66O pla+f5k4X4ScICNiF40dKigj26d7VzWwlK6mdxmAUNiUutE+HIq8pYZ2ii6V7YJuyuA5 2ccw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=DA7JrLVp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 5-20020a630405000000b0046fea9618cdsi15890071pge.323.2022.11.29.06.51.41; Tue, 29 Nov 2022 06:51:55 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=DA7JrLVp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234926AbiK2OvZ (ORCPT + 99 others); Tue, 29 Nov 2022 09:51:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52536 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230391AbiK2OvS (ORCPT ); Tue, 29 Nov 2022 09:51:18 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D083BAD; Tue, 29 Nov 2022 06:51:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1669733477; x=1701269477; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CX12l/BYcHckW0nxt5dW6uGaSf9bcCVSRsIUm2MrbaY=; b=DA7JrLVpepXpqVe7J3e2kwZ+2bgGr0OHLrpTZxiKLMLF79BDOa4stEqY I8B2ZS8uBISd6Z0UqtscpECyUSiJcZAItm+PRAGz7A3DTBy3tf6r4+5ZQ SIxG3jkIfvUBkTTMwlcmtSbM8qqeO66s1Ua5DS2ANj6uuX0TndFDDM49f N8YbB11V68H0m7QlHoOxap31wAWajstPyc+lCepwE7XgJ3/7G2LnRVpyn FSe3tfWz6kaBrc3YHQgGq8SmmK2IqTfFZlHfh1zqnHtxm7S/9qqg9d95W Oacz2NlwhR1DWxiJhHbM5Sqwyeg9D+Hq3ANE0czNXepfLAGNZT053nBqU A==; X-IronPort-AV: E=Sophos;i="5.96,203,1665471600"; d="scan'208";a="190983230" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 29 Nov 2022 07:51:17 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 29 Nov 2022 07:51:15 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 29 Nov 2022 07:51:13 -0700 From: Conor Dooley To: CC: Conor Dooley , , , , , , , , , , , Subject: [RFC 1/2] RISC-V: clarify ISA string ordering rules in cpu.c Date: Tue, 29 Nov 2022 14:47:42 +0000 Message-ID: <20221129144742.2935581-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750842490836613244?= X-GMAIL-MSGID: =?utf-8?q?1750842490836613244?= While the list of rules may have been accurate when created, it now lacks some clarity in the face of isa-manual updates. Specifically: - there is no mention here of a distinction between regular 'Z' extensions which are "Additional Standard Extensions" and "Zxm" extensions which are "Standard Machine-Level Extensions" - there is also no explicit mention of where either should be sorted in the list - underscores are only required between two *multi-letter* extensions but the list of rules implies that this is required between a multi-letter extension and any other extension. IOW "rv64imafdzicsr_zifencei" is a valid string Attempt to clean up the list of rules, by adding information on the above & sprinkling in some white space for readability. Signed-off-by: Conor Dooley --- arch/riscv/kernel/cpu.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 852ecccd8920..5e42c92a8456 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -120,20 +120,32 @@ device_initcall(riscv_cpuinfo_init); .uprop = #UPROP, \ .isa_ext_id = EXTID, \ } + /* * Here are the ordering rules of extension naming defined by RISC-V * specification : - * 1. All extensions should be separated from other multi-letter extensions - * by an underscore. + * + * 1. All multi-letter extensions should be separated from other multi-letter + * extensions by an underscore. + * * 2. The first letter following the 'Z' conventionally indicates the most * closely related alphabetical extension category, IMAFDQLCBKJTPVH. - * If multiple 'Z' extensions are named, they should be ordered first - * by category, then alphabetically within a category. + * 'Z' extensions should be sorted after single-letter extensions and before + * any higher-privileged extensions. + * If multiple 'Z' extensions are named, they should be ordered first by + * category, then alphabetically within a category. + * * 3. Standard supervisor-level extensions (starts with 'S') should be * listed after standard unprivileged extensions. If multiple * supervisor-level extensions are listed, they should be ordered * alphabetically. - * 4. Non-standard extensions (starts with 'X') must be listed after all + * + * 4 Standard machine-level extensions (starts with 'Zxm') should be + * listed after any lower-privileged, standard extensions. If multiple + * machine-level extensions are listed, they should be ordered + * alphabetically. + * + * 5. Non-standard extensions (starts with 'X') must be listed after all * standard extensions. They must be separated from other multi-letter * extensions by an underscore. */ From patchwork Tue Nov 29 14:47:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 27290 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp385393wrr; Tue, 29 Nov 2022 06:52:42 -0800 (PST) X-Google-Smtp-Source: AA0mqf4sHIb/zYt9Q6ImAZZFGDQghSINB8ERKGF9yqpoWPgU/rjfLQuP2JRUNjo4S+CN6Cni0AhA X-Received: by 2002:a17:906:8547:b0:7b4:ae8f:c61 with SMTP id h7-20020a170906854700b007b4ae8f0c61mr39888471ejy.403.1669733562702; Tue, 29 Nov 2022 06:52:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669733562; cv=none; d=google.com; s=arc-20160816; b=LGosnhK1N4vPRxE6WgP4p4SUu9Tt3Wh5y9zH0UOEgbYGlQ13nCV1chmztzEztlZSGM 1SilQKOwjUQ/jm+e+eJZK9en4s7Kxwto/qsAFjZdllYjzqWUPZRoxujgjHoSgYsVLpNE CzCUPA6k4BLbPAc8x9NXKTJ3rH9zUsxHrJxm7jgfxrZkOUIxeJwe82eqm/4yJCDDVrbg WDVrK/PK6zRhTgV6nXhD5CUKr8c1EClOjw+efk0swdq2EBXwyrZdBQ4IRnDBZ1MDija4 gSkzN4uv+R/X6nxZqweD29CfwbcCYwgYLROQiYm4AMRnLfrVdkrV6U84J5AqpUyWSaxj ht7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=JFuNk0+fKb8PB47wG6KzVrAultvTxV733fBeeqP/9YY=; b=SbFrNSKr+weA8jFWt8o6ajLs1Tbfz+Ckp5b0fCBLsyYbuvUf2raWB4JUw0yBfUR/gw 0ygIPtoKygcC8hoQots7Sj33sOwOHczHr2MVVzDT5ecOGrdDr3PwAG5tBhrTf+F8VbqD r4jSzRrfFDcNneC5sIf8clZBwJWTnQ0o3OsVWDPU4EcClDlEoS9Ka+8+eulhO886cWhG Z52k+WKEpWT8pFC1/2aMdHv8atZeJn28nXXtHmHJFa//mpgQ3DkO9IocCMaH6uiNFXha 1EBJwcXlVogwgu5rALqpi0G3Hj32zaGZp7V8Lvp5gMY2sDheo0oxsHhB1Ddimp62Z6YX 0Vkg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=TWVfXd70; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id sa9-20020a1709076d0900b007bf22d4e679si5964467ejc.63.2022.11.29.06.52.18; Tue, 29 Nov 2022 06:52:42 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=TWVfXd70; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235179AbiK2Ov2 (ORCPT + 99 others); Tue, 29 Nov 2022 09:51:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57904 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234622AbiK2OvX (ORCPT ); Tue, 29 Nov 2022 09:51:23 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0601FB4F; Tue, 29 Nov 2022 06:51:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1669733483; x=1701269483; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ag9tRag2tCMnYNZ7PXKJUn99ayga3IWCVtRNMuIqp7c=; b=TWVfXd706Az1RcBgR0msPdvL/N1kWL128Qm5KnDIZhnwRjjCEVQfRMDt 33gO6eIC+OE5006Jmf7XzpKo8sCIbQcgZ6gKqzkY2MmxJAXW/wRhFH0P7 VjLGUW3NdZ9pC/8gSmvCW60tEengyAJEjm/ByOrxRrKM2jUOimx6LdaGo 8HQUDIkAJXwerZuwKWQ01wlBOUNMOGCZudCGIxzBkaFi2bm1DsNaDXXXU wf0hMGueM37LhaqJDzB4ps9hlprfuBl2PdfBhuTqfMKKZnEhfua7GVm3i 6HvDH72gZSAQXXJJEJvpsjxjCXKwI7w4Firzl79CeA6SJLxGi4lGHaPZy A==; X-IronPort-AV: E=Sophos;i="5.96,203,1665471600"; d="scan'208";a="185697717" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 29 Nov 2022 07:51:22 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 29 Nov 2022 07:51:18 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 29 Nov 2022 07:51:16 -0700 From: Conor Dooley To: CC: Conor Dooley , , , , , , , , , , , Subject: [RFC 2/2] RISC-V: resort all extensions in "canonical" order Date: Tue, 29 Nov 2022 14:47:43 +0000 Message-ID: <20221129144742.2935581-3-conor.dooley@microchip.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750842540420756658?= X-GMAIL-MSGID: =?utf-8?q?1750842540420756658?= Per the comment in cpu.c, re-sort all lists/tables/enums/whatever in arch/riscv (apart from KVM) in the current edition of what the isa manual considers to be "canonical" order. None of this is in uapi, so we are free to re-order it? I'm never sure when it comes to hwcap... Signed-off-by: Conor Dooley --- arch/riscv/include/asm/hwcap.h | 6 +++--- arch/riscv/kernel/cpu.c | 4 ++-- arch/riscv/kernel/cpufeature.c | 4 ++-- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index b22525290073..d7d5f27619ee 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -53,12 +53,12 @@ extern unsigned long elf_hwcap; * available logical extension id. */ enum riscv_isa_ext_id { - RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, - RISCV_ISA_EXT_SVPBMT, - RISCV_ISA_EXT_ZICBOM, + RISCV_ISA_EXT_ZICBOM = RISCV_ISA_EXT_BASE, RISCV_ISA_EXT_ZIHINTPAUSE, + RISCV_ISA_EXT_SSCOFPMF, RISCV_ISA_EXT_SSTC, RISCV_ISA_EXT_SVINVAL, + RISCV_ISA_EXT_SVPBMT, RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 5e42c92a8456..1d0fa0ebf6a8 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -150,12 +150,12 @@ device_initcall(riscv_cpuinfo_init); * extensions by an underscore. */ static struct riscv_isa_ext_data isa_ext_arr[] = { + __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), + __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), - __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), - __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), }; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 694267d1fe81..d3df72c4b94f 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -199,12 +199,12 @@ void __init riscv_fill_hwcap(void) this_hwcap |= isa2hwcap[(unsigned char)(*ext)]; set_bit(*ext - 'a', this_isa); } else { - SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); - SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM); SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); + SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL); + SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); } #undef SET_ISA_EXT_MAP }