From patchwork Tue Nov 29 03:41:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yinbo Zhu X-Patchwork-Id: 27070 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp109208wrr; Mon, 28 Nov 2022 19:45:00 -0800 (PST) X-Google-Smtp-Source: AA0mqf6JxhAtX674VmRgAfy3y6GHyUVxSKj+GgdEqkdmOykNRmeZh0qndbVX3o83WAjLxepD/UqB X-Received: by 2002:a05:6402:3707:b0:467:6847:83d3 with SMTP id ek7-20020a056402370700b00467684783d3mr10490623edb.247.1669693500395; Mon, 28 Nov 2022 19:45:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669693500; cv=none; d=google.com; s=arc-20160816; b=TCH/0q6iFWSoI8TgGWB/bUl72uwjVEXcpk8hcZ01lO0lgjOeTrfrUI21D5UGfpvjRh IfKoPSO417UyEB/YPrnm8q0fhUKUNOsLTGYr0r2OLRlJI2JsDb98fN+rWzXMMmAwFCIi jkKzWCmIALvZEL9OXA25M27gWP9pkKcPTYvZNnuLlGeJGaX+ruSPdtQX8p53rrdZaJGU EJiZrL4dPZKMD1avE6XJof+AmuGR/Xm4LDwdjCg8XfxKqe47apuVR6vwF95gNHb5lEcR t4/jKM0Av/wbLJiGZOpBo2ezSW+7G+MdjqnIK9KkzgtLMXQRv5YG/kHhJKhEU4W678Ew VTlw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=Ool3wnLMsgp5KMPQOcY8tpCy+NmhSRN07NuUONAeXHY=; b=SNF9CIuh+QMhQ/g4lXtUahrlRINStsFMJsZpgtEBTUuTQUGIfNogrkMNaenOiO31/O c9HE2XbaLP515k0R4KJphYAloXfbcemhmh5Q6o6w0AXB9kkhGrEJYzfhnR7DRfzqfm/T /csFtYZE7Xl6z5JNqibYiXHx8yMFWNL2NxYWfwk1LO1E889jajAYBU9JErRS35+3R7mh GQQloM+UipmjcpvmOzxYIujta9gheLsGoj7SZD5mw8soIkOZDEE6U7iTllRDxgcHB3Jb mULrONq+WgpAZeDDhwOrWvBqLC7wUlS6huGSElIdhT+/vEG178vSXamUO3A+psOBbmB7 XhdQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id xa3-20020a170906fd8300b007a8beb3aa4csi10535048ejb.872.2022.11.28.19.44.37; Mon, 28 Nov 2022 19:45:00 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235545AbiK2DmL (ORCPT + 99 others); Mon, 28 Nov 2022 22:42:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59182 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235529AbiK2DmF (ORCPT ); Mon, 28 Nov 2022 22:42:05 -0500 Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id D8CE14B773; Mon, 28 Nov 2022 19:42:03 -0800 (PST) Received: from loongson.cn (unknown [10.180.13.64]) by gateway (Coremail) with SMTP id _____8DxM_CKf4VjXugBAA--.4539S3; Tue, 29 Nov 2022 11:42:02 +0800 (CST) Received: from localhost.localdomain (unknown [10.180.13.64]) by localhost.localdomain (Coremail) with SMTP id AQAAf8AxPuCGf4VjjecdAA--.10584S2; Tue, 29 Nov 2022 11:42:02 +0800 (CST) From: Yinbo Zhu To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Huacai Chen , WANG Xuerui , Jiaxun Yang , Jianmin Lv , Yang Li , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Yinbo Zhu Cc: Krzysztof Kozlowski Subject: [PATCH v10 1/4] dt-bindings: clock: add loongson-2 clock include file Date: Tue, 29 Nov 2022 11:41:54 +0800 Message-Id: <20221129034157.15036-1-zhuyinbo@loongson.cn> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8AxPuCGf4VjjecdAA--.10584S2 X-CM-SenderInfo: 52kx5xhqerqz5rrqw2lrqou0/ X-Coremail-Antispam: 1Uk129KBjvJXoWxAF1fAw4ktFykCF4UGw4fuFg_yoW5Cry8pF s5CFZ3KrW2yF4IkanYgFy7Kr15ua4xJ3srAF42kw1UAFnrJw18JrnrKF1rArZxXrsrCFWx Z3ZYkw409a9rZ3DanT9S1TB71UUUUj7qnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj qI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUU bS8Fc2x0x2IEx4CE42xK8VAvwI8IcIk0rVWrJVCq3wAFIxvE14AKwVWUXVWUAwA2ocxC64 kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28E F7xvwVC0I7IYx2IY6xkF7I0E14v26r4j6F4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJw A2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJwAaw2AFwI0_JF0_Jw1le2I262IYc4CY 6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27wAqx4xG64xvF2IEw4CE5I8CrV C2j2WlYx0E2Ix0cI8IcVAFwI0_JF0_Jw1lYx0Ex4A2jsIE14v26r4j6F4UMcvjeVCFs4IE 7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCY1x0262kKe7AKxVWUAVWUtwCF04k20xvY0x 0EwIxGrwCF04k20xvE74AGY7Cv6cx26rWl4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1l4IxYO2xF xVAFwI0_JF0_Jw1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWw C2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_ JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJV WUCwCI42IY6I8E87Iv67AKxVWxJVW8Jr1lIxAIcVC2z280aVCY1x0267AKxVW8Jr0_Cr1U YxBIdaVFxhVjvjDU0xZFpf9x07jYnmiUUUUU= X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750800531869985586?= X-GMAIL-MSGID: =?utf-8?q?1750800531869985586?= This file defines all Loongson-2 SoC clock indexes, it should be included in the device tree in which there's device using the clocks. Signed-off-by: Yinbo Zhu Acked-by: Krzysztof Kozlowski --- Change in v10: 1. NO change, but other patch in this series of patches has changes. Change in v9: 1. Add all history changelog infomation. Change in v8: 1. NO change, but other patch in this series of patches has changes. Change in v7: 1. NO change, but other patch in this series of patches has changes. Change in v6: 1. Replace string LOONGSON2 with LOONGSON-2 in MAINTAINERS. Change in v5: 1. Replace loongson2/Loongson2 with loongson-2/Loongson-2. 2. Replace soc with SoC. Change in v4: 1. NO change, but other patch in this series of patches has changes. Change in v3: 1. Add the review information. Change in v2: 1. Make filename matching the compatible. 2. Drop weird indentation after define. 3. Add dual license. 4. Use subject prefixes matching the subsystem. MAINTAINERS | 6 ++++ include/dt-bindings/clock/loongson,ls2k-clk.h | 29 +++++++++++++++++++ 2 files changed, 35 insertions(+) create mode 100644 include/dt-bindings/clock/loongson,ls2k-clk.h diff --git a/MAINTAINERS b/MAINTAINERS index 182129c73ed5..ab94893fe2f6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12021,6 +12021,12 @@ S: Maintained F: Documentation/devicetree/bindings/thermal/loongson,ls2k-thermal.yaml F: drivers/thermal/loongson2_thermal.c +LOONGSON-2 SOC SERIES CLOCK DRIVER +M: Yinbo Zhu +L: linux-clk@vger.kernel.org +S: Maintained +F: include/dt-bindings/clock/loongson,ls2k-clk.h + LSILOGIC MPT FUSION DRIVERS (FC/SAS/SPI) M: Sathya Prakash M: Sreekanth Reddy diff --git a/include/dt-bindings/clock/loongson,ls2k-clk.h b/include/dt-bindings/clock/loongson,ls2k-clk.h new file mode 100644 index 000000000000..db1e27e792ff --- /dev/null +++ b/include/dt-bindings/clock/loongson,ls2k-clk.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Author: Yinbo Zhu + * Copyright (C) 2022-2023 Loongson Technology Corporation Limited + */ + +#ifndef __DT_BINDINGS_CLOCK_LOONGSON2_H +#define __DT_BINDINGS_CLOCK_LOONGSON2_H + +#define LOONGSON2_REF_100M 0 +#define LOONGSON2_NODE_PLL 1 +#define LOONGSON2_DDR_PLL 2 +#define LOONGSON2_DC_PLL 3 +#define LOONGSON2_PIX0_PLL 4 +#define LOONGSON2_PIX1_PLL 5 +#define LOONGSON2_NODE_CLK 6 +#define LOONGSON2_HDA_CLK 7 +#define LOONGSON2_GPU_CLK 8 +#define LOONGSON2_DDR_CLK 9 +#define LOONGSON2_GMAC_CLK 10 +#define LOONGSON2_DC_CLK 11 +#define LOONGSON2_APB_CLK 12 +#define LOONGSON2_USB_CLK 13 +#define LOONGSON2_SATA_CLK 14 +#define LOONGSON2_PIX0_CLK 15 +#define LOONGSON2_PIX1_CLK 16 +#define LOONGSON2_CLK_END 17 + +#endif From patchwork Tue Nov 29 03:41:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yinbo Zhu X-Patchwork-Id: 27072 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp113238wrr; Mon, 28 Nov 2022 19:58:30 -0800 (PST) X-Google-Smtp-Source: AA0mqf4WxYQw+XfgEC2poxx5Rh/rZUL7ff6Ak/Gqkx5Dxc4O8gg82Bv6/Aq+uytObqdPy1CFpWsm X-Received: by 2002:a17:906:94e:b0:7ba:4617:3f17 with SMTP id j14-20020a170906094e00b007ba46173f17mr24213488ejd.226.1669694310510; Mon, 28 Nov 2022 19:58:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669694310; cv=none; d=google.com; s=arc-20160816; b=GMFK8J95CgVOkTsuokylXul+vKtSXbhS9BSMlg/Mk03tc6HvnJkUKfEcFf05uSW9T0 jTNTEhbgg9gDbAPNGgLpSaBNmfSoDZO0Dg/7NXZA8uJ2z/mvJt1lMopLXfGZAz39shd5 9BGtzq7IECdFkWDnK3mLG6cuBYrjylGi6j4EIMkqA50RCZypag7pON1s+dQe0hhPo2G0 iV+inAmDxHhdyS6JvqPGsFUkZRA6cDoG9hPt71LcET/QzGGb04kV34SNQVCG4C4BN/4I PrpCtsjfwpSDbdKnjeRUvHNS8q2M98uq9hNhvRD9sxmS3MATqS09AD24q9xfaPEAKsyp mn8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from; bh=xo8uC71SXA4CO3Qzezjvb3HHzu0A8oJkXrtZlRMkZ3g=; b=CUTb12lzaPIFi+PURBZS+MY3F00oMl/iGkckLuVzNRWzuCUg95PG0W28AGcQHlI6U8 8kgEkDwanUeaitsX3N5CMTHOT8IMFpuyKsoegllihMiLQx+j16Kc7UEwmILgQuPtvocy 0H4FH4Ka7PPS5lPZ/9R/PYlLHlVP8IyFSoYZnxx226xKJNVwhrVdR8t8KkyK5o6bYnZL schHgw7Sl5RRYQmQ8eNUcg/PcHHkLcdiW8hxbaq6SLC2VhBbm5ARCzHEaJ0HO62StuOd YkGdqG4uiq3I05nzWAKiHxzm5+S9O923RRFaFI9+0ht1UbQ43dItmwTYETSgS+uRNWbG 58MA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id sh36-20020a1709076ea400b0079bf804c0c4si11392928ejc.103.2022.11.28.19.57.54; Mon, 28 Nov 2022 19:58:30 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235509AbiK2DmS (ORCPT + 99 others); Mon, 28 Nov 2022 22:42:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235546AbiK2DmI (ORCPT ); Mon, 28 Nov 2022 22:42:08 -0500 Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 7C5CF4B773; Mon, 28 Nov 2022 19:42:06 -0800 (PST) Received: from loongson.cn (unknown [10.180.13.64]) by gateway (Coremail) with SMTP id _____8Dx+OiMf4Vjb+gBAA--.1336S3; Tue, 29 Nov 2022 11:42:04 +0800 (CST) Received: from localhost.localdomain (unknown [10.180.13.64]) by localhost.localdomain (Coremail) with SMTP id AQAAf8AxPuCGf4VjjecdAA--.10584S3; Tue, 29 Nov 2022 11:42:02 +0800 (CST) From: Yinbo Zhu To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Huacai Chen , WANG Xuerui , Jiaxun Yang , Jianmin Lv , Yang Li , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Yinbo Zhu Subject: [PATCH v10 2/4] clk: clk-loongson2: add clock controller driver support Date: Tue, 29 Nov 2022 11:41:55 +0800 Message-Id: <20221129034157.15036-2-zhuyinbo@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20221129034157.15036-1-zhuyinbo@loongson.cn> References: <20221129034157.15036-1-zhuyinbo@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8AxPuCGf4VjjecdAA--.10584S3 X-CM-SenderInfo: 52kx5xhqerqz5rrqw2lrqou0/ X-Coremail-Antispam: 1Uk129KBjvJXoW3trWkXFyUWF13XFy3ur1xKrg_yoWkWw1DpF WfAay5WrWjqr45uFsxtryDGr15Aas3Ca47AF43Ga4jkrZ7X345Wr40yFy8AF4UZrWkAay2 vFZagrW8CFs8WwUanT9S1TB71UUUUjDqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj qI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUU bS8Fc2x0x2IEx4CE42xK8VAvwI8IcIk0rVWrJVCq3wAFIxvE14AKwVWUXVWUAwA2ocxC64 kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28E F7xvwVC0I7IYx2IY6xkF7I0E14v26r4j6F4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJw A2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Cr1j6rxdM2kKe7AKxVWUAVWUtwAS0I0E0xvYzxvE 52x082IY62kv0487Mc804VCY07AIYIkI8VC2zVCFFI0UMc02F40EFcxC0VAKzVAqx4xG6I 80ewAv7VC0I7IYx2IY67AKxVWUtVWrXwAv7VC2z280aVAFwI0_Cr0_Gr1UMcvjeVCFs4IE 7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCY1x0262kKe7AKxVWUAVWUtwCF04k20xvY0x 0EwIxGrwCF04k20xvE74AGY7Cv6cx26rWl4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1l4IxYO2xF xVAFwI0_JF0_Jw1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWw C2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Xr0_ Ar1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJV WUCwCI42IY6I8E87Iv67AKxVWxJVW8Jr1lIxAIcVC2z280aVCY1x0267AKxVW8Jr0_Cr1U YxBIdaVFxhVjvjDU0xZFpf9x07UR89_UUUUU= X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750801381383973204?= X-GMAIL-MSGID: =?utf-8?q?1750801381383973204?= This driver provides support for clock controller on Loongson-2 SoC, the Loongson-2 SoC uses a 100MHz clock as the PLL reference clock, there are five independent PLLs inside, each of which PLL can provide up to three sets of frequency dependent clock outputs. Signed-off-by: Yinbo Zhu --- Change in v10: 1. Detach of_clk_init to another patch. Change in v9: 1. Add all history changelog information. Change in v8: 1. Remove the flag "CLK_IS_BASIC". Change in v7: 1. Adjust position alphabetically in Kconfig and Makefile. 2. Add static for loongson2_pll_base. 3. Move other file-scope variables in probe. Change in v6: 1. NO change, but other patch in this series of patches has changes. Change in v5: 1. Replace loongson2 with Loongson-2 in commit info. 2. Replace Loongson2 with Loongson-2 in binding and Kconfig file. 3. Replace soc with SoC. Change in v4: 1. Fixup clock-names that replace "xxx-clk" with "xxx". Change in v3: 1. NO change, but other patch in this series of patches has changes. Change in v2: 1. Update the include filename. 2. Change string from refclk/REFCLK to ref/REF. MAINTAINERS | 1 + arch/loongarch/Kconfig | 1 + drivers/clk/Kconfig | 9 ++ drivers/clk/Makefile | 1 + drivers/clk/clk-loongson2.c | 286 ++++++++++++++++++++++++++++++++++++ 5 files changed, 298 insertions(+) create mode 100644 drivers/clk/clk-loongson2.c diff --git a/MAINTAINERS b/MAINTAINERS index ab94893fe2f6..73fa56f1fd5d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12025,6 +12025,7 @@ LOONGSON-2 SOC SERIES CLOCK DRIVER M: Yinbo Zhu L: linux-clk@vger.kernel.org S: Maintained +F: drivers/clk/clk-loongson2.c F: include/dt-bindings/clock/loongson,ls2k-clk.h LSILOGIC MPT FUSION DRIVERS (FC/SAS/SPI) diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig index 903096bd87f8..4f8f1b8f796d 100644 --- a/arch/loongarch/Kconfig +++ b/arch/loongarch/Kconfig @@ -127,6 +127,7 @@ config LOONGARCH select USE_PERCPU_NUMA_NODE_ID select USER_STACKTRACE_SUPPORT select ZONE_DMA32 + select COMMON_CLK config 32BIT bool diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index d79905f3e174..d13626f63739 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -326,6 +326,15 @@ config COMMON_CLK_LOCHNAGAR This driver supports the clocking features of the Cirrus Logic Lochnagar audio development board. +config COMMON_CLK_LOONGSON2 + bool "Clock driver for Loongson-2 SoC" + depends on COMMON_CLK && OF + help + This driver provides support for Clock Controller that base on + Common Clock Framework Controller (CCF) on Loongson-2 SoC. The + Clock Controller can generates and supplies clock to various + peripherals within the SoC. + config COMMON_CLK_NXP def_bool COMMON_CLK && (ARCH_LPC18XX || ARCH_LPC32XX) select REGMAP_MMIO if ARCH_LPC32XX diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index e3ca0d058a25..b298c5dabc1a 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -43,6 +43,7 @@ obj-$(CONFIG_COMMON_CLK_K210) += clk-k210.o obj-$(CONFIG_LMK04832) += clk-lmk04832.o obj-$(CONFIG_COMMON_CLK_LAN966X) += clk-lan966x.o obj-$(CONFIG_COMMON_CLK_LOCHNAGAR) += clk-lochnagar.o +obj-$(CONFIG_COMMON_CLK_LOONGSON2) += clk-loongson2.o obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o obj-$(CONFIG_COMMON_CLK_MAX9485) += clk-max9485.o obj-$(CONFIG_ARCH_MILBEAUT_M10V) += clk-milbeaut.o diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c new file mode 100644 index 000000000000..7487effceeab --- /dev/null +++ b/drivers/clk/clk-loongson2.c @@ -0,0 +1,286 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Author: Yinbo Zhu + * Copyright (C) 2022-2023 Loongson Technology Corporation Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LOONGSON2_PLL_MULT_SHIFT 32 +#define LOONGSON2_PLL_MULT_WIDTH 10 +#define LOONGSON2_PLL_DIV_SHIFT 26 +#define LOONGSON2_PLL_DIV_WIDTH 6 +#define LOONGSON2_APB_FREQSCALE_SHIFT 20 +#define LOONGSON2_APB_FREQSCALE_WIDTH 3 +#define LOONGSON2_USB_FREQSCALE_SHIFT 16 +#define LOONGSON2_USB_FREQSCALE_WIDTH 3 +#define LOONGSON2_SATA_FREQSCALE_SHIFT 12 +#define LOONGSON2_SATA_FREQSCALE_WIDTH 3 + +static void __iomem *loongson2_pll_base; + +static struct clk_hw *loongson2_clk_register(struct device *dev, + const char *name, + const char *parent_name, + const struct clk_ops *ops, + unsigned long flags) +{ + int ret; + struct clk_hw *hw; + struct clk_init_data init; + + /* allocate the divider */ + hw = kzalloc(sizeof(*hw), GFP_KERNEL); + if (!hw) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = ops; + init.flags = flags; + init.parent_names = (parent_name ? &parent_name : NULL); + init.num_parents = (parent_name ? 1 : 0); + hw->init = &init; + + /* register the clock */ + ret = clk_hw_register(dev, hw); + if (ret) { + kfree(hw); + hw = ERR_PTR(ret); + } + + return hw; +} + +static struct clk_hw *loongson2_clk_pll_register(const char *name, + const char *parent, void __iomem *reg) +{ + u64 val; + u32 mult = 1, div = 1; + + val = readq((void *)reg); + + mult = (val >> LOONGSON2_PLL_MULT_SHIFT) & + clk_div_mask(LOONGSON2_PLL_MULT_WIDTH); + div = (val >> LOONGSON2_PLL_DIV_SHIFT) & + clk_div_mask(LOONGSON2_PLL_DIV_WIDTH); + + return clk_hw_register_fixed_factor(NULL, name, parent, + CLK_SET_RATE_PARENT, mult, div); +} + +static unsigned long loongson2_apb_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + u64 val; + u32 mult; + unsigned long rate; + + val = readq((void *)(loongson2_pll_base + 0x50)); + + mult = (val >> LOONGSON2_APB_FREQSCALE_SHIFT) & + clk_div_mask(LOONGSON2_APB_FREQSCALE_WIDTH); + + rate = parent_rate * (mult + 1); + do_div(rate, 8); + + return rate; +} + +static const struct clk_ops loongson2_apb_clk_ops = { + .recalc_rate = loongson2_apb_recalc_rate, +}; + +static unsigned long loongson2_usb_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + u64 val; + u32 mult; + unsigned long rate; + + val = readq((void *)(loongson2_pll_base + 0x50)); + + mult = (val >> LOONGSON2_USB_FREQSCALE_SHIFT) & + clk_div_mask(LOONGSON2_USB_FREQSCALE_WIDTH); + + rate = parent_rate * (mult + 1); + do_div(rate, 8); + + return rate; +} + +static const struct clk_ops loongson2_usb_clk_ops = { + .recalc_rate = loongson2_usb_recalc_rate, +}; + +static unsigned long loongson2_sata_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + u64 val; + u32 mult; + unsigned long rate; + + val = readq((void *)(loongson2_pll_base + 0x50)); + + mult = (val >> LOONGSON2_SATA_FREQSCALE_SHIFT) & + clk_div_mask(LOONGSON2_SATA_FREQSCALE_WIDTH); + + rate = parent_rate * (mult + 1); + do_div(rate, 8); + + return rate; +} + +static const struct clk_ops loongson2_sata_clk_ops = { + .recalc_rate = loongson2_sata_recalc_rate, +}; + +static void loongson2_check_clk_hws(struct clk_hw *clks[], unsigned int count) +{ + unsigned int i; + + for (i = 0; i < count; i++) + if (IS_ERR(clks[i])) + pr_err("Loongson2 clk %u: register failed with %ld\n" + , i, PTR_ERR(clks[i])); +} + +static struct clk_hw *loongson2_obtain_fixed_clk_hw( + struct device_node *np, + const char *name) +{ + struct clk *clk; + + clk = of_clk_get_by_name(np, name); + if (IS_ERR(clk)) + return ERR_PTR(-ENOENT); + + return __clk_get_hw(clk); +} + +static void __init loongson2_clocks_init(struct device_node *np) +{ + struct clk_hw **hws; + struct clk_hw_onecell_data *clk_hw_data; + spinlock_t loongson2_clk_lock; + + loongson2_pll_base = of_iomap(np, 0); + + if (!loongson2_pll_base) { + pr_err("clk: unable to map loongson2 clk registers\n"); + goto err; + } + + clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, LOONGSON2_CLK_END), + GFP_KERNEL); + if (WARN_ON(!clk_hw_data)) + goto err; + + clk_hw_data->num = LOONGSON2_CLK_END; + hws = clk_hw_data->hws; + + hws[LOONGSON2_REF_100M] = loongson2_obtain_fixed_clk_hw(np, + "ref_100m"); + + hws[LOONGSON2_NODE_PLL] = loongson2_clk_pll_register("node_pll", + "ref_100m", + loongson2_pll_base); + + hws[LOONGSON2_DDR_PLL] = loongson2_clk_pll_register("ddr_pll", + "ref_100m", + loongson2_pll_base + 0x10); + + hws[LOONGSON2_DC_PLL] = loongson2_clk_pll_register("dc_pll", + "ref_100m", + loongson2_pll_base + 0x20); + + hws[LOONGSON2_PIX0_PLL] = loongson2_clk_pll_register("pix0_pll", + "ref_100m", + loongson2_pll_base + 0x30); + + hws[LOONGSON2_PIX1_PLL] = loongson2_clk_pll_register("pix1_pll", + "ref_100m", + loongson2_pll_base + 0x40); + + hws[LOONGSON2_NODE_CLK] = clk_hw_register_divider(NULL, "node", + "node_pll", 0, + loongson2_pll_base + 0x8, 0, + 6, CLK_DIVIDER_ONE_BASED, + &loongson2_clk_lock); + + /* + * The hda clk divisor in the upper 32bits and the clk-prodiver + * layer code doesn't support 64bit io operation thus a conversion + * is required that subtract shift by 32 and add 4byte to the hda + * address + */ + hws[LOONGSON2_HDA_CLK] = clk_hw_register_divider(NULL, "hda", + "ddr_pll", 0, + loongson2_pll_base + 0x22, 12, + 7, CLK_DIVIDER_ONE_BASED, + &loongson2_clk_lock); + + hws[LOONGSON2_GPU_CLK] = clk_hw_register_divider(NULL, "gpu", + "ddr_pll", 0, + loongson2_pll_base + 0x18, 22, + 6, CLK_DIVIDER_ONE_BASED, + &loongson2_clk_lock); + + hws[LOONGSON2_DDR_CLK] = clk_hw_register_divider(NULL, "ddr", + "ddr_pll", 0, + loongson2_pll_base + 0x18, 0, + 6, CLK_DIVIDER_ONE_BASED, + &loongson2_clk_lock); + + hws[LOONGSON2_GMAC_CLK] = clk_hw_register_divider(NULL, "gmac", + "dc_pll", 0, + loongson2_pll_base + 0x28, 22, + 6, CLK_DIVIDER_ONE_BASED, + &loongson2_clk_lock); + + hws[LOONGSON2_DC_CLK] = clk_hw_register_divider(NULL, "dc", + "dc_pll", 0, + loongson2_pll_base + 0x28, 0, + 6, CLK_DIVIDER_ONE_BASED, + &loongson2_clk_lock); + + hws[LOONGSON2_APB_CLK] = loongson2_clk_register(NULL, "apb", + "gmac", + &loongson2_apb_clk_ops, 0); + + hws[LOONGSON2_USB_CLK] = loongson2_clk_register(NULL, "usb", + "gmac", + &loongson2_usb_clk_ops, 0); + + hws[LOONGSON2_SATA_CLK] = loongson2_clk_register(NULL, "sata", + "gmac", + &loongson2_sata_clk_ops, 0); + + hws[LOONGSON2_PIX0_CLK] = clk_hw_register_divider(NULL, "pix0", + "pix0_pll", 0, + loongson2_pll_base + 0x38, 0, 6, + CLK_DIVIDER_ONE_BASED, + &loongson2_clk_lock); + + hws[LOONGSON2_PIX1_CLK] = clk_hw_register_divider(NULL, "pix1", + "pix1_pll", 0, + loongson2_pll_base + 0x48, 0, 6, + CLK_DIVIDER_ONE_BASED, + &loongson2_clk_lock); + + loongson2_check_clk_hws(hws, LOONGSON2_CLK_END); + + of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); + +err: + iounmap(loongson2_pll_base); +} + +CLK_OF_DECLARE(loongson2_clk, "loongson,ls2k-clk", loongson2_clocks_init); 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id g14-20020a1709065d0e00b0078049ab4bbasi1037255ejt.526.2022.11.28.19.44.51; Mon, 28 Nov 2022 19:45:14 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235556AbiK2DmO (ORCPT + 99 others); Mon, 28 Nov 2022 22:42:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59188 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235532AbiK2DmG (ORCPT ); Mon, 28 Nov 2022 22:42:06 -0500 Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id D3A5F4B779; Mon, 28 Nov 2022 19:42:04 -0800 (PST) Received: from loongson.cn (unknown [10.180.13.64]) by gateway (Coremail) with SMTP id _____8BxXeuLf4VjbOgBAA--.4562S3; Tue, 29 Nov 2022 11:42:03 +0800 (CST) Received: from localhost.localdomain (unknown [10.180.13.64]) by localhost.localdomain (Coremail) with SMTP id AQAAf8AxPuCGf4VjjecdAA--.10584S4; Tue, 29 Nov 2022 11:42:02 +0800 (CST) From: Yinbo Zhu To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Huacai Chen , WANG Xuerui , Jiaxun Yang , Jianmin Lv , Yang Li , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Yinbo Zhu Subject: [PATCH v10 3/4] LoongArch: time: add of_clk_init in time_init Date: Tue, 29 Nov 2022 11:41:56 +0800 Message-Id: <20221129034157.15036-3-zhuyinbo@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20221129034157.15036-1-zhuyinbo@loongson.cn> References: <20221129034157.15036-1-zhuyinbo@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8AxPuCGf4VjjecdAA--.10584S4 X-CM-SenderInfo: 52kx5xhqerqz5rrqw2lrqou0/ X-Coremail-Antispam: 1Uk129KBjvdXoW7Wr4UWFyruw17uw47ZFy5Arb_yoWfZrg_uw 17Cw1DWryfJ39ak34vq3ZxXw1jkw48tFn0vas7Zr17CFn7J3yUCw43Z343ArnI9as29rs5 ZrWrGF97Cr13KjkaLaAFLSUrUUUUnb8apTn2vfkv8UJUUUU8wcxFpf9Il3svdxBIdaVrn0 xqx4xG64xvF2IEw4CE5I8CrVC2j2Jv73VFW2AGmfu7bjvjm3AaLaJ3UjIYCTnIWjp_UUUY C7CY07I20VC2zVCF04k26cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r126r13M28lY4IEw2 IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84AC jcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM2 8EF7xvwVC2z280aVCY1x0267AKxVW8Jr0_Cr1UM2kKe7AKxVWUAVWUtwAS0I0E0xvYzxvE 52x082IY62kv0487Mc804VCY07AIYIkI8VC2zVCFFI0UMc02F40EFcxC0VAKzVAqx4xG6I 80ewAv7VC0I7IYx2IY67AKxVWUtVWrXwAv7VC2z280aVAFwI0_Cr0_Gr1UMcvjeVCFs4IE 7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCY1x0262kKe7AKxVWUAVWUtwCF04k20xvY0x 0EwIxGrwCF04k20xvE74AGY7Cv6cx26rWl4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1l4IxYO2xF xVAFwI0_JF0_Jw1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWw C2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Gr0_ Xr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJV WUCwCI42IY6I8E87Iv67AKxVWxJVW8Jr1lIxAIcVC2z280aVCY1x0267AKxVW8Jr0_Cr1U YxBIdaVFxhVjvjDU0xZFpf9x07UKXd8UUUUU= X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750800546418275091?= X-GMAIL-MSGID: =?utf-8?q?1750800546418275091?= The Loongson-2 clock controller driver used CLK_OF_DECLARE to register clock subsystem that ask of_clk_init was called in time_init and this patch was to addd such support. Signed-off-by: Yinbo Zhu Acked-by: Stephen Boyd --- arch/loongarch/kernel/time.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/loongarch/kernel/time.c b/arch/loongarch/kernel/time.c index 786735dcc8d6..09f20bc81798 100644 --- a/arch/loongarch/kernel/time.c +++ b/arch/loongarch/kernel/time.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -214,6 +215,8 @@ int __init constant_clocksource_init(void) void __init time_init(void) { + of_clk_init(NULL); + if (!cpu_has_cpucfg) const_clock_freq = cpu_clock_freq; else From patchwork Tue Nov 29 03:41:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yinbo Zhu X-Patchwork-Id: 27073 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp113612wrr; Mon, 28 Nov 2022 19:59:57 -0800 (PST) X-Google-Smtp-Source: AA0mqf7id3kK7+9KNIkqgC/+DZbj6iduUOElt2G3TM7YPWS7zZJfbs1W6QOyytv6MAMyN3uHlhhq X-Received: by 2002:a63:c42:0:b0:43c:3b6d:d6ab with SMTP id 2-20020a630c42000000b0043c3b6dd6abmr50878524pgm.52.1669694397529; Mon, 28 Nov 2022 19:59:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669694397; cv=none; d=google.com; s=arc-20160816; b=nZ6qM3xu9eo4UzlOm/yYANlNlq71augx+a8QssEOHStgnNCXGOHqcHXqLI5u2oHH+u klC8SB/R9mE5N7+o33edIpVhFjHHTPj+tSEWhll4cLlCNA7A1bQmJFbJ5waFQNChmIdl /etlSvaR60BU55d+6jBrWP2QUCQjuxylDw/L8Ar8bjACb0BEoXNL6Uiw+y7Mm6/XQX5K KOLjSQDcgBx+goE9GmKWDgkpDqjPeydgRrItBv8eToCsfbUOoAb9L/c4uZgAO0dHOtxg /dAR1A07urd/s6Q5XUW2PJSRyAYz+qTy0GN1mP+X09m77KhTKWVb1FH9h47QDVekNhbY DHeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=b9tpo5xJduOntFCMdWtgIICyGFEO6uRVHg0SiHrEwig=; b=P1SOHPE5kFvfo8bEfAB3XGpjoN1hxy0Sl33dMGC3pzINMQ+gtJueSN41YsNbaX4lms 4K/cKm+N7MLvt3vr7MzCunmSLTd5GYb0Q7XBGpmMmdSLrzcnrPt8OSh2dZAy6PULcPXJ KXqrfoobRjygSC439TST0t2ApMiJ2GnuK7yZaQYLHTJBte4DPtHVHElGwWwVfdLyXWQS n8pWhslkyCYtLYORVcVlX+lN05LsMofCTU9+2Hi5AurY10Usq+XO10bD3pgOL4e8jQBp ZIjl+gFrUrSvaYzYFVpBhslVmMZsEL0tD0VEstZwcw82fhJO6+qb4+o4tQvb9zZdMMbo tCzw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id j16-20020a170902da9000b00186dcc389a8si4384266plx.329.2022.11.28.19.59.44; Mon, 28 Nov 2022 19:59:57 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235533AbiK2DmV (ORCPT + 99 others); Mon, 28 Nov 2022 22:42:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59202 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235538AbiK2DmH (ORCPT ); Mon, 28 Nov 2022 22:42:07 -0500 Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id BC0EE4B985; Mon, 28 Nov 2022 19:42:05 -0800 (PST) Received: from loongson.cn (unknown [10.180.13.64]) by gateway (Coremail) with SMTP id _____8CxruuMf4Vjd+gBAA--.4653S3; Tue, 29 Nov 2022 11:42:04 +0800 (CST) Received: from localhost.localdomain (unknown [10.180.13.64]) by localhost.localdomain (Coremail) with SMTP id AQAAf8AxPuCGf4VjjecdAA--.10584S5; Tue, 29 Nov 2022 11:42:03 +0800 (CST) From: Yinbo Zhu To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Huacai Chen , WANG Xuerui , Jiaxun Yang , Jianmin Lv , Yang Li , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Yinbo Zhu Cc: Krzysztof Kozlowski Subject: [PATCH v10 4/4] dt-bindings: clock: add loongson-2 clock Date: Tue, 29 Nov 2022 11:41:57 +0800 Message-Id: <20221129034157.15036-4-zhuyinbo@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20221129034157.15036-1-zhuyinbo@loongson.cn> References: <20221129034157.15036-1-zhuyinbo@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8AxPuCGf4VjjecdAA--.10584S5 X-CM-SenderInfo: 52kx5xhqerqz5rrqw2lrqou0/ X-Coremail-Antispam: 1Uk129KBjvJXoWxXF47tF4DJw1xAFWruF1xKrg_yoW5tr1DpF sxCr95JrWIyF13uFsxKFyIywn5Za4xAFWDAw42ka42yr90gw15XF1xKa4UZ39xXr17Za9F vFyS9r4UCa1Uuw7anT9S1TB71UUUUjDqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj qI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUU bSxFc2x0x2IEx4CE42xK8VAvwI8IcIk0rVWrJVCq3wAFIxvE14AKwVWUXVWUAwA2ocxC64 kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28E F7xvwVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJwA2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr 1l84ACjcxK6I8E87Iv6xkF7I0E14v26F4UJVW0owAaw2AFwI0_JF0_Jw1le2I262IYc4CY 6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27wAqx4xG64xvF2IEw4CE5I8CrV C2j2WlYx0E2Ix0cI8IcVAFwI0_Jw0_WrylYx0Ex4A2jsIE14v26F4j6r4UJwAm72CE4IkC 6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lc7CjxVAaw2AFwI0_Jw0_GFyl42xK82IYc2 Ij64vIr41l42xK82IY6x8ErcxFaVAv8VWrMxC20s026xCaFVCjc4AY6r1j6r4UMxCIbckI 1I0E14v26r126r1DMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_Jr Wlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26ryj 6F1UMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr 0_JF4lIxAIcVC2z280aVAFwI0_Cr0_Gr1UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr1j6F4U JbIYCTnIWIevJa73UjIFyTuYvjxUwD7aUUUUU X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750801472918540885?= X-GMAIL-MSGID: =?utf-8?q?1750801472918540885?= Add the Loongson-2 clock binding with DT schema format using json-schema. Signed-off-by: Yinbo Zhu Reviewed-by: Krzysztof Kozlowski --- Change in v10: 1. NO change, but other patch in this series of patches has changes. Change in v9: 1. Add all history changlog information. Change in v8: 1. NO change, but other patch in this series of patches has changes. Change in v7: 1. NO change, but other patch in this series of patches has changes. Change in v6: 1. NO change, but other patch in this series of patches has changes. Change in v5: 1. NO change, but other patch in this series of patches has changes. Change in v4: 1. NO change, but other patch in this series of patches has changes. Change in v3: 1. Drop redundant (last) binding from the title. 2. Drop "- |" between ref_100m node and clk node. Change in v2: 1. Drop "Binding" string in the title. 2. Drop entire allOf and move the contents to top level. 3. Change string "refclk_100m" to "ref_100m". .../bindings/clock/loongson,ls2k-clk.yaml | 63 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml diff --git a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml new file mode 100644 index 000000000000..63a59015987e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/loongson,ls2k-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson-2 SoC Clock Control Module + +maintainers: + - Yinbo Zhu + +description: | + Loongson-2 SoC clock control module is an integrated clock controller, which + generates and supplies to all modules. + +properties: + compatible: + enum: + - loongson,ls2k-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: 100m ref + + clock-names: + items: + - const: ref_100m + + '#clock-cells': + const: 1 + description: + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/loongson,ls2k-clk.h + for the full list of Loongson-2 SoC clock IDs. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + ref_100m: clock-ref-100m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "ref_100m"; + }; + + clk: clock-controller@1fe00480 { + compatible = "loongson,ls2k-clk"; + reg = <0x1fe00480 0x58>; + #clock-cells = <1>; + clocks = <&ref_100m>; + clock-names = "ref_100m"; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 73fa56f1fd5d..0cdd1437c093 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12025,6 +12025,7 @@ LOONGSON-2 SOC SERIES CLOCK DRIVER M: Yinbo Zhu L: linux-clk@vger.kernel.org S: Maintained +F: Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml F: drivers/clk/clk-loongson2.c F: include/dt-bindings/clock/loongson,ls2k-clk.h