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[8.43.85.97]) by mx.google.com with ESMTPS id nc36-20020a1709071c2400b007ae8d01144dsi11677345ejc.717.2022.11.28.18.07.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Nov 2022 18:07:22 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=nAtCC5xh; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4CAD1385781A for ; Tue, 29 Nov 2022 02:07:21 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4CAD1385781A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1669687641; bh=9okEdy7TEmtvuheHevY62a7pOPZMIGK0aD0OYeF5Jio=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=nAtCC5xhSw88OXwd7rCmUV0twOGSOuPIPjjIsktmcC8DvGV7o6G1KJxWLF1COC0lk x2l0beSqM92zt/KP+FYTlusuulML38cKFZAE0G0vqq31DrBf3UP1mwWsVirNH6uCZg TsZsIdjx1VXNm4E8LWDt+GyhKl7fl4cS+B148+m0= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 9381A38582BE for ; Tue, 29 Nov 2022 02:07:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 9381A38582BE Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 03588300089; Tue, 29 Nov 2022 02:07:09 +0000 (UTC) To: Tsukasa OI Cc: binutils@sourceware.org Subject: [REVIEW ONLY v2 1/1] UNRATIFIED RISC-V: Add 'ZiCondOps' extension Date: Tue, 29 Nov 2022 02:06:57 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750791231121085826?= X-GMAIL-MSGID: =?utf-8?q?1750794389871924460?= From: Tsukasa OI [DO NOT MERGE] Until 'ZiCondOps' extension is frozen/ratified and final version number is determined, this patch should not be merged upstream. This commit uses version 1.0 as in the documentation. This commit adds support for the latest draft of RISC-V Integer Conditional Operations (ZiCondOps) extension consisting of 2 new instructions. This is based on the early draft of ZiCondOps on GitHub: bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_std_z_ext): Add 'ZiCondOps'. (riscv_multi_subset_supports): Support new instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zicondops.s: New test for 'ZiCondOps'. * testsuite/gas/riscv/zicondops.d: Likewise. * testsuite/gas/riscv/zicondops-noarch.d: New test for architecture failure. * testsuite/gas/riscv/zicondops-noarch.l: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_CZERO_EQZ, MASK_CZERO_EQZ, MATCH_CZERO_NEZ, MASK_CZERO_NEZ): New. * opcode/riscv.h (enum riscv_insn_class): Add new instruction class INSN_CLASS_ZICONDOPS. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Add new instructions from the 'ZiCondOps' extension. --- bfd/elfxx-riscv.c | 5 +++++ gas/testsuite/gas/riscv/zicondops-noarch.d | 3 +++ gas/testsuite/gas/riscv/zicondops-noarch.l | 3 +++ gas/testsuite/gas/riscv/zicondops.d | 11 +++++++++++ gas/testsuite/gas/riscv/zicondops.s | 3 +++ include/opcode/riscv-opc.h | 8 ++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 4 ++++ 8 files changed, 38 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zicondops-noarch.d create mode 100644 gas/testsuite/gas/riscv/zicondops-noarch.l create mode 100644 gas/testsuite/gas/riscv/zicondops.d create mode 100644 gas/testsuite/gas/riscv/zicondops.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 0bcf2fdcfa34..564fef205d01 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1168,6 +1168,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zicbom", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zicondops", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zicsr", ISA_SPEC_CLASS_20191213, 2, 0, 0 }, {"zicsr", ISA_SPEC_CLASS_20190608, 2, 0, 0 }, {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 }, @@ -2318,6 +2319,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "zicbop"); case INSN_CLASS_ZICBOZ: return riscv_subset_supports (rps, "zicboz"); + case INSN_CLASS_ZICONDOPS: + return riscv_subset_supports (rps, "zicondops"); case INSN_CLASS_ZICSR: return riscv_subset_supports (rps, "zicsr"); case INSN_CLASS_ZIFENCEI: @@ -2467,6 +2470,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "zicbop"; case INSN_CLASS_ZICBOZ: return "zicboz"; + case INSN_CLASS_ZICONDOPS: + return "zicondops"; case INSN_CLASS_ZICSR: return "zicsr"; case INSN_CLASS_ZIFENCEI: diff --git a/gas/testsuite/gas/riscv/zicondops-noarch.d b/gas/testsuite/gas/riscv/zicondops-noarch.d new file mode 100644 index 000000000000..4f01b10f42df --- /dev/null +++ b/gas/testsuite/gas/riscv/zicondops-noarch.d @@ -0,0 +1,3 @@ +#as: -march=rv32i +#source: zicondops.s +#error_output: zicondops-noarch.l diff --git a/gas/testsuite/gas/riscv/zicondops-noarch.l b/gas/testsuite/gas/riscv/zicondops-noarch.l new file mode 100644 index 000000000000..b665d6022b98 --- /dev/null +++ b/gas/testsuite/gas/riscv/zicondops-noarch.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: unrecognized opcode `czero\.eqz a0,a1,a2', extension `zicondops' required +.*: Error: unrecognized opcode `czero\.nez a3,a4,a5', extension `zicondops' required diff --git a/gas/testsuite/gas/riscv/zicondops.d b/gas/testsuite/gas/riscv/zicondops.d new file mode 100644 index 000000000000..16feba95c4d3 --- /dev/null +++ b/gas/testsuite/gas/riscv/zicondops.d @@ -0,0 +1,11 @@ +#as: -march=rv32i_zicondops +#source: zicondops.s +#objdump: -d + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+06c5d533[ ]+czero\.eqz[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+06f776b3[ ]+czero\.nez[ ]+a3,a4,a5 diff --git a/gas/testsuite/gas/riscv/zicondops.s b/gas/testsuite/gas/riscv/zicondops.s new file mode 100644 index 000000000000..dcf3d98ccd7e --- /dev/null +++ b/gas/testsuite/gas/riscv/zicondops.s @@ -0,0 +1,3 @@ +target: + czero.eqz a0, a1, a2 + czero.nez a3, a4, a5 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 06e3df0f5a63..0115539931fe 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2113,6 +2113,11 @@ #define MASK_CBO_INVAL 0xfff07fff #define MATCH_CBO_ZERO 0x40200f #define MASK_CBO_ZERO 0xfff07fff +/* ZiCondOps instructions. */ +#define MATCH_CZERO_EQZ 0x6005033 +#define MASK_CZERO_EQZ 0xfe00707f +#define MATCH_CZERO_NEZ 0x6007033 +#define MASK_CZERO_NEZ 0xfe00707f /* Zawrs intructions. */ #define MATCH_WRS_NTO 0x00d00073 #define MASK_WRS_NTO 0xffffffff @@ -3115,6 +3120,9 @@ DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN, MASK_CBO_CLEAN); DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH); DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL); DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO); +/* ZiCondOps instructions. */ +DECLARE_INSN(czero_eqz, MATCH_CZERO_EQZ, MASK_CZERO_EQZ) +DECLARE_INSN(czero_nez, MATCH_CZERO_NEZ, MASK_CZERO_NEZ) /* Zawrs instructions. */ DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO) DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index c3cbde600cb0..c482f6f4d9f2 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -375,6 +375,7 @@ enum riscv_insn_class INSN_CLASS_Q, INSN_CLASS_F_AND_C, INSN_CLASS_D_AND_C, + INSN_CLASS_ZICONDOPS, INSN_CLASS_ZICSR, INSN_CLASS_ZIFENCEI, INSN_CLASS_ZIHINTPAUSE, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 0e691544f9bc..311df46daa2d 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -935,6 +935,10 @@ const struct riscv_opcode riscv_opcodes[] = {"cbo.inval", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 }, {"cbo.zero", 0, INSN_CLASS_ZICBOZ, "0(s)", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 }, +/* ZiCondOps instructions. */ +{"czero.eqz", 0, INSN_CLASS_ZICONDOPS, "d,s,t", MATCH_CZERO_EQZ, MASK_CZERO_EQZ, match_opcode, 0 }, +{"czero.nez", 0, INSN_CLASS_ZICONDOPS, "d,s,t", MATCH_CZERO_NEZ, MASK_CZERO_NEZ, match_opcode, 0 }, + /* Zawrs instructions. */ {"wrs.nto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, match_opcode, 0 }, {"wrs.sto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO, match_opcode, 0 },