From patchwork Tue Nov 29 01:23:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 27013 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp56682wrr; Mon, 28 Nov 2022 17:25:58 -0800 (PST) X-Google-Smtp-Source: AA0mqf4aPYfZhUqVsUjV0Ea4l+fxAAgKJlmHCVJuo49yS7JzBsaHcKRS6fJjMQc2FhmaOHcC7NmP X-Received: by 2002:a17:906:52c8:b0:7ad:ba1e:1bac with SMTP id w8-20020a17090652c800b007adba1e1bacmr45965443ejn.528.1669685158664; Mon, 28 Nov 2022 17:25:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669685158; cv=none; d=google.com; s=arc-20160816; b=oq+pb0B5mw8bTYyamNcUHQqfuL0t45POAzvZKwUCNf7I04u0MkG/OtkW5wqzcA9noG 6ZoC8a7GfJcn1TKR+Ho7Gf4ba3w2F1lmuyHZPLkbB1N7thKpgOCW50Z6Wv/KFHpHv214 cWUER9tOJqY6aCUctSfiw4Q93mutvLJQBahiDp5RstXMALJ+F4eDWZZd/KF2ppROzx1H F3Fe0WuKsmOVEZJXsXAcxTVsHmA+wYV0iSwPqCaGLYMv99zJXQwbdJ9XRGGB4iARwCyg 9yQU5dObiiOgclzNkaRYmtwJ5jKeD4p296Ybm1Mbn5T/HwF/XNHx23SXQAQLm4WlziOL F7Og== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=PJMMrEdiwCvmAy1Mw3xBsl7KP2KRMHO6z78+bApWW8E=; b=Mvw/ka2a9EUMJW1d6JV7F5+S5I+HTYdc1tzzbIFRpdDm0ir5+NJP+m2JIBi1EvZMwL 0c4z++MXiOoX27xEQbK+4OBhsPw2ExqKXicaKYVoGRCDJk0zyPCfdslaEIGPYB1OYKVv S1IgNEUlyU530oA4OKG075ApZbdPzFhhTHlQtosvx3QgeaF7SE7imSP8cRxQR5MeElD9 YsrIsJh7JslixuXzn659VFkEY07Rs9E6DBFWkIoL09d0Z3U+C3SlUxg3L0y9pvm5l+FF FN1qeIrqLDwYGEIGw8mrHXUx4+LYasgtvpcjHOz1Z/HAHE8EmZvAV6fS8CCVs/X+Dmr1 eiUg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=TwpK2F0i; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id qa42-20020a17090786aa00b007ae26c753edsi12260236ejc.52.2022.11.28.17.25.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Nov 2022 17:25:58 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=TwpK2F0i; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8910F38362E8 for ; Tue, 29 Nov 2022 01:24:23 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8910F38362E8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1669685063; bh=PJMMrEdiwCvmAy1Mw3xBsl7KP2KRMHO6z78+bApWW8E=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=TwpK2F0iBjNhZbuBBcjEss3vQqX6/56nV8YJgECnF3GJrFlTeCNcdXgncRGPtHY74 U9wR5oeUSOkx+ahj4R3Voj6bBNwY0c13Mtv5mdZaazNJqXgQ8yZ6FUA6xDS7USrwYk otygLxgjSVOv1sxtLCtg/zGorfiJ+8Ggd7UycZww= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 05FB53839D82 for ; Tue, 29 Nov 2022 01:24:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 05FB53839D82 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 66255300089; Tue, 29 Nov 2022 01:24:11 +0000 (UTC) To: Tsukasa OI Cc: binutils@sourceware.org Subject: [REVIEW ONLY 1/3] RISC-V: Add "XUN@S" operand type Date: Tue, 29 Nov 2022 01:23:57 +0000 Message-Id: <0187562c00ee6c8ba82439bd61e46a1899b9f916.1669684988.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750791785066906888?= X-GMAIL-MSGID: =?utf-8?q?1750791785066906888?= From: Tsukasa OI This is a variant of operand type "XuN@S" but when disassembling, it's printed as a hexadecimal number. The author intends to use this operand type on: - Shift amount operands on 'P'-extension proposal's shift instructions (to make them consistent with regular shift instructions) - Landing pad label operand on the 'Zisslpcfi' extension proposal (because they allow three different precision of landing pad label [9, 17 and 25-bits] with up to three likely consecutive instructions with 9, 8 and 8-bit immediates respectively, printing them as binary- based will fit better to these instructions) gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn, riscv_ip): Add new operand type and its handling. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Print new operand type value as a hexadecimal number. --- gas/config/tc-riscv.c | 2 ++ opcodes/riscv-dis.c | 9 ++++++--- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 0682eb355241..b58b7bc0cb05 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1399,6 +1399,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */ goto use_imm; case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S. */ + case 'U': /* 'XUN@S' ... same but disassembled as hex. */ goto use_imm; use_imm: n = strtol (oparg + 1, (char **)&oparg, 10); @@ -3437,6 +3438,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, sign = true; goto parse_imm; case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S. */ + case 'U': /* 'XUN@S' ... same but disassembled as hex. */ sign = false; goto parse_imm; parse_imm: diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 0e1f3b4610aa..b3127dccb3e0 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -587,8 +587,9 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info size_t n; size_t s; bool sign; + char opch = *++oparg; - switch (*++oparg) + switch (opch) { case 'l': /* Literal. */ oparg++; @@ -603,6 +604,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info sign = true; goto print_imm; case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S. */ + case 'U': /* 'XUN@S' ... same but disassembled as hex. */ sign = false; goto print_imm; print_imm: @@ -613,8 +615,9 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info oparg--; if (!sign) - print (info->stream, dis_style_immediate, "%lu", - (unsigned long)EXTRACT_U_IMM (n, s, l)); + print (info->stream, dis_style_immediate, + opch == 'U' ? "0x%lx" : "%lu", + (unsigned long) EXTRACT_U_IMM (n, s, l)); else print (info->stream, dis_style_immediate, "%li", (signed long)EXTRACT_S_IMM (n, s, l)); From patchwork Tue Nov 29 01:23:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 27017 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp57318wrr; Mon, 28 Nov 2022 17:27:32 -0800 (PST) X-Google-Smtp-Source: AA0mqf7/FbXbt5sIUbbI1ZxhZt6G8wFglgK4qhf1LflrikkWobsIrOYYXVTaoOKvJhAefjolp4Kz X-Received: by 2002:a17:906:5050:b0:7b2:8f2c:a877 with SMTP id e16-20020a170906505000b007b28f2ca877mr20592694ejk.90.1669685252796; Mon, 28 Nov 2022 17:27:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669685252; cv=none; d=google.com; s=arc-20160816; b=JmwGFnKbbLthRYet66gQ0GHgxtgl3RomXyhC098VbTc4KdVwxfyXdF2H8EWG+iik24 x4ysUs/87ddDBBqj2xyKGn5WTBRk3hjJvpckHxyjZLtWGWuO3tgbEZF1Nw300jKis+G6 dshaUdO2WCmExzjix+HqlN6M97HR9xMZg2ejjAcwlyUFywLOdQ0EsXjPpDjJ3wXSjxJF RKZWejftTtOj59UWdtTw35e6uoB35+JXlAZv6FyoNz1o+Wwc/cfaAVGhSd3hYPS2cdQO PDBA+EujfLI4H8sB7avssjlvMjVp42vZSgHMIgVXXCvHUGaRE88qdvG2DpE+9yidaMsG RKhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=x45agduUqlVtPavFdpgWUMODMKuLbgEW9Icc3Q/5k5g=; b=rMtXq8K/4LclrknH7Jmein+TNjHNnuYhcqXsIx1XKVVrj7+eZasyCutLBLZhFCzfT0 GPmC66fcK96fMlOx4jgQyL3G/IUumJZ3vLDQ96oeT18TFnFd0GqD0TF2MOX50gQQkIfr ARfdvGblEFTq1exBL9NPEideipqksHbi7PQyrtZ6pReTAbrBTEPkr4tAqfQEPNjEK8Y2 wkF+M9m7Svu8yinYqGX9Ht07ETaBo6hlvLwqZlePPvD+tQxSFNP1usBKnXW8Y073/5QB YQ0m+e8qERPdNKhJNhm8vRyK8jPuAwXyqYKMBL9MeIOdl3ljKy86FUp72na7zMW1WHcZ +uTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=dOM81j99; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id he44-20020a1709073dac00b0078dee0fce23si11010051ejc.123.2022.11.28.17.27.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Nov 2022 17:27:32 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=dOM81j99; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2F8B238518A2 for ; Tue, 29 Nov 2022 01:25:24 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2F8B238518A2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1669685124; bh=x45agduUqlVtPavFdpgWUMODMKuLbgEW9Icc3Q/5k5g=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=dOM81j99AmsGV7k8JSlpchyEcVGjPavWhoxXY20Sx0fXVDAQfDtkEJaCWl9CA2oA/ ZIS4+VKlyugNIqy7FAT3DwQavNPBooNVAtmyh+ySo92l/FX2OO/yQKK7tFEPaH3t8o d9BO1go/YXmByf2B+P+/8Fm5qMPvl0szS3STgevY= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 745353852C50 for ; Tue, 29 Nov 2022 01:24:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 745353852C50 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id D4E02300089; Tue, 29 Nov 2022 01:24:21 +0000 (UTC) To: Tsukasa OI Cc: binutils@sourceware.org Subject: [REVIEW ONLY 2/3] UNRATIFIED RISC-V: Add 'Zisslpcfi' extension and its TENTATIVE CSRs Date: Tue, 29 Nov 2022 01:23:58 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750791768933894012?= X-GMAIL-MSGID: =?utf-8?q?1750791883531030297?= From: Tsukasa OI [DO NOT MERGE] Until 'Zisslpcfi' extension is frozen/ratified and final version number is determined, this patch should not be merged upstream. This commit uses unratified version 0.1 as in the documentation (instead of possible 1.0 after ratification). This commit adds RISC-V Shadow Stacks and Landing Pads (Zisslpcfi) and its CSRs based on the document version 0.1 (latest git revision): and a feedback from Mr. Andrew Waterman (through a private conversation: 'Zimop', not 'Zimops'). **Note** Because CSR addresses are not fixed yet, this commit uses tentative addresses (a part of custom CSR space). bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Add implication 'Zisslpcfi' -> 'Zicsr' and 'Zisslpcfi' -> 'Zimop'. (riscv_supported_std_z_ext): Add 'Zisslpcfi' extension to valid 'Z' extension list. Add 'Zimop' stub extension without actual definitions to valid 'Z' extension list. (riscv_multi_subset_supports): Add new instruction class handling. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add new CSR class. (riscv_csr_address): Add new CSR class handling. * testsuite/gas/riscv/csr.s: Add new CSR test. * testsuite/gas/riscv/csr-dw-regnums.s: Likewise. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/zisslpcfi.s: New test for CFI instructions. * testsuite/gas/riscv/zisslpcfi.d: Likewise. * testsuite/gas/riscv/zisslpcfi-noarch.d: New test for architecture failure. * testsuite/gas/riscv/zisslpcfi-noarch.l: Likewise. * testsuite/gas/riscv/zisslpcfi-fail.s: New failure test for CFI instructions. * testsuite/gas/riscv/zisslpcfi-fail.d: Likewise. * testsuite/gas/riscv/zisslpcfi-fail.l: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_SSPUSH, MASK_SSPUSH, MATCH_SSPOP, MASK_SSPOP, MATCH_SSPRR, MASK_SSPRR, MATCH_SSAMOSWAP, MASK_SSAMOSWAP, MATCH_SSCHKRA, MASK_SSCHKRA, MATCH_LPSLL, MASK_LPSLL, MATCH_LPCLL, MASK_LPCLL, MATCH_LPSML, MASK_LPSML, MATCH_LPCML, MASK_LPCML, MATCH_LPSUL, MASK_LPSUL, MATCH_LPCUL, MASK_LPCUL): New. (CSR_LPLR, CSR_SSP): New. * opcode/riscv.h (enum riscv_insn_class): Add new instruction class INSN_CLASS_ZISSLPCFI. opcodes/ChangeLog: * riscv-opc.c (match_rs1_nonzero): New. (riscv_opcodes): Add 'Zisslpcfi' instructions. --- bfd/elfxx-riscv.c | 8 ++++ gas/config/tc-riscv.c | 4 ++ gas/testsuite/gas/riscv/csr-dw-regnums.d | 2 + gas/testsuite/gas/riscv/csr-dw-regnums.s | 3 ++ gas/testsuite/gas/riscv/csr-version-1p10.d | 4 ++ gas/testsuite/gas/riscv/csr-version-1p10.l | 4 ++ gas/testsuite/gas/riscv/csr-version-1p11.d | 4 ++ gas/testsuite/gas/riscv/csr-version-1p11.l | 4 ++ gas/testsuite/gas/riscv/csr-version-1p12.d | 4 ++ gas/testsuite/gas/riscv/csr-version-1p12.l | 4 ++ gas/testsuite/gas/riscv/csr-version-1p9p1.d | 4 ++ gas/testsuite/gas/riscv/csr-version-1p9p1.l | 4 ++ gas/testsuite/gas/riscv/csr.s | 4 ++ gas/testsuite/gas/riscv/zisslpcfi-fail.d | 2 + gas/testsuite/gas/riscv/zisslpcfi-fail.l | 19 ++++++++++ gas/testsuite/gas/riscv/zisslpcfi-fail.s | 26 +++++++++++++ gas/testsuite/gas/riscv/zisslpcfi-noarch.d | 3 ++ gas/testsuite/gas/riscv/zisslpcfi-noarch.l | 24 ++++++++++++ gas/testsuite/gas/riscv/zisslpcfi.d | 31 ++++++++++++++++ gas/testsuite/gas/riscv/zisslpcfi.s | 26 +++++++++++++ include/opcode/riscv-opc.h | 41 +++++++++++++++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 19 ++++++++++ 23 files changed, 245 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zisslpcfi-fail.d create mode 100644 gas/testsuite/gas/riscv/zisslpcfi-fail.l create mode 100644 gas/testsuite/gas/riscv/zisslpcfi-fail.s create mode 100644 gas/testsuite/gas/riscv/zisslpcfi-noarch.d create mode 100644 gas/testsuite/gas/riscv/zisslpcfi-noarch.l create mode 100644 gas/testsuite/gas/riscv/zisslpcfi.d create mode 100644 gas/testsuite/gas/riscv/zisslpcfi.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 0bcf2fdcfa34..7efd44aeecf5 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1087,6 +1087,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zhinx", "zhinxmin", check_implicit_always}, {"zhinxmin", "zfinx", check_implicit_always}, {"zfinx", "zicsr", check_implicit_always}, + {"zisslpcfi", "zicsr", check_implicit_always}, + {"zisslpcfi", "zimop", check_implicit_always}, {"zk", "zkn", check_implicit_always}, {"zk", "zkr", check_implicit_always}, {"zk", "zkt", check_implicit_always}, @@ -1173,6 +1175,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 }, {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 }, {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, + {"zimop", ISA_SPEC_CLASS_DRAFT, 0, 1, 0 }, + {"zisslpcfi", ISA_SPEC_CLASS_DRAFT, 0, 1, 0 }, {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2318,6 +2322,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "zicbop"); case INSN_CLASS_ZICBOZ: return riscv_subset_supports (rps, "zicboz"); + case INSN_CLASS_ZISSLPCFI: + return riscv_subset_supports (rps, "zisslpcfi"); case INSN_CLASS_ZICSR: return riscv_subset_supports (rps, "zicsr"); case INSN_CLASS_ZIFENCEI: @@ -2467,6 +2473,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "zicbop"; case INSN_CLASS_ZICBOZ: return "zicboz"; + case INSN_CLASS_ZISSLPCFI: + return "zisslpcfi"; case INSN_CLASS_ZICSR: return "zicsr"; case INSN_CLASS_ZIFENCEI: diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index b58b7bc0cb05..bcfcef771784 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -67,6 +67,7 @@ enum riscv_csr_class CSR_CLASS_I, CSR_CLASS_I_32, /* rv32 only */ CSR_CLASS_F, /* f-ext only */ + CSR_CLASS_ZISSLPCFI, /* Zisslpcfi only */ CSR_CLASS_ZKR, /* zkr only */ CSR_CLASS_V, /* rvv only */ CSR_CLASS_DEBUG, /* debug CSR */ @@ -1037,6 +1038,9 @@ riscv_csr_address (const char *csr_name, case CSR_CLASS_F: extension = "f"; break; + case CSR_CLASS_ZISSLPCFI: + extension = "zisslpcfi"; + break; case CSR_CLASS_ZKR: extension = "zkr"; break; diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d index fd830666ab89..f3f0fc788953 100644 --- a/gas/testsuite/gas/riscv/csr-dw-regnums.d +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d @@ -399,6 +399,8 @@ Contents of the .* section: DW_CFA_offset_extended_sf: r4445 \(stimecmph\) at cfa\+1396 DW_CFA_offset_extended_sf: r4685 \(vstimecmp\) at cfa\+2356 DW_CFA_offset_extended_sf: r4701 \(vstimecmph\) at cfa\+2420 + DW_CFA_offset_extended_sf: r6144 \(lplr\) at cfa\+8192 + DW_CFA_offset_extended_sf: r6145 \(ssp\) at cfa\+8196 DW_CFA_offset_extended_sf: r4163 \(utval\) at cfa\+268 DW_CFA_offset_extended_sf: r4419 \(stval\) at cfa\+1292 DW_CFA_offset_extended_sf: r4480 \(satp\) at cfa\+1536 diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s index b8b0f7902297..bb0578964dee 100644 --- a/gas/testsuite/gas/riscv/csr-dw-regnums.s +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s @@ -400,6 +400,9 @@ _start: .cfi_offset stimecmph, 1396 .cfi_offset vstimecmp, 2356 .cfi_offset vstimecmph, 2420 + # Zisslpci extension + .cfi_offset lplr, 8192 + .cfi_offset ssp, 8196 # dropped .cfi_offset ubadaddr, 268 # aliases .cfi_offset sbadaddr, 1292 # aliases diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d index ee41e1025cce..c047e922d6ef 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p10.d +++ b/gas/testsuite/gas/riscv/csr-version-1p10.d @@ -773,6 +773,10 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+24d59073[ ]+csrw[ ]+vstimecmp,a1 [ ]+[0-9a-f]+:[ ]+25d02573[ ]+csrr[ ]+a0,vstimecmph [ ]+[0-9a-f]+:[ ]+25d59073[ ]+csrw[ ]+vstimecmph,a1 +[ ]+[0-9a-f]+:[ ]+80002573[ ]+csrr[ ]+a0,lplr +[ ]+[0-9a-f]+:[ ]+80059073[ ]+csrw[ ]+lplr,a1 +[ ]+[0-9a-f]+:[ ]+80102573[ ]+csrr[ ]+a0,ssp +[ ]+[0-9a-f]+:[ ]+80159073[ ]+csrw[ ]+ssp,a1 [ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,utval [ ]+[0-9a-f]+:[ ]+04359073[ ]+csrw[ ]+utval,a1 [ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,stval diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l index e677b78b8bb8..d0be49f4a206 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p10.l +++ b/gas/testsuite/gas/riscv/csr-version-1p10.l @@ -743,6 +743,10 @@ .*Warning: invalid CSR `vstimecmph', needs rv32i extension .*Warning: invalid CSR `vstimecmph', needs `h' extension .*Warning: invalid CSR `vstimecmph', needs `sstc' extension +.*Warning: invalid CSR `lplr', needs `zisslpcfi' extension +.*Warning: invalid CSR `lplr', needs `zisslpcfi' extension +.*Warning: invalid CSR `ssp', needs `zisslpcfi' extension +.*Warning: invalid CSR `ssp', needs `zisslpcfi' extension .*Warning: invalid CSR `ubadaddr' for the privileged spec `1.10' .*Warning: invalid CSR `ubadaddr' for the privileged spec `1.10' .*Warning: invalid CSR `sbadaddr' for the privileged spec `1.10' diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d index a83b1bf68f98..e04c406a9368 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p11.d +++ b/gas/testsuite/gas/riscv/csr-version-1p11.d @@ -773,6 +773,10 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+24d59073[ ]+csrw[ ]+vstimecmp,a1 [ ]+[0-9a-f]+:[ ]+25d02573[ ]+csrr[ ]+a0,vstimecmph [ ]+[0-9a-f]+:[ ]+25d59073[ ]+csrw[ ]+vstimecmph,a1 +[ ]+[0-9a-f]+:[ ]+80002573[ ]+csrr[ ]+a0,lplr +[ ]+[0-9a-f]+:[ ]+80059073[ ]+csrw[ ]+lplr,a1 +[ ]+[0-9a-f]+:[ ]+80102573[ ]+csrr[ ]+a0,ssp +[ ]+[0-9a-f]+:[ ]+80159073[ ]+csrw[ ]+ssp,a1 [ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,utval [ ]+[0-9a-f]+:[ ]+04359073[ ]+csrw[ ]+utval,a1 [ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,stval diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l index 81ca86ca7bcc..d5590eda9190 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p11.l +++ b/gas/testsuite/gas/riscv/csr-version-1p11.l @@ -741,6 +741,10 @@ .*Warning: invalid CSR `vstimecmph', needs rv32i extension .*Warning: invalid CSR `vstimecmph', needs `h' extension .*Warning: invalid CSR `vstimecmph', needs `sstc' extension +.*Warning: invalid CSR `lplr', needs `zisslpcfi' extension +.*Warning: invalid CSR `lplr', needs `zisslpcfi' extension +.*Warning: invalid CSR `ssp', needs `zisslpcfi' extension +.*Warning: invalid CSR `ssp', needs `zisslpcfi' extension .*Warning: invalid CSR `ubadaddr' for the privileged spec `1.11' .*Warning: invalid CSR `ubadaddr' for the privileged spec `1.11' .*Warning: invalid CSR `sbadaddr' for the privileged spec `1.11' diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d index 612aac280768..1c39668eaf96 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p12.d +++ b/gas/testsuite/gas/riscv/csr-version-1p12.d @@ -773,6 +773,10 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+24d59073[ ]+csrw[ ]+vstimecmp,a1 [ ]+[0-9a-f]+:[ ]+25d02573[ ]+csrr[ ]+a0,vstimecmph [ ]+[0-9a-f]+:[ ]+25d59073[ ]+csrw[ ]+vstimecmph,a1 +[ ]+[0-9a-f]+:[ ]+80002573[ ]+csrr[ ]+a0,lplr +[ ]+[0-9a-f]+:[ ]+80059073[ ]+csrw[ ]+lplr,a1 +[ ]+[0-9a-f]+:[ ]+80102573[ ]+csrr[ ]+a0,ssp +[ ]+[0-9a-f]+:[ ]+80159073[ ]+csrw[ ]+ssp,a1 [ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,0x43 [ ]+[0-9a-f]+:[ ]+04359073[ ]+csrw[ ]+0x43,a1 [ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,stval diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l index 1c0bb4ef2d8f..e2aa6c8e66dd 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p12.l +++ b/gas/testsuite/gas/riscv/csr-version-1p12.l @@ -603,6 +603,10 @@ .*Warning: invalid CSR `vstimecmph', needs rv32i extension .*Warning: invalid CSR `vstimecmph', needs `h' extension .*Warning: invalid CSR `vstimecmph', needs `sstc' extension +.*Warning: invalid CSR `lplr', needs `zisslpcfi' extension +.*Warning: invalid CSR `lplr', needs `zisslpcfi' extension +.*Warning: invalid CSR `ssp', needs `zisslpcfi' extension +.*Warning: invalid CSR `ssp', needs `zisslpcfi' extension .*Warning: invalid CSR `ubadaddr' for the privileged spec `1.12' .*Warning: invalid CSR `ubadaddr' for the privileged spec `1.12' .*Warning: invalid CSR `sbadaddr' for the privileged spec `1.12' diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.d b/gas/testsuite/gas/riscv/csr-version-1p9p1.d index 0fe849c269c2..40464002374b 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p9p1.d +++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.d @@ -773,6 +773,10 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+24d59073[ ]+csrw[ ]+vstimecmp,a1 [ ]+[0-9a-f]+:[ ]+25d02573[ ]+csrr[ ]+a0,vstimecmph [ ]+[0-9a-f]+:[ ]+25d59073[ ]+csrw[ ]+vstimecmph,a1 +[ ]+[0-9a-f]+:[ ]+80002573[ ]+csrr[ ]+a0,lplr +[ ]+[0-9a-f]+:[ ]+80059073[ ]+csrw[ ]+lplr,a1 +[ ]+[0-9a-f]+:[ ]+80102573[ ]+csrr[ ]+a0,ssp +[ ]+[0-9a-f]+:[ ]+80159073[ ]+csrw[ ]+ssp,a1 [ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,ubadaddr [ ]+[0-9a-f]+:[ ]+04359073[ ]+csrw[ ]+ubadaddr,a1 [ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,sbadaddr diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.l b/gas/testsuite/gas/riscv/csr-version-1p9p1.l index c65d0b48e414..7666c9260bd4 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p9p1.l +++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.l @@ -793,6 +793,10 @@ .*Warning: invalid CSR `vstimecmph', needs rv32i extension .*Warning: invalid CSR `vstimecmph', needs `h' extension .*Warning: invalid CSR `vstimecmph', needs `sstc' extension +.*Warning: invalid CSR `lplr', needs `zisslpcfi' extension +.*Warning: invalid CSR `lplr', needs `zisslpcfi' extension +.*Warning: invalid CSR `ssp', needs `zisslpcfi' extension +.*Warning: invalid CSR `ssp', needs `zisslpcfi' extension .*Warning: invalid CSR `utval' for the privileged spec `1.9.1' .*Warning: invalid CSR `utval' for the privileged spec `1.9.1' .*Warning: invalid CSR `fflags', needs `f' extension diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s index c7406ce34c2e..1ae2cc1c49de 100644 --- a/gas/testsuite/gas/riscv/csr.s +++ b/gas/testsuite/gas/riscv/csr.s @@ -433,6 +433,10 @@ csr vstimecmp csr vstimecmph + # Control flow integrity + csr lplr + csr ssp + # Supported in previous priv spec, but dropped now csr ubadaddr # 0x043 in 1.9.1, but the value is utval since 1.10 diff --git a/gas/testsuite/gas/riscv/zisslpcfi-fail.d b/gas/testsuite/gas/riscv/zisslpcfi-fail.d new file mode 100644 index 000000000000..6a949a6b6bd7 --- /dev/null +++ b/gas/testsuite/gas/riscv/zisslpcfi-fail.d @@ -0,0 +1,2 @@ +#as: -march=rv32i_zisslpcfi +#error_output: zisslpcfi-fail.l diff --git a/gas/testsuite/gas/riscv/zisslpcfi-fail.l b/gas/testsuite/gas/riscv/zisslpcfi-fail.l new file mode 100644 index 000000000000..86ab28c5744a --- /dev/null +++ b/gas/testsuite/gas/riscv/zisslpcfi-fail.l @@ -0,0 +1,19 @@ +.*: Assembler messages: +.*: Error: illegal operands `sspush x0' +.*: Error: illegal operands `sspop x0' +.*: Error: illegal operands `ssamoswap x0,t1,t2' +.*: Error: illegal operands `sschkra x0,x0' +.*: Error: illegal operands `sschkra x1,x5' +.*: Error: illegal operands `sschkra x31,x31' +.*: Error: improper immediate value \(-?[0-9]+\) +.*: Error: improper immediate value \(512\) +.*: Error: improper immediate value \(-?[0-9]+\) +.*: Error: improper immediate value \(512\) +.*: Error: improper immediate value \(-?[0-9]+\) +.*: Error: improper immediate value \(256\) +.*: Error: improper immediate value \(-?[0-9]+\) +.*: Error: improper immediate value \(256\) +.*: Error: improper immediate value \(-?[0-9]+\) +.*: Error: improper immediate value \(256\) +.*: Error: improper immediate value \(-?[0-9]+\) +.*: Error: improper immediate value \(256\) diff --git a/gas/testsuite/gas/riscv/zisslpcfi-fail.s b/gas/testsuite/gas/riscv/zisslpcfi-fail.s new file mode 100644 index 000000000000..f326f6e3e507 --- /dev/null +++ b/gas/testsuite/gas/riscv/zisslpcfi-fail.s @@ -0,0 +1,26 @@ +target: + # sspush / sspop: using x0 is not allowed. + sspush x0 + sspop x0 + + # ssamoswap: using x0 to destination is not allowed. + ssamoswap x0, t1, t2 + + # sschkra: only "sschkra x5, x1 (or t0, ra)" is allowed. + sschkra x0, x0 + sschkra x1, x5 + sschkra x31, x31 + + # lp*: lplr.LL is 9-bit width, lplr.{ML,UL} are 8-bit width. + lpsll -1 + lpsll 0x200 + lpcll -1 + lpcll 0x200 + lpsml -1 + lpsml 0x100 + lpcml -1 + lpcml 0x100 + lpsul -1 + lpsul 0x100 + lpcul -1 + lpcul 0x100 diff --git a/gas/testsuite/gas/riscv/zisslpcfi-noarch.d b/gas/testsuite/gas/riscv/zisslpcfi-noarch.d new file mode 100644 index 000000000000..78acc704582f --- /dev/null +++ b/gas/testsuite/gas/riscv/zisslpcfi-noarch.d @@ -0,0 +1,3 @@ +#as: -march=rv32i +#source: zisslpcfi.s +#error_output: zisslpcfi-noarch.l diff --git a/gas/testsuite/gas/riscv/zisslpcfi-noarch.l b/gas/testsuite/gas/riscv/zisslpcfi-noarch.l new file mode 100644 index 000000000000..60759c816bce --- /dev/null +++ b/gas/testsuite/gas/riscv/zisslpcfi-noarch.l @@ -0,0 +1,24 @@ +.*: Assembler messages: +.*: Error: unrecognized opcode `sspush x1', extension `zisslpcfi' required +.*: Error: unrecognized opcode `sspush x5', extension `zisslpcfi' required +.*: Error: unrecognized opcode `sspop x1', extension `zisslpcfi' required +.*: Error: unrecognized opcode `sspop x5', extension `zisslpcfi' required +.*: Error: unrecognized opcode `ssprr x0', extension `zisslpcfi' required +.*: Error: unrecognized opcode `ssprr a0', extension `zisslpcfi' required +.*: Error: unrecognized opcode `ssamoswap a1,a2,a3', extension `zisslpcfi' required +.*: Error: unrecognized opcode `ssamoswap t0,a0,x0', extension `zisslpcfi' required +.*: Error: unrecognized opcode `ssamoswap a4,x0,a5', extension `zisslpcfi' required +.*: Error: unrecognized opcode `sschkra x5,x1', extension `zisslpcfi' required +.*: Error: unrecognized opcode `sschkra t0,ra', extension `zisslpcfi' required +.*: Error: unrecognized opcode `lpsll 0x000', extension `zisslpcfi' required +.*: Error: unrecognized opcode `lpsll 0x1ff', extension `zisslpcfi' required +.*: Error: unrecognized opcode `lpcll 0x000', extension `zisslpcfi' required +.*: Error: unrecognized opcode `lpcll 0x1ff', extension `zisslpcfi' required +.*: Error: unrecognized opcode `lpsml 0x00', extension `zisslpcfi' required +.*: Error: unrecognized opcode `lpsml 0xff', extension `zisslpcfi' required +.*: Error: unrecognized opcode `lpcml 0x00', extension `zisslpcfi' required +.*: Error: unrecognized opcode `lpcml 0xff', extension `zisslpcfi' required +.*: Error: unrecognized opcode `lpsul 0x00', extension `zisslpcfi' required +.*: Error: unrecognized opcode `lpsul 0xff', extension `zisslpcfi' required +.*: Error: unrecognized opcode `lpcul 0x00', extension `zisslpcfi' required +.*: Error: unrecognized opcode `lpcul 0xff', extension `zisslpcfi' required diff --git a/gas/testsuite/gas/riscv/zisslpcfi.d b/gas/testsuite/gas/riscv/zisslpcfi.d new file mode 100644 index 000000000000..b4d0fb4a4abe --- /dev/null +++ b/gas/testsuite/gas/riscv/zisslpcfi.d @@ -0,0 +1,31 @@ +#as: -march=rv32i_zisslpcfi +#objdump: -d + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+81c0c073[ ]+sspush[ ]+ra +[ ]+[0-9a-f]+:[ ]+81c2c073[ ]+sspush[ ]+t0 +[ ]+[0-9a-f]+:[ ]+81c040f3[ ]+sspop[ ]+ra +[ ]+[0-9a-f]+:[ ]+81c042f3[ ]+sspop[ ]+t0 +[ ]+[0-9a-f]+:[ ]+81d04073[ ]+ssprr[ ]+zero +[ ]+[0-9a-f]+:[ ]+81d04573[ ]+ssprr[ ]+a0 +[ ]+[0-9a-f]+:[ ]+82d645f3[ ]+ssamoswap[ ]+a1,a2,a3 +[ ]+[0-9a-f]+:[ ]+820542f3[ ]+ssamoswap[ ]+t0,a0,zero +[ ]+[0-9a-f]+:[ ]+82f04773[ ]+ssamoswap[ ]+a4,zero,a5 +[ ]+[0-9a-f]+:[ ]+8a12c073[ ]+sschkra[ ]+t0,ra +[ ]+[0-9a-f]+:[ ]+8a12c073[ ]+sschkra[ ]+t0,ra +[ ]+[0-9a-f]+:[ ]+82004073[ ]+lpsll[ ]+0x0 +[ ]+[0-9a-f]+:[ ]+82ffc073[ ]+lpsll[ ]+0x1ff +[ ]+[0-9a-f]+:[ ]+83004073[ ]+lpcll[ ]+0x0 +[ ]+[0-9a-f]+:[ ]+83ffc073[ ]+lpcll[ ]+0x1ff +[ ]+[0-9a-f]+:[ ]+86004073[ ]+lpsml[ ]+0x0 +[ ]+[0-9a-f]+:[ ]+867fc073[ ]+lpsml[ ]+0xff +[ ]+[0-9a-f]+:[ ]+86804073[ ]+lpcml[ ]+0x0 +[ ]+[0-9a-f]+:[ ]+86ffc073[ ]+lpcml[ ]+0xff +[ ]+[0-9a-f]+:[ ]+87004073[ ]+lpsul[ ]+0x0 +[ ]+[0-9a-f]+:[ ]+877fc073[ ]+lpsul[ ]+0xff +[ ]+[0-9a-f]+:[ ]+87804073[ ]+lpcul[ ]+0x0 +[ ]+[0-9a-f]+:[ ]+87ffc073[ ]+lpcul[ ]+0xff diff --git a/gas/testsuite/gas/riscv/zisslpcfi.s b/gas/testsuite/gas/riscv/zisslpcfi.s new file mode 100644 index 000000000000..a69befc95929 --- /dev/null +++ b/gas/testsuite/gas/riscv/zisslpcfi.s @@ -0,0 +1,26 @@ +target: + # Shadow stack instructions + sspush x1 + sspush x5 + sspop x1 + sspop x5 + ssprr x0 + ssprr a0 + ssamoswap a1, a2, a3 + ssamoswap t0, a0, x0 + ssamoswap a4, x0, a5 + sschkra x5, x1 + sschkra t0, ra + # Landing pad instructions + lpsll 0x000 + lpsll 0x1ff + lpcll 0x000 + lpcll 0x1ff + lpsml 0x00 + lpsml 0xff + lpcml 0x00 + lpcml 0xff + lpsul 0x00 + lpsul 0xff + lpcul 0x00 + lpcul 0xff diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 06e3df0f5a63..7e2e0b64aa8b 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2113,6 +2113,29 @@ #define MASK_CBO_INVAL 0xfff07fff #define MATCH_CBO_ZERO 0x40200f #define MASK_CBO_ZERO 0xfff07fff +/* Zisslpcfi instructions. */ +#define MATCH_SSPUSH 0x81c04073 +#define MASK_SSPUSH 0xfff07fff +#define MATCH_SSPOP 0x81c04073 +#define MASK_SSPOP 0xfffff07f +#define MATCH_SSPRR 0x81d04073 +#define MASK_SSPRR 0xfffff07f +#define MATCH_SSAMOSWAP 0x82004073 +#define MASK_SSAMOSWAP 0xfe00707f +#define MATCH_SSCHKRA 0x8a12c073 +#define MASK_SSCHKRA 0xffffffff +#define MATCH_LPSLL 0x82004073 +#define MASK_LPSLL 0xff007fff +#define MATCH_LPCLL 0x83004073 +#define MASK_LPCLL 0xff007fff +#define MATCH_LPSML 0x86004073 +#define MASK_LPSML 0xff807fff +#define MATCH_LPCML 0x86804073 +#define MASK_LPCML 0xff807fff +#define MATCH_LPSUL 0x87004073 +#define MASK_LPSUL 0xff807fff +#define MATCH_LPCUL 0x87804073 +#define MASK_LPCUL 0xff807fff /* Zawrs intructions. */ #define MATCH_WRS_NTO 0x00d00073 #define MASK_WRS_NTO 0xffffffff @@ -2752,6 +2775,9 @@ #define CSR_STIMECMPH 0x15d #define CSR_VSTIMECMP 0x24d #define CSR_VSTIMECMPH 0x25d +/* Zisslpcfi extension CSR addresses. */ +#define CSR_LPLR 0x800 /* TENTATIVELY use custom CSR address. */ +#define CSR_SSP 0x801 /* TENTATIVELY use custom CSR address. */ /* Unprivileged Floating-Point CSR addresses. */ #define CSR_FFLAGS 0x1 #define CSR_FRM 0x2 @@ -3115,6 +3141,18 @@ DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN, MASK_CBO_CLEAN); DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH); DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL); DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO); +/* Zisslpcfi instructions. */ +DECLARE_INSN(sspush, MATCH_SSPUSH, MASK_SSPUSH) +DECLARE_INSN(sspop, MATCH_SSPOP, MASK_SSPOP) +DECLARE_INSN(ssprr, MATCH_SSPRR, MASK_SSPRR) +DECLARE_INSN(ssamoswap, MATCH_SSAMOSWAP, MASK_SSAMOSWAP) +DECLARE_INSN(sschkra, MATCH_SSCHKRA, MASK_SSCHKRA) +DECLARE_INSN(lpsll, MATCH_LPSLL, MASK_LPSLL) +DECLARE_INSN(lpcll, MATCH_LPCLL, MASK_LPCLL) +DECLARE_INSN(lpsml, MATCH_LPSML, MASK_LPSML) +DECLARE_INSN(lpcml, MATCH_LPCML, MASK_LPCML) +DECLARE_INSN(lpsul, MATCH_LPSUL, MASK_LPSUL) +DECLARE_INSN(lpcul, MATCH_LPCUL, MASK_LPCUL) /* Zawrs instructions. */ DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO) DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) @@ -3648,6 +3686,9 @@ DECLARE_CSR(utval, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS DECLARE_CSR(uip, CSR_UIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P12) DECLARE_CSR(sedeleg, CSR_SEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P12) DECLARE_CSR(sideleg, CSR_SIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P12) +/* Zisslpcfi extension CSRs. */ +DECLARE_CSR(lplr, CSR_LPLR, CSR_CLASS_ZISSLPCFI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(ssp, CSR_SSP, CSR_CLASS_ZISSLPCFI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) /* Unprivileged Floating-Point CSRs. */ DECLARE_CSR(fflags, CSR_FFLAGS, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(frm, CSR_FRM, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index c3cbde600cb0..0c548fb2bb42 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -409,6 +409,7 @@ enum riscv_insn_class INSN_CLASS_ZICBOM, INSN_CLASS_ZICBOP, INSN_CLASS_ZICBOZ, + INSN_CLASS_ZISSLPCFI, INSN_CLASS_H, INSN_CLASS_XTHEADBA, INSN_CLASS_XTHEADBB, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 0e691544f9bc..dc328b0b377c 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -171,6 +171,12 @@ match_rd_nonzero (const struct riscv_opcode *op, insn_t insn) return match_opcode (op, insn) && ((insn & MASK_RD) != 0); } +static int +match_rs1_nonzero (const struct riscv_opcode *op, insn_t insn) +{ + return match_opcode (op, insn) && ((insn & MASK_RS1) != 0); +} + static int match_c_add (const struct riscv_opcode *op, insn_t insn) { @@ -935,6 +941,19 @@ const struct riscv_opcode riscv_opcodes[] = {"cbo.inval", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 }, {"cbo.zero", 0, INSN_CLASS_ZICBOZ, "0(s)", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 }, +/* Zisslpcfi instructions. */ +{"sspush", 0, INSN_CLASS_ZISSLPCFI, "s", MATCH_SSPUSH, MASK_SSPUSH, match_rs1_nonzero, INSN_DREF }, +{"sspop", 0, INSN_CLASS_ZISSLPCFI, "d", MATCH_SSPOP, MASK_SSPOP, match_rd_nonzero, INSN_DREF }, +{"ssprr", 0, INSN_CLASS_ZISSLPCFI, "d", MATCH_SSPRR, MASK_SSPRR, match_opcode, 0 }, +{"ssamoswap", 0, INSN_CLASS_ZISSLPCFI, "d,s,t", MATCH_SSAMOSWAP, MASK_SSAMOSWAP, match_rd_nonzero, INSN_DREF }, +{"sschkra", 0, INSN_CLASS_ZISSLPCFI, "s,t", MATCH_SSCHKRA, MASK_SSCHKRA, match_opcode, 0 }, +{"lpsll", 0, INSN_CLASS_ZISSLPCFI, "XU9@15", MATCH_LPSLL, MASK_LPSLL, match_opcode, 0 }, +{"lpcll", 0, INSN_CLASS_ZISSLPCFI, "XU9@15", MATCH_LPCLL, MASK_LPCLL, match_opcode, 0 }, +{"lpsml", 0, INSN_CLASS_ZISSLPCFI, "XU8@15", MATCH_LPSML, MASK_LPSML, match_opcode, 0 }, +{"lpcml", 0, INSN_CLASS_ZISSLPCFI, "XU8@15", MATCH_LPCML, MASK_LPCML, match_opcode, 0 }, +{"lpsul", 0, INSN_CLASS_ZISSLPCFI, "XU8@15", MATCH_LPSUL, MASK_LPSUL, match_opcode, 0 }, +{"lpcul", 0, INSN_CLASS_ZISSLPCFI, "XU8@15", MATCH_LPCUL, MASK_LPCUL, match_opcode, 0 }, + /* Zawrs instructions. */ {"wrs.nto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, match_opcode, 0 }, {"wrs.sto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO, match_opcode, 0 }, From patchwork Tue Nov 29 01:23:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 27018 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp57628wrr; Mon, 28 Nov 2022 17:28:12 -0800 (PST) X-Google-Smtp-Source: AA0mqf6yjCgdefWBBD85eRKjK1E2km9g0YPwdfVedaCYAUh1VDNzWK3a0tVju23xxNEYL/DEBiVX X-Received: by 2002:a17:906:3ad6:b0:7ae:40b7:7fbe with SMTP id z22-20020a1709063ad600b007ae40b77fbemr44280476ejd.371.1669685292660; Mon, 28 Nov 2022 17:28:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669685292; 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[8.43.85.97]) by mx.google.com with ESMTPS id cw9-20020a170906478900b007c080a3f372si1355144ejc.363.2022.11.28.17.28.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Nov 2022 17:28:12 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=x9D6AGqm; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B8EAB38518AE for ; Tue, 29 Nov 2022 01:26:27 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B8EAB38518AE DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1669685187; bh=UByC+I3v3y5SMspeqABkF/WfYMTmEqc3Xua09V7fMXc=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=x9D6AGqmwsKqeXGxhaYCYA4Gr2SGjIjha8XzY9G5NqnrlQF/NV5Wu9w6lwsKCzDJ3 Dvgxpsw521VyAGY8CIKZAwhJTmpFTNhwMN187YKtmIlj96LpamvOxn40UOe7dF7sPG ZetgRL8zHm2iXvFrAau6bSrj6PugS9brDRbpW7ag= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id F09C63832D00 for ; Tue, 29 Nov 2022 01:24:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org F09C63832D00 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 5E4BF300089; Tue, 29 Nov 2022 01:24:32 +0000 (UTC) To: Tsukasa OI Cc: binutils@sourceware.org Subject: [REVIEW ONLY 3/3] TEST: Add instantiation script on CSR allocation Date: Tue, 29 Nov 2022 01:23:59 +0000 Message-Id: <73828cb4ccf8c03275b6af7e42872d661dea267f.1669684988.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750791925847690831?= X-GMAIL-MSGID: =?utf-8?q?1750791925847690831?= From: Tsukasa OI --- instantiate-zisslpcfi.sh | 127 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 127 insertions(+) create mode 100755 instantiate-zisslpcfi.sh diff --git a/instantiate-zisslpcfi.sh b/instantiate-zisslpcfi.sh new file mode 100755 index 000000000000..a6bb0dfd763b --- /dev/null +++ b/instantiate-zisslpcfi.sh @@ -0,0 +1,127 @@ +#! /bin/bash +# SPDX-License-Identifier: CC0-1.0 +# Author: Tsukasa OI +# Year: 2022 + +check_csr_addr () +{ + ADDR="$1" + case "$ADDR" in + 0x* | 0X*) + ADDR="${ADDR#??}" + ;; + esac + case "$ADDR" in + [0-9a-fA-F]) + ADDR=00$ADDR + ;; + [0-9a-fA-F][0-9a-fA-F]) + ADDR=0$ADDR + ;; + [0-9a-fA-F][0-9a-fA-F][0-9a-fA-F]) + ;; + *) + echo "ERROR: \`$1' is not a valid CSR address for \`$2'." 1>&2 + exit 1 + ;; + esac + ADDR=$(echo $ADDR | tr A-F a-f) + printf %s $ADDR + return 0 +} + +canonicalize_hex () +{ + ADDR=$1 + while : + do + case $ADDR in + 0) + break + ;; + 0?*) + ADDR=${ADDR#0} + ;; + *) + break + ;; + esac + done + printf 0x%s $ADDR +} + +dwarf_regnum () +{ + echo -n $(($1 + 4096)) +} + +dwarf_offset () +{ + echo -n $(($1 * 4)) +} + +test_path () +{ + if test '!' -f "$1" + then + echo "ERROR: file \`$1' is not found." 1>&2 + exit 1 + fi +} + +CSRS=( + lplr + ssp +) + +if test $# -ne ${#CSRS[@]} +then + ERRMSG="usage: $0" + for CSR in ${CSRS[@]} + do + CSR_UPPER=$(echo $CSR | tr a-z A-Z) + ERRMSG="$ERRMSG ADDR_${CSR_UPPER}" + done + echo "$ERRMSG" 1>&2 + exit 1 +fi + +PRIV_VERSIONS="1p9p1 1p10 1p11 1p12" + +test_path include/opcode/riscv-opc.h +for V in $PRIV_VERSIONS +do + test_path gas/testsuite/gas/riscv/csr-version-$V.d +done +test_path gas/testsuite/gas/riscv/csr-dw-regnums.s +test_path gas/testsuite/gas/riscv/csr-dw-regnums.d + +do_csr_instantiation () +{ + CSR="$1" + CSR_UPPER=$(echo $CSR | tr a-z A-Z) + ADDR=$(check_csr_addr "$2" $CSR) + HEXC=$(canonicalize_hex $ADDR) + DWREG=$(dwarf_regnum $HEXC) + DWOFF=$(dwarf_offset $HEXC) + ORIG_ADDR=$(grep "a0,${CSR}\$" gas/testsuite/gas/riscv/csr-version-1p12.d | head -n 1 | sed 's/.*+\([0-9a-f]\{3\}\)02573.*/\1/') + sed -i "s/^#define CSR_${CSR_UPPER} .*/#define CSR_${CSR_UPPER} $HEXC/" include/opcode/riscv-opc.h + for V in $PRIV_VERSIONS + do + sed -i "s/+${ORIG_ADDR}\\(02573\\|59073\\)/+${ADDR}\\1/" gas/testsuite/gas/riscv/csr-version-$V.d + done + sed -i "s/\\.cfi_offset ${CSR}, .*/.cfi_offset ${CSR}, ${DWOFF}/" gas/testsuite/gas/riscv/csr-dw-regnums.s + sed -i "s/DW_CFA_offset_extended_sf: r[0-9]\\+ \\\\(${CSR}\\\\) at cfa\\\\+[0-9]\\+/DW_CFA_offset_extended_sf: r${DWREG} \\\\(${CSR}\\\\) at cfa\\\\+${DWOFF}/" gas/testsuite/gas/riscv/csr-dw-regnums.d +} + +for CSR in ${CSRS[@]} +do + do_csr_instantiation $CSR "$1" + shift +done + +if test -f "$0" +then + rm -f "$0" +fi +exit 0