From patchwork Tue Nov 29 01:22:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 27009 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp56522wrr; Mon, 28 Nov 2022 17:25:34 -0800 (PST) X-Google-Smtp-Source: AA0mqf7CS5XPPk3c7Szf5z2lZ6otmobxYGz1M2aG5XISwFFImgy49NVs8veHnN55XmAujwQOPUK1 X-Received: by 2002:a17:906:2dda:b0:7bd:6149:2097 with SMTP id h26-20020a1709062dda00b007bd61492097mr14456926eji.185.1669685134867; Mon, 28 Nov 2022 17:25:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669685134; cv=none; d=google.com; s=arc-20160816; b=w5yqEuNa5R1m772uoO0l3x3uLsYJxpnxQ7kbJC32b9iyAr55G6SnC9k3ImfH7n1UX6 7o/tBUfSEHwiCQ5NOcZnfS5LmeZ4POtUbucmIEP+YQa6ASfoTQm+qO11B56ysWJ+x0h5 UXzjSNH7+mYXlfM8L58atw/GuMSX7sIFbpnr3xjuFMKHwUkfHmf/CUSBvHbgXdPVybM5 3gTQuf69phqrn3ok01X8+RZ+sUWp8/YiRGdh2h7MJ5Kbc/vkd65znsN+mBtJA964bBD5 gQDf9GywLNZk+WYhot3uP4ZY1MUy/zXf4zAFxyPP7oc1wVqyT3FICzztcR5PE/yZzb70 gerA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:feedback-id :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:dmarc-filter:delivered-to; bh=+4tBkeiUucw8I7GhYUU9JTj6FwktoMJFwTVdB3YpAGc=; b=C1J0biL0NlOfy7U9Eg4eJInUVM7WMNns641otKRsEhjsTjyz8rC62ttUmggLBi8tdu 3Pmijg0j2rAFJv5tIqDlD3/hH1lqs+VOltb5iABZ/Ug3AukwPR/MKHM7wlK6pz/U/NNL f2unY+MyJNx/uVcs3ksmPy731orPiEXibQ5t84WhoTL9RZ6iHD1EF59OJNAjFRuaSKoh +ok0Lwi3idV8SdRdwAx3oEOvYxD272nmK8UW2ztji9Z+E2z+1RvCqIcCGP+gFU7LSlUT fuAMuaMlPWZvT2czOmjPkOsjaFidsCVX78SjmUrI7uTeXZ9TKuOP2sps5VTCM+yaDuVb povQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id js6-20020a17090797c600b007ada2ec1a28si12550072ejc.165.2022.11.28.17.25.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Nov 2022 17:25:34 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6E22E38451B4 for ; Tue, 29 Nov 2022 01:24:05 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast3.qq.com (smtpbguseast3.qq.com [54.243.244.52]) by sourceware.org (Postfix) with ESMTPS id 6A86538432C5 for ; Tue, 29 Nov 2022 01:22:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 6A86538432C5 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp82t1669684924tls01ip2 Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 29 Nov 2022 09:22:03 +0800 (CST) X-QQ-SSF: 01400000000000D0K000000A0000000 X-QQ-FEAT: XBN7tc9DADKAUTwclrnRBiFh6ayzoffnAJrTHYmDFMS6B0ACkBp9fhdFGdczw 23NZZzGBhbMpJZEmlNLQgm0KcSyKQ99O00vJZ5JrwyDu8DhoFWSt/gPJg4kmHvkzG78Cbwk LkcAzUngDr9GZ7ZUtCg1OUq8Epcg3uzPwFZkOvg3gYJjRoeWk3oO5GmuYW31NkJpuL5ffU1 96VBtKB3YsKCJxtanx85BirQehw3489aA4I34u+71FLNiLBssKo0amL2yCGNb+jica4QJRd I8wlfCc0o2W9aw+jhAoNEVHU0nlUFMYZLaAnl33TqbYjHWpt9VVYFfRN0VgS38bB2oJFlfu JYaCjOBKmsGyp5bdsOkOVxYrq0LHAYElJjEdBhhnPATMOAaZ9CJ8QFo8uAE8g== X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Remove tail && mask policy operand for vmclr, vmset, vmld, vmst Date: Tue, 29 Nov 2022 09:22:01 +0800 Message-Id: <20221129012201.76355-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750750005340901043?= X-GMAIL-MSGID: =?utf-8?q?1750791760196288532?= From: Ju-Zhe Zhong Sorry for resend this patch, I found I miss commit a file. 1. vector.md: remove tail && mask policy operand for mask mode operations since we don't need them according to RVV ISA. 2. riscv-v.cc: adapt emit_pred_op for mask mode predicated mov since all RVV modes including vector integer mode && vector float mode && vector bool mode are all use emit_pred_op function. For vector integer mode && vector float mode, we have instruction like vle.v/vse.v that we need tail && mask policy. However, for vector bool mode, the instruction is vlm/vsm that we don't need tail && mask policy. So we add a condition here to add tail && mask policy operand during expand if it is not a vector bool modes. This patch is to cleanup the code and make it be consistent with RVV ISA. gcc/ChangeLog: * config/riscv/riscv-v.cc (emit_pred_op): Adapt for mask mode. * config/riscv/vector.md: Remove Tail && make policy operand for mask mode mov. --- gcc/config/riscv/riscv-v.cc | 3 ++- gcc/config/riscv/vector.md | 2 -- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index d54795694f1..4992ff2470c 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -136,7 +136,8 @@ emit_pred_op (unsigned icode, rtx dest, rtx src, machine_mode mask_mode) rtx vlmax = emit_vlmax_vsetvl (mode); e.add_input_operand (vlmax, Pmode); - e.add_policy_operand (TAIL_AGNOSTIC, MASK_AGNOSTIC); + if (GET_MODE_CLASS (mode) != MODE_VECTOR_BOOL) + e.add_policy_operand (TAIL_AGNOSTIC, MASK_AGNOSTIC); e.expand ((enum insn_code) icode, MEM_P (dest) || MEM_P (src)); } diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 3bb87232d3f..38da2f7f095 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -593,8 +593,6 @@ (unspec:VB [(match_operand:VB 1 "vector_mask_operand" "Wc1, Wc1, Wc1, Wc1, Wc1") (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK") - (match_operand 5 "const_int_operand" " i, i, i, i, i") - (match_operand 6 "const_int_operand" " i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operand:VB 3 "vector_move_operand" " m, vr, vr, Wc0, Wc1")