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([172.25.112.68]) by fmsmga008.fm.intel.com with ESMTP; 28 Nov 2022 09:04:19 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com, jgross@suse.com Subject: [PATCH v5 1/5] x86/cpufeature: add the cpu feature bit for LKGS Date: Mon, 28 Nov 2022 08:40:24 -0800 Message-Id: <20221128164028.4570-2-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221128164028.4570-1-xin3.li@intel.com> References: <20221128164028.4570-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750760768086288151?= X-GMAIL-MSGID: =?utf-8?q?1750760768086288151?= From: "H. Peter Anvin (Intel)" Add the CPU feature bit for LKGS (Load "Kernel" GS). LKGS instruction is introduced with Intel FRED (flexible return and event delivery) specificaton https://cdrdv2.intel.com/v1/dl/getContent/678938. LKGS behaves like the MOV to GS instruction except that it loads the base address into the IA32_KERNEL_GS_BASE MSR instead of the GS segment’s descriptor cache, which is exactly what Linux kernel does to load a user level GS base. Thus, with LKGS, there is no need to SWAPGS away from the kernel GS base. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- Change since V2: * add "" not to show "lkgs" in /proc/cpuinfo (Chang S. Bae). --- arch/x86/include/asm/cpufeatures.h | 1 + tools/arch/x86/include/asm/cpufeatures.h | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index b2da7cb64b31..29f53b31056e 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -311,6 +311,7 @@ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ +#define X86_FEATURE_LKGS (12*32+ 18) /* "" Load "kernel" (userspace) gs */ /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h index b71f4f2ecdd5..3dc1a48c2796 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -308,6 +308,7 @@ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ +#define X86_FEATURE_LKGS (12*32+ 18) /* "" Load "kernel" (userspace) gs */ /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ From patchwork Mon Nov 28 16:40:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 26879 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5819931wrr; Mon, 28 Nov 2022 09:13:11 -0800 (PST) X-Google-Smtp-Source: AA0mqf5/H6AFyc8WyDPMpxW4lTLsuGkeOPmq++IG5A9CDbNkSKEHyf7yHU5qM4/2Mh4+7v8gAz5v X-Received: by 2002:a17:906:9250:b0:7bb:7520:c527 with SMTP id c16-20020a170906925000b007bb7520c527mr19224768ejx.347.1669655591700; Mon, 28 Nov 2022 09:13:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669655591; cv=none; d=google.com; s=arc-20160816; b=hl2D+BC3ssTeF5aPAJJ5vI3mRpTKchOwsw8ixrTUuKt/K16IgaFKl8ufXzGq4iZP4p ZUmS358Qs0Dg3D5AseVEYMlHAsdj93SEKsHKd4UQPjYcUrA6RPeR4vUOQSM43ebs6fyW YWV9xDpd5wbaJaocCNHstFENk1bJm6gE0515Wg7GKRlCdbXWGxfMf3WLDcUVJrn51o8O cBBPRQb3nTs40rjnEOE1SEC7xofl6JwvlZfZJWpIyG0orqNLmmfcFuDJas6c2uN4IfLf b+Zns7Nbke2TMjeQfGCp55PcGk2L7BXAedBusCp/1oeMaUI9t7t4b5mNFNROUBS6nNTb dlxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+3L/zBhMiW903xYBCmWze24Rs8tywihmXNz1C+Zm5Es=; b=GZCfkwEXIAz8WD9DNnddIe0k8HAK0ib+PANVRHjSfaWwdWfnmeIVwWfINI5sh9d5Kn o0fB3xMWfj90aGIBkCgY5l63AoOIh/DAVOdF8FgZQyVBTfUw0gnaBvZbIWUHAx5xodmu zrrrjscd3GumDNdEl+9ZFOpQvBPKXJ9+QDF8cpEmV2MxrUnvQ1q6QlO8ePJ/WfOoNjin mw8Z/k1KotJON7BcoOl/V25ZjN8bM9aaWupUZ9UqOAagx6QT6GuPonzlmJLrxHhLTQ3p PWyjGZBvr8Ra0RzoBa/rmlVfVrzt+lDrpQ9dLvKPNxr8jeA6uk5f8cmEmHVrfdYLufic Ytag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=M3nYsWdF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by fmsmga008.fm.intel.com with ESMTP; 28 Nov 2022 09:04:20 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com, jgross@suse.com Subject: [PATCH v5 2/5] x86/opcode: add the LKGS instruction to x86-opcode-map Date: Mon, 28 Nov 2022 08:40:25 -0800 Message-Id: <20221128164028.4570-3-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221128164028.4570-1-xin3.li@intel.com> References: <20221128164028.4570-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750760781809703833?= X-GMAIL-MSGID: =?utf-8?q?1750760781809703833?= From: "H. Peter Anvin (Intel)" Add the instruction opcode used by LKGS. Opcode number is per public FRED draft spec v3.0 https://cdrdv2.intel.com/v1/dl/getContent/678938. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/lib/x86-opcode-map.txt | 1 + tools/arch/x86/lib/x86-opcode-map.txt | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt index d12d1358f96d..5168ee0360b2 100644 --- a/arch/x86/lib/x86-opcode-map.txt +++ b/arch/x86/lib/x86-opcode-map.txt @@ -1047,6 +1047,7 @@ GrpTable: Grp6 3: LTR Ew 4: VERR Ew 5: VERW Ew +6: LKGS Ew (F2) EndTable GrpTable: Grp7 diff --git a/tools/arch/x86/lib/x86-opcode-map.txt b/tools/arch/x86/lib/x86-opcode-map.txt index d12d1358f96d..5168ee0360b2 100644 --- a/tools/arch/x86/lib/x86-opcode-map.txt +++ b/tools/arch/x86/lib/x86-opcode-map.txt @@ -1047,6 +1047,7 @@ GrpTable: Grp6 3: LTR Ew 4: VERR Ew 5: VERW Ew +6: LKGS Ew (F2) EndTable GrpTable: Grp7 From patchwork Mon Nov 28 16:40:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 26881 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5820201wrr; Mon, 28 Nov 2022 09:13:32 -0800 (PST) X-Google-Smtp-Source: AA0mqf6cVrPBCHpljHyj6AMUX9LGr5o998XKxl2BOAwafmaUFZaa7FUuF5aZYNGFg//aFwyf5LGE X-Received: by 2002:a17:906:6093:b0:78d:b37c:83d9 with SMTP id t19-20020a170906609300b0078db37c83d9mr28479339ejj.637.1669655611985; Mon, 28 Nov 2022 09:13:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669655611; cv=none; d=google.com; s=arc-20160816; b=vvPbdWRxEy9VnNZpnI07zRIUww5GBRiGZpJs+BP2Or42R+l+NGS0DdXkoOUHbrm77H V6rmcjETvTPqWO1R+uc/S1Z2KRX9mN4ZxALbZuhVjIHuiu/8kN+rpKdvsZSyR0hZnxdh Cc+4rbhWQ9auOQsWSnYdT9r6R8DAgkCwqGnAypVkFPF4fQd1/qE4ffmVh2dmWD13TfAb jx5/PPZBwnHpvAh/li8X74yzaT3kPXFSceJJzycWjGjRUs6X5ZxmGwIzGxTxnRNf1IIX 6MZC/BcCOY96C87E7x9qbtWzsN8PpTT9uYMMX2Qbcdt2qM6SorCY5hHAxO1XruaSGpDc 464A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Y0zyNmAYzT3ri+4nefmoVJ0xInwrkHd8fCwz/8mxmhE=; b=u8H1x528Af8+mg18IWHhIrJ2uUfgGcO+roJ+ojgDWKzWucSL+dFmdv8FFfDbS1/EwR NESoycR1cnZH88ULInrM1VRhE/6ReqeTy23KwJC3KGwEpGF7obT2lVtw174591e+NiZv wBKraS0oJM79J3BloYH2TDJ4OEcOm6cEJxFz/a5hOokNOBYl3WOtp7fTZ9XiFGLipGUs hslWlKLsIFKKIzFYYkk+JUsRKh+QViiDNLKb7rbuNxgPKbjxdx0fHJ+eCsk55Ubhcx3V K4Lzz1Y2d+855iu+cbTYWTyMfJ9l7iy5EX8sJsmX3GtaH4HiI2UEKYMIQFlifjaOCYzE r07A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=D5TpavpQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by fmsmga008.fm.intel.com with ESMTP; 28 Nov 2022 09:04:20 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com, jgross@suse.com Subject: [PATCH v5 3/5] x86/gsseg: make asm_load_gs_index() take an u16 Date: Mon, 28 Nov 2022 08:40:26 -0800 Message-Id: <20221128164028.4570-4-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221128164028.4570-1-xin3.li@intel.com> References: <20221128164028.4570-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750760802912621869?= X-GMAIL-MSGID: =?utf-8?q?1750760802912621869?= From: "H. Peter Anvin (Intel)" Let gcc know that only the low 16 bits of load_gs_index() argument actually matter. It might allow it to create slightly better code. However, do not propagate this into the prototypes of functions that end up being paravirtualized, to avoid unnecessary changes. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/entry/entry_64.S | 2 +- arch/x86/include/asm/special_insns.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index 9953d966d124..e0c48998d2fb 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -779,7 +779,7 @@ _ASM_NOKPROBE(common_interrupt_return) /* * Reload gs selector with exception handling - * edi: new selector + * di: new selector * * Is in entry.text as it shouldn't be instrumented. */ diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h index 35f709f619fb..a71d0e8d4684 100644 --- a/arch/x86/include/asm/special_insns.h +++ b/arch/x86/include/asm/special_insns.h @@ -120,7 +120,7 @@ static inline void native_wbinvd(void) asm volatile("wbinvd": : :"memory"); } -extern asmlinkage void asm_load_gs_index(unsigned int selector); +extern asmlinkage void asm_load_gs_index(u16 selector); static inline void native_load_gs_index(unsigned int selector) { From patchwork Mon Nov 28 16:40:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 26880 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5819961wrr; Mon, 28 Nov 2022 09:13:14 -0800 (PST) X-Google-Smtp-Source: AA0mqf76b0boXNnIZLPBjO/cf+oV1O17CyodBSphUtJyJaqJj2p2HZcJErGjUR1/otlZ+dEZjmRN X-Received: by 2002:a17:906:1498:b0:73f:40a9:62ff with SMTP id x24-20020a170906149800b0073f40a962ffmr45170669ejc.678.1669655594164; Mon, 28 Nov 2022 09:13:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669655594; cv=none; d=google.com; s=arc-20160816; b=OpV4JBMuOn8PI3JtpxUo94ZATQBX/fkJTbzj+HGiugWEs17uZO2TO/w0kzWgtvAxFm EJkJX9uaF0aNRdm4/9b4tX4G5oaJevGiEhJzIEvjPOx43Za+05dJ26jzO9nvjpDBeTpd Hw5MkUBFHuEsgyFzfwnRpuApDGQbdlmR/CcAUW3GZs69P4Aza0QELf54kKeM1qBF5Asi d0eXMcCgLQT3oMDRKw9jzvntOBLgXb/cGK+APwnT+NYGp3VW7OnGuRINMGM3Esvumw4x QYrSUQadh9yfKVhTZainWFFNv7ptr83wI1l0tEFbImSFc6jSxQwitXGmwj2Zmxxd3V+Y 2JAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=B1/bKgLO1zn8qG0TcKZhJiT7VIXXp1YNTY7nenPzEwk=; b=QorbQXgpTClbkA/tQp/bijMTwOL3pkzvegXRCql50r8pNkY6X5LzfFpUruZp8rSxMU nLeuKDN6eWmVDSrZ1KQ3ACkZK6kIw9ab3NEaJ1bbAshp4tZ7Hk29uCOWlrHcTRQ6+96x cBrMLo7vUqSRqrTzTfS3EBfpzTNfmGsZeEYnSR+A36GmkN78u8xYPmSxFqkC89TmpoYi XZEZV8nLcgt+PxeT0JxZYg1k/cTvuH4fumxjnLfOTgbps9su4wAFS6MYwWW3ECli+3Ev 83XbsTKbqC9ZTjAI/V1FR1j8NfZR72olMyrBBsNlbRobylJfqsdHmyfaSzWb6+wWBMbG Ri1A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=nGiEmV07; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by fmsmga008.fm.intel.com with ESMTP; 28 Nov 2022 09:04:20 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com, jgross@suse.com Subject: [PATCH v5 4/5] x86/gsseg: move load_gs_index() to its own new header file Date: Mon, 28 Nov 2022 08:40:27 -0800 Message-Id: <20221128164028.4570-5-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221128164028.4570-1-xin3.li@intel.com> References: <20221128164028.4570-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750760784628690038?= X-GMAIL-MSGID: =?utf-8?q?1750760784628690038?= From: "H. Peter Anvin (Intel)" GS is a special segment on x86_64, move load_gs_index() to its own new header file. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/ia32/ia32_signal.c | 1 + arch/x86/include/asm/gsseg.h | 41 ++++++++++++++++++++++++++++ arch/x86/include/asm/mmu_context.h | 1 + arch/x86/include/asm/special_insns.h | 21 -------------- arch/x86/kernel/paravirt.c | 1 + arch/x86/kernel/tls.c | 1 + 6 files changed, 45 insertions(+), 21 deletions(-) create mode 100644 arch/x86/include/asm/gsseg.h diff --git a/arch/x86/ia32/ia32_signal.c b/arch/x86/ia32/ia32_signal.c index c9c3859322fa..14c739303099 100644 --- a/arch/x86/ia32/ia32_signal.c +++ b/arch/x86/ia32/ia32_signal.c @@ -34,6 +34,7 @@ #include #include #include +#include static inline void reload_segments(struct sigcontext_32 *sc) { diff --git a/arch/x86/include/asm/gsseg.h b/arch/x86/include/asm/gsseg.h new file mode 100644 index 000000000000..d15577c39e8d --- /dev/null +++ b/arch/x86/include/asm/gsseg.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASM_X86_GSSEG_H +#define _ASM_X86_GSSEG_H + +#include + +#include +#include +#include +#include +#include + +#ifdef CONFIG_X86_64 + +extern asmlinkage void asm_load_gs_index(u16 selector); + +static inline void native_load_gs_index(unsigned int selector) +{ + unsigned long flags; + + local_irq_save(flags); + asm_load_gs_index(selector); + local_irq_restore(flags); +} + +#endif /* CONFIG_X86_64 */ + +#ifndef CONFIG_PARAVIRT_XXL + +static inline void load_gs_index(unsigned int selector) +{ +#ifdef CONFIG_X86_64 + native_load_gs_index(selector); +#else + loadsegment(gs, selector); +#endif +} + +#endif /* CONFIG_PARAVIRT_XXL */ + +#endif /* _ASM_X86_GSSEG_H */ diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h index b8d40ddeab00..e01aa74a6de7 100644 --- a/arch/x86/include/asm/mmu_context.h +++ b/arch/x86/include/asm/mmu_context.h @@ -12,6 +12,7 @@ #include #include #include +#include extern atomic64_t last_mm_ctx_id; diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h index a71d0e8d4684..cfd9499b617c 100644 --- a/arch/x86/include/asm/special_insns.h +++ b/arch/x86/include/asm/special_insns.h @@ -120,17 +120,6 @@ static inline void native_wbinvd(void) asm volatile("wbinvd": : :"memory"); } -extern asmlinkage void asm_load_gs_index(u16 selector); - -static inline void native_load_gs_index(unsigned int selector) -{ - unsigned long flags; - - local_irq_save(flags); - asm_load_gs_index(selector); - local_irq_restore(flags); -} - static inline unsigned long __read_cr4(void) { return native_read_cr4(); @@ -184,16 +173,6 @@ static inline void wbinvd(void) native_wbinvd(); } - -static inline void load_gs_index(unsigned int selector) -{ -#ifdef CONFIG_X86_64 - native_load_gs_index(selector); -#else - loadsegment(gs, selector); -#endif -} - #endif /* CONFIG_PARAVIRT_XXL */ static inline void clflush(volatile void *__p) diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index 7ca2d46c08cc..00f6a92551d2 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -32,6 +32,7 @@ #include #include #include +#include /* * nop stub, which must not clobber anything *including the stack* to diff --git a/arch/x86/kernel/tls.c b/arch/x86/kernel/tls.c index 3c883e064242..3ffbab0081f4 100644 --- a/arch/x86/kernel/tls.c +++ b/arch/x86/kernel/tls.c @@ -12,6 +12,7 @@ #include #include #include +#include #include "tls.h" From patchwork Mon Nov 28 16:40:28 2022 Content-Type: text/plain; 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([172.25.112.68]) by fmsmga008.fm.intel.com with ESMTP; 28 Nov 2022 09:04:20 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com, jgross@suse.com Subject: [PATCH v5 5/5] x86/gsseg: use the LKGS instruction if available for load_gs_index() Date: Mon, 28 Nov 2022 08:40:28 -0800 Message-Id: <20221128164028.4570-6-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221128164028.4570-1-xin3.li@intel.com> References: <20221128164028.4570-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750760826775106200?= X-GMAIL-MSGID: =?utf-8?q?1750760826775106200?= From: "H. Peter Anvin (Intel)" The LKGS instruction atomically loads a segment descriptor into the %gs descriptor registers, *except* that %gs.base is unchanged, and the base is instead loaded into MSR_IA32_KERNEL_GS_BASE, which is exactly what we want this function to do. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Peter Zijlstra (Intel) Signed-off-by: Brian Gerst Signed-off-by: Juergen Gross Signed-off-by: Xin Li --- Changes since v4: * Clear the LKGS feature from Xen PV guests (Juergen Gross). Changes since v3: * We want less ASM not more, thus keep local_irq_save/restore() inside native_load_gs_index() (Thomas Gleixner). * For paravirt enabled kernels, initialize pv_ops.cpu.load_gs_index to native_lkgs (Thomas Gleixner). Changes since v2: * Mark DI as input and output (+D) as in V1, since the exception handler modifies it (Brian Gerst). Changes since v1: * Use EX_TYPE_ZERO_REG instead of fixup code in the obsolete .fixup code section (Peter Zijlstra). * Add a comment that states the LKGS_DI macro will be repalced with "lkgs %di" once the binutils support the LKGS instruction (Peter Zijlstra). --- arch/x86/include/asm/gsseg.h | 33 +++++++++++++++++++++++++++++---- arch/x86/kernel/cpu/common.c | 1 + arch/x86/xen/enlighten_pv.c | 1 + 3 files changed, 31 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/gsseg.h b/arch/x86/include/asm/gsseg.h index d15577c39e8d..ab6a595cea70 100644 --- a/arch/x86/include/asm/gsseg.h +++ b/arch/x86/include/asm/gsseg.h @@ -14,17 +14,42 @@ extern asmlinkage void asm_load_gs_index(u16 selector); +/* Replace with "lkgs %di" once binutils support LKGS instruction */ +#define LKGS_DI _ASM_BYTES(0xf2,0x0f,0x00,0xf7) + +static inline void native_lkgs(unsigned int selector) +{ + u16 sel = selector; + asm_inline volatile("1: " LKGS_DI + _ASM_EXTABLE_TYPE_REG(1b, 1b, EX_TYPE_ZERO_REG, %k[sel]) + : [sel] "+D" (sel)); +} + static inline void native_load_gs_index(unsigned int selector) { - unsigned long flags; + if (cpu_feature_enabled(X86_FEATURE_LKGS)) { + native_lkgs(selector); + } else { + unsigned long flags; - local_irq_save(flags); - asm_load_gs_index(selector); - local_irq_restore(flags); + local_irq_save(flags); + asm_load_gs_index(selector); + local_irq_restore(flags); + } } #endif /* CONFIG_X86_64 */ +static inline void __init lkgs_init(void) +{ +#ifdef CONFIG_PARAVIRT_XXL +#ifdef CONFIG_X86_64 + if (cpu_feature_enabled(X86_FEATURE_LKGS)) + pv_ops.cpu.load_gs_index = native_lkgs; +#endif +#endif +} + #ifndef CONFIG_PARAVIRT_XXL static inline void load_gs_index(unsigned int selector) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 3e508f239098..d6eb4f60b47d 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1939,6 +1939,7 @@ void __init identify_boot_cpu(void) setup_cr_pinning(); tsx_init(); + lkgs_init(); } void identify_secondary_cpu(struct cpuinfo_x86 *c) diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index 038da45f057a..c48a9061160e 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -276,6 +276,7 @@ static void __init xen_init_capabilities(void) setup_clear_cpu_cap(X86_FEATURE_ACC); setup_clear_cpu_cap(X86_FEATURE_X2APIC); setup_clear_cpu_cap(X86_FEATURE_SME); + setup_clear_cpu_cap(X86_FEATURE_LKGS); /* * Xen PV would need some work to support PCID: CR3 handling as well