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[2620:137:e000::1:20]) by mx.google.com with ESMTP id s18-20020a056a0008d200b00573f637f57asi12024492pfu.238.2022.11.28.06.45.37; Mon, 28 Nov 2022 06:45:51 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=m11KIfuM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232546AbiK1OjJ (ORCPT + 99 others); Mon, 28 Nov 2022 09:39:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59750 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232585AbiK1Oiz (ORCPT ); Mon, 28 Nov 2022 09:38:55 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 44F1422BC6; Mon, 28 Nov 2022 06:38:43 -0800 (PST) X-UUID: 092a6639ebeb4525b2ec9bba80470fb0-20221128 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=fXE3ixxnwn9kbAy+LhtuatbP6zj0qagtky4+i+jidZo=; b=m11KIfuMnfsG9rLFA7vXoaOlZLuBIU4w2WfvRAgxYD3Bat1WQSHZkmB4hQVdbL3+af9dgl/i0WwS0ZPcYXDV91HTrXYNgAsr1GcEeO1IIwcqe0Jwo2JnFBYalaaA/eIwLRAq618lUzc7riReDjH0oIJOKrHI0YV1zR8buNZAYhY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:a7d4b020-c3eb-4032-b172-57ef6f027f47,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:90 X-CID-INFO: VERSION:1.1.14,REQID:a7d4b020-c3eb-4032-b172-57ef6f027f47,IP:0,URL :0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:90 X-CID-META: VersionHash:dcaaed0,CLOUDID:2aca7117-81a9-4b5f-95c6-b6b92590fd73,B ulkID:22112822383903MH7I3W,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 092a6639ebeb4525b2ec9bba80470fb0-20221128 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1094259597; Mon, 28 Nov 2022 22:38:38 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 28 Nov 2022 22:38:37 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 28 Nov 2022 22:38:37 +0800 From: Allen-KH Cheng To: Mauro Carvalho Chehab , Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , , , Allen-KH Cheng Subject: [PATCH v5 1/3] media: dt-bindings: media: mediatek: Rename child node names for decoder Date: Mon, 28 Nov 2022 22:38:30 +0800 Message-ID: <20221128143832.25584-2-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221128143832.25584-1-allen-kh.cheng@mediatek.com> References: <20221128143832.25584-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750751511950719035?= X-GMAIL-MSGID: =?utf-8?q?1750751511950719035?= In order to make the names of the child nodes more generic, we rename "vcodec-lat" and "vcodec-core" to "video-codec" for decoder in patternProperties and example. Signed-off-by: Allen-KH Cheng Reviewed-by: Krzysztof Kozlowski --- .../media/mediatek,vcodec-subdev-decoder.yaml | 60 ++----------------- 1 file changed, 4 insertions(+), 56 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml index c4f20acdc1f8..695402041e04 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml @@ -91,12 +91,13 @@ properties: # Required child node: patternProperties: - '^vcodec-lat@[0-9a-f]+$': + '^video-codec@[0-9a-f]+$': type: object properties: compatible: enum: + - mediatek,mtk-vcodec-core - mediatek,mtk-vcodec-lat - mediatek,mtk-vcodec-lat-soc @@ -145,59 +146,6 @@ patternProperties: additionalProperties: false - '^vcodec-core@[0-9a-f]+$': - type: object - - properties: - compatible: - const: mediatek,mtk-vcodec-core - - reg: - maxItems: 1 - - interrupts: - maxItems: 1 - - iommus: - minItems: 1 - maxItems: 32 - description: | - List of the hardware port in respective IOMMU block for current Socs. - Refer to bindings/iommu/mediatek,iommu.yaml. - - clocks: - maxItems: 5 - - clock-names: - items: - - const: sel - - const: soc-vdec - - const: soc-lat - - const: vdec - - const: top - - assigned-clocks: - maxItems: 1 - - assigned-clock-parents: - maxItems: 1 - - power-domains: - maxItems: 1 - - required: - - compatible - - reg - - interrupts - - iommus - - clocks - - clock-names - - assigned-clocks - - assigned-clock-parents - - power-domains - - additionalProperties: false - required: - compatible - reg @@ -241,7 +189,7 @@ examples: #size-cells = <2>; ranges = <0 0 0 0x16000000 0 0x40000>; reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */ - vcodec-lat@10000 { + video-codec@10000 { compatible = "mediatek,mtk-vcodec-lat"; reg = <0 0x10000 0 0x800>; interrupts = ; @@ -264,7 +212,7 @@ examples: power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; }; - vcodec-core@25000 { + video-codec@25000 { compatible = "mediatek,mtk-vcodec-core"; reg = <0 0x25000 0 0x1000>; interrupts = ; From patchwork Mon Nov 28 14:38:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 26807 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5720248wrr; Mon, 28 Nov 2022 06:45:57 -0800 (PST) X-Google-Smtp-Source: AA0mqf5x2ErznmWE/fqpxgryHfCA0bfEmosqxf+DDAFbGN+GTImRgKbXY3eV5sTFqej+Mkb1epgr X-Received: by 2002:a17:902:784c:b0:189:65c5:4507 with SMTP id e12-20020a170902784c00b0018965c54507mr16830898pln.172.1669646756882; Mon, 28 Nov 2022 06:45:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669646756; cv=none; d=google.com; s=arc-20160816; b=LAFtZohedIWdfrvgndYzqjSJyuZ3LDYthKVAYoWzHbXezd3+taeGIBsIkYdODLmoW2 C9bnBHnOSz5J5wTDiTTddoGi2EgggfGyUnFrp2RG7ygQprFls90ZSpux0yHpa64M3tQp iNBGQBqcvmSrUh2MrvZJlk8fiAdEXvUhLZceV4HwuvKjNOmgLQfMC9sltsAjZOKdch82 ITq8tLRCiIYOUbQ+ZLjemWPD+as21BfVlKYGmrUbrSScBNkG/vweB5K8guppIooTUlpt ikhwjNnz0W2avDhFkUJWf1M2GNwNUzzb1GAuaxb4XtE7kwuFlQrcEgSoeZ5K+3//95h+ 6Iug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=WP0Ri4l4ARLO/MzGAoD+zVZWP+9658CD4ZHeqjUyq/I=; b=u6g99eNdtlH78DR58/5y4wVX++lmjcOq0kKyjvKtOsdLPYCFLiSCFJDOJaQyzUw6uN 70EO9AhtnUrriEQO1JTAMMJlVMBM/bOAcmZV+u9ifdHlFd3NdL8fusUEWNE5ceElZg+6 DPDQmHiIJN0wXeqPDDiA79z7DJ3zBb8RSgHO6h/zaAZalkpkb60hUd59W+xdIfJX4zMz 6iei0giWO9qVk98e6jIka2vfyff6l/vPCrMvEQlHR1Y9Ed6LcrHVTLqi1cmcYzdwqtHa FNGA7aglq5NfTOmeA/0OO7etAm7hvwyISgyZ+QOOAkVx7wQyWAOJ8q9vK18GEaMP4ZEs 47yw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=r5Kp5DgM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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We remove the dma-ranges property and fix the example in mediatek,vcodec-subdev-decoder.yaml Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring Reviewed-by: Nícolas F. R. A. Prado --- .../bindings/media/mediatek,vcodec-subdev-decoder.yaml | 7 ------- 1 file changed, 7 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml index 695402041e04..7c5b4a91c59b 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml @@ -76,11 +76,6 @@ properties: The node of system control processor (SCP), using the remoteproc & rpmsg framework. - dma-ranges: - maxItems: 1 - description: | - Describes the physical address space of IOMMU maps to memory. - "#address-cells": const: 2 @@ -151,7 +146,6 @@ required: - reg - iommus - mediatek,scp - - dma-ranges - ranges if: @@ -184,7 +178,6 @@ examples: compatible = "mediatek,mt8192-vcodec-dec"; mediatek,scp = <&scp>; iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; - dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; #address-cells = <2>; #size-cells = <2>; ranges = <0 0 0 0x16000000 0 0x40000>; From patchwork Mon Nov 28 14:38:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 26808 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5721062wrr; Mon, 28 Nov 2022 06:47:11 -0800 (PST) X-Google-Smtp-Source: AA0mqf6gGEfkiaiwFGnpOOQ5RF4eIrR6XL1QLBn1Q0x6XOilM5aihSkYu1DVdiZ5AkuxazUwnH6l X-Received: by 2002:a50:ee87:0:b0:469:a893:534d with SMTP id f7-20020a50ee87000000b00469a893534dmr34845966edr.213.1669646831155; Mon, 28 Nov 2022 06:47:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669646831; cv=none; d=google.com; s=arc-20160816; b=yiNZ6CTmprNa/0Kn6Wgo2Rvrt3wVEwRUeGZbHTM98PPp3fSyTHB9ETQJE+1y+xNFwS OoBSLMwXT3Jw3pOHN8VM0dKEnckkoPZVVg1fdx6u0X+n/dai3eMNLfyGmBA/6Ax+/jTV PBkJCyr7qS7oXm9v4xpkAoVBJGfNenkxCrWQ0AfdBbwamNZJ16WrLx94rcm4exelyuTN 0jt8WsJ0GWAsQpqfO8pWqaKLtLCdhNZIljl8nAVxyWdPwoih7YqAjNZ7QfkCL1MJrFl4 pL+HwilaD1IqOo3c9mvNbwoiJuDw5av/BbSVfVC4WUI1MwOnre1jU/bJXe1OW4gdX22T Qb7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=gz1uPBnoeOPXBBVk8DqZFdSk72POcdwsgdcC8tIsRVE=; b=kep5r2OF0lMrmratFOoCB+/Pke8I4FXf+uiRntnfpNsn43rbV5zyuXSxFViH2sssBi 1770mklJ0qzHHgcJntHcfH0xk2bUDoCMKhe79L4emAmIFBw9bZV72EaBwVr4nFyLWuQN dSnedWZVYyv5R3lxcBJ246w4PwDlF02pxEl8Y+hKN3cC6G5Swxb8/dROTba5oZ8ymrnB je3/kBn3YURIybyy6Jz6lAZxB2yqJWksl5NZ79PPhVF2bKUGRztTgjVrN49THsJ0bmmQ dLAR/2lFYenfLS3u6DRc2eOWVeXiUu6bOnCucFtU+IfsSc0jM7OXz2fvR6sKbA/OCG6I wycw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=E06ye64F; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id e4-20020a17090658c400b007877b1c7f27si10441469ejs.829.2022.11.28.06.46.47; Mon, 28 Nov 2022 06:47:11 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=E06ye64F; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232553AbiK1OjN (ORCPT + 99 others); Mon, 28 Nov 2022 09:39:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59680 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232146AbiK1Oi4 (ORCPT ); Mon, 28 Nov 2022 09:38:56 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 319281ADAC; Mon, 28 Nov 2022 06:38:47 -0800 (PST) X-UUID: f624dee2f57d483fba71e55eaa58a6ac-20221128 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=gz1uPBnoeOPXBBVk8DqZFdSk72POcdwsgdcC8tIsRVE=; b=E06ye64FMyEsEcf6PhVJS9Zp+EJ5meVyh6mGjQqyagulF6s1xKafP5LaDOkixAHbTb4UDilosMeCLi5agvPZe9AeLP0BdrLdrF/zYu/TIKy2AMZBuVN0A4i9buHEHq0eGEaDiN93FPSFtgjAGrTqDtT1CekZzh4WKOkXQDMT3BI=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:b969d06a-4a70-4373-ace7-2833a1ba70ae,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:90 X-CID-INFO: VERSION:1.1.14,REQID:b969d06a-4a70-4373-ace7-2833a1ba70ae,IP:0,URL :0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:90 X-CID-META: VersionHash:dcaaed0,CLOUDID:54ca7117-81a9-4b5f-95c6-b6b92590fd73,B ulkID:221128223842750CKH9S,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: f624dee2f57d483fba71e55eaa58a6ac-20221128 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1623862368; Mon, 28 Nov 2022 22:38:40 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Mon, 28 Nov 2022 22:38:39 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 28 Nov 2022 22:38:39 +0800 From: Allen-KH Cheng To: Mauro Carvalho Chehab , Matthias Brugger , Rob Herring , "Krzysztof Kozlowski" CC: , , , , , , , "Allen-KH Cheng" Subject: [PATCH v5 3/3] arm64: dts: mt8192: Add video-codec nodes Date: Mon, 28 Nov 2022 22:38:32 +0800 Message-ID: <20221128143832.25584-4-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221128143832.25584-1-allen-kh.cheng@mediatek.com> References: <20221128143832.25584-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750751595759435231?= X-GMAIL-MSGID: =?utf-8?q?1750751595759435231?= Add video-codec lat and core nodes for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado Tested-by: Nícolas F. R. A. Prado --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 59 ++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 424fc89cc6f7..eb5606204f22 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1452,6 +1452,65 @@ power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>; }; + vcodec_dec: video-codec@16000000 { + compatible = "mediatek,mt8192-vcodec-dec"; + reg = <0 0x16000000 0 0x1000>; + mediatek,scp = <&scp>; + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0x16000000 0 0x26000>; + + video-codec@10000 { + compatible = "mediatek,mtk-vcodec-lat"; + reg = <0x0 0x10000 0 0x800>; + interrupts = ; + iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>; + clocks = <&topckgen CLK_TOP_VDEC_SEL>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>, + <&topckgen CLK_TOP_MAINPLL_D4>; + clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; + }; + + video-codec@25000 { + compatible = "mediatek,mtk-vcodec-core"; + reg = <0 0x25000 0 0x1000>; + interrupts = ; + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>; + clocks = <&topckgen CLK_TOP_VDEC_SEL>, + <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_LAT>, + <&vdecsys CLK_VDEC_LARB1>, + <&topckgen CLK_TOP_MAINPLL_D4>; + clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; + }; + }; + larb5: larb@1600d000 { compatible = "mediatek,mt8192-smi-larb"; reg = <0 0x1600d000 0 0x1000>;