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[2620:137:e000::1:20]) by mx.google.com with ESMTP id y6-20020a655b46000000b00476f2af54f6si13126093pgr.47.2022.11.28.05.14.07; Mon, 28 Nov 2022 05:14:24 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="U5vi/ORG"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231332AbiK1NNq (ORCPT + 99 others); Mon, 28 Nov 2022 08:13:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231656AbiK1NNd (ORCPT ); Mon, 28 Nov 2022 08:13:33 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5727713D5E; Mon, 28 Nov 2022 05:13:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669641212; x=1701177212; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=bVqpVo1Q9MYSWk8Td5o+e8rn4ip/1+KMBJaJ/M8s+/Y=; b=U5vi/ORGokvMveSG0Qai9S11M08uOBRjdSHA8jXTTzLa/lPDNCuT7VvG 8B9LKyJjj3eCneQEjqVHlJNnyHMu2TGaEC8GGCNV5yTk4KHa++thsMMeb l5iCSupGVtJK7hfRJqg6g0EPqyy2ZI60zCZRjn8tZu62mSuhuZeRaBYbm fmNEFhICVDfE3Co+d5zeqdzCqk47bwvo8zk1Ff+ryj+1b69WPwhxi79Mk 34f1KPLeonfpCRCiQwyYtvxX8sENJcSDv2cDCNqvRfPErv12Jn7FFtfA3 X3ZuadxzzzstMV4a3hPI7mZIy5kQ03No4d1QBqNJ30D/3GNT/XVn9C+eo g==; X-IronPort-AV: E=McAfee;i="6500,9779,10544"; a="401117058" X-IronPort-AV: E=Sophos;i="5.96,200,1665471600"; d="scan'208";a="401117058" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Nov 2022 05:13:31 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10544"; a="749381321" X-IronPort-AV: E=Sophos;i="5.96,200,1665471600"; d="scan'208";a="749381321" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga002.fm.intel.com with ESMTP; 28 Nov 2022 05:13:31 -0800 From: Ricardo Neri To: "Peter Zijlstra (Intel)" , Juri Lelli , Vincent Guittot Cc: Ricardo Neri , "Ravi V. Shankar" , Ben Segall , Daniel Bristot de Oliveira , Dietmar Eggemann , Len Brown , Mel Gorman , "Rafael J. Wysocki" , Srinivas Pandruvada , Steven Rostedt , Tim Chen , Valentin Schneider , x86@kernel.org, "Joel Fernandes (Google)" , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Ricardo Neri , "Tim C . Chen" Subject: [PATCH v2 01/22] sched/task_struct: Introduce IPC classes of tasks Date: Mon, 28 Nov 2022 05:20:39 -0800 Message-Id: <20221128132100.30253-2-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> References: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750745758362341880?= X-GMAIL-MSGID: =?utf-8?q?1750745758362341880?= On hybrid processors, the architecture differences between the types of CPUs lead to different instructions-per-cycle (IPC) on each type of CPU. IPCs may differ further by the type of instructions. Instructions can be grouped into classes of similar IPCs. Hence, tasks can be classified into groups based on the type of instructions they execute. Add a new member task_struct::ipcc to associate a particular task to an IPC class that depends on the instructions it executes. The scheduler may use the IPC class of a task and data about the performance among CPUs of a given IPC class to improve throughput. It may, for instance, place certain classes of tasks on CPUs of higher performance. The methods to determine the classification of a task and its relative IPC score are specific to each CPU architecture. Cc: Ben Segall Cc: Daniel Bristot de Oliveira Cc: Dietmar Eggemann Cc: Joel Fernandes (Google) Cc: Len Brown Cc: Mel Gorman Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Steven Rostedt Cc: Tim C. Chen Cc: Valentin Schneider Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ricardo Neri --- Changes since v1: * Renamed task_struct::class as task::struct_ipcc. (Joel) * Use task_struct::ipcc = 0 for unclassified tasks. (PeterZ) * Renamed CONFIG_SCHED_TASK_CLASSES as CONFIG_IPC_CLASSES. (PeterZ, Joel) --- include/linux/sched.h | 10 ++++++++++ init/Kconfig | 12 ++++++++++++ 2 files changed, 22 insertions(+) diff --git a/include/linux/sched.h b/include/linux/sched.h index 68c07ae0d7ff..47ae3557ba07 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -127,6 +127,8 @@ struct task_group; __TASK_TRACED | EXIT_DEAD | EXIT_ZOMBIE | \ TASK_PARKED) +#define IPC_CLASS_UNCLASSIFIED 0 + #define task_is_running(task) (READ_ONCE((task)->__state) == TASK_RUNNING) #define task_is_traced(task) ((READ_ONCE(task->jobctl) & JOBCTL_TRACED) != 0) @@ -1525,6 +1527,14 @@ struct task_struct { union rv_task_monitor rv[RV_PER_TASK_MONITORS]; #endif +#ifdef CONFIG_IPC_CLASSES + /* + * A hardware-defined classification of task based on the number + * of instructions per cycle. + */ + unsigned int ipcc; +#endif + /* * New fields for task_struct should be added above here, so that * they are included in the randomized portion of task_struct. diff --git a/init/Kconfig b/init/Kconfig index abf65098f1b6..cd17dd4d3718 100644 --- a/init/Kconfig +++ b/init/Kconfig @@ -865,6 +865,18 @@ config UCLAMP_BUCKETS_COUNT If in doubt, use the default value. +config IPC_CLASSES + bool "IPC classes of tasks" + depends on SMP + help + If selected, each task is assigned a classification value that + reflects the type of instructions that the task executes. This + classification reflects but is not equal to the number of + instructions retired per cycle. + + The scheduler uses the classification value to improve the placement + of tasks. + endmenu # From patchwork Mon Nov 28 13:20:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 26754 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5657011wrr; Mon, 28 Nov 2022 05:14:44 -0800 (PST) X-Google-Smtp-Source: AA0mqf7+A5beBwDQlBQuOKk1NWALD2lDFglkJUmgJ+ARR3JolQC3I7I9XHzK3VL97XuHcxLBn8j+ X-Received: by 2002:a17:902:aa06:b0:182:f36b:3221 with SMTP id be6-20020a170902aa0600b00182f36b3221mr32056949plb.36.1669641283952; Mon, 28 Nov 2022 05:14:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669641283; cv=none; d=google.com; s=arc-20160816; b=eN8xLUgGYZ3UffyLtZ4Qi6gXRu7v57XYzBuRwtIVa4IQz5Gh4doYF/BB/4Jn+RkXuc GkY/rDWCD4U8gChqirHFWIlDh51s+fPTT9p4bgSwq3Fi5FCf77kxqygvxBvCFVxYKR5h 42eVopZJsiatzkAJBkumPN2G4baZawdyRjYauFwO/I4hY1aUF/SyU0W5pAzjz5nmA4ul jHtHRjN+BA4Tmy3GKFDRRB2NkJq7G8ZwWDeH4GNYuMxrr4eMyMOqwKOSuYtNauWi5GJp 6u5qm7ECcLrpX2o0ujOj8N4mSAMVXNwMOwnQXVc+lzOXEG83MfdLXltY/K490ELbNctu qwsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=skNG8/ZfQF/Vc9Rc1zfjS6CgcgfonYU1VL6OCDUwwf8=; b=tUj7/xPiu2uM9P3yrViEgaJO+tVDuHQEmWBWTJsNVsTDntHS0Vb6ij8btYcC+X+Ef6 dIHOUc9sjP5n9yaGrFzogP+CBm4gOPwdL9cfusXwfJ0nY3+pwNb4tU4ezy25CysOPf8O iExa8Z9UzSN5z4/utn3dGFrIvSildky/9PAOfuieu68umAmMMywF2I2M/mnBIjfstReu n+40iqfI9Oo77XBs12Z8jFTsqLNagCydbo/7aSu5f0vLyqTuWx+6pMznHyGiw61M1yfj zNNeB6bxDKynkxndEUkw3Dxbn0TwrJBDkxdBbigsJUO/C2MRTC9Ayf+qXGjU21XCkMDK i1cA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=MB5KWN8H; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Shankar" , Ben Segall , Daniel Bristot de Oliveira , Dietmar Eggemann , Len Brown , Mel Gorman , "Rafael J. Wysocki" , Srinivas Pandruvada , Steven Rostedt , Tim Chen , Valentin Schneider , x86@kernel.org, "Joel Fernandes (Google)" , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Ricardo Neri , "Tim C . Chen" Subject: [PATCH v2 02/22] sched: Add interfaces for IPC classes Date: Mon, 28 Nov 2022 05:20:40 -0800 Message-Id: <20221128132100.30253-3-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> References: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750745778990059925?= X-GMAIL-MSGID: =?utf-8?q?1750745778990059925?= Add the interfaces that architectures shall implement to convey the data to support IPC classes. arch_update_ipcc() updates the IPC classification of the current task as given by hardware. arch_get_ipcc_score() provides a performance score for a given IPC class when placed on a specific CPU. Higher scores indicate higher performance. The number of classes and the score of each class of task are determined by hardware. Cc: Ben Segall Cc: Daniel Bristot de Oliveira Cc: Dietmar Eggemann Cc: Joel Fernandes (Google) Cc: Len Brown Cc: Mel Gorman Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Steven Rostedt Cc: Tim C. Chen Cc: Valentin Schneider Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ricardo Neri --- Changes since v1: * Shortened the names of the IPCC interfaces (PeterZ): sched_task_classes_enabled >> sched_ipcc_enabled arch_has_task_classes >> arch_has_ipc_classes arch_update_task_class >> arch_update_ipcc arch_get_task_class_score >> arch_get_ipcc_score * Removed smt_siblings_idle argument from arch_update_ipcc(). (PeterZ) --- kernel/sched/sched.h | 60 +++++++++++++++++++++++++++++++++++++++++ kernel/sched/topology.c | 8 ++++++ 2 files changed, 68 insertions(+) diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h index b1d338a740e5..75e22baa2622 100644 --- a/kernel/sched/sched.h +++ b/kernel/sched/sched.h @@ -2531,6 +2531,66 @@ void arch_scale_freq_tick(void) } #endif +#ifdef CONFIG_IPC_CLASSES +DECLARE_STATIC_KEY_FALSE(sched_ipcc); + +static inline bool sched_ipcc_enabled(void) +{ + return static_branch_unlikely(&sched_ipcc); +} + +#ifndef arch_has_ipc_classes +/** + * arch_has_ipc_classes() - Check whether hardware supports IPC classes of tasks + * + * Returns: true of IPC classes of tasks are supported. + */ +static __always_inline +bool arch_has_ipc_classes(void) +{ + return false; +} +#endif + +#ifndef arch_update_ipcc +/** + * arch_update_ipcc() - Update the IPC class of the current task + * @curr: The current task + * + * Request that the IPC classification of @curr is updated. + * + * Returns: none + */ +static __always_inline +void arch_update_ipcc(struct task_struct *curr) +{ +} +#endif + +#ifndef arch_get_ipcc_score +/** + * arch_get_ipcc_score() - Get the IPC score of a class of task + * @ipcc: The IPC class + * @cpu: A CPU number + * + * Returns the performance score of an IPC class when running on @cpu. + * Error when either @class or @cpu are invalid. + */ +static __always_inline +int arch_get_ipcc_score(unsigned short ipcc, int cpu) +{ + return 1; +} +#endif +#else /* CONFIG_IPC_CLASSES */ + +#define arch_get_ipcc_score(ipcc, cpu) (-EINVAL) +#define arch_update_ipcc(curr) + +static inline bool sched_ipcc_enabled(void) { return false; } + +#endif /* CONFIG_IPC_CLASSES */ + #ifndef arch_scale_freq_capacity /** * arch_scale_freq_capacity - get the frequency scale factor of a given CPU. diff --git a/kernel/sched/topology.c b/kernel/sched/topology.c index 8154ef590b9f..eb1654b64df7 100644 --- a/kernel/sched/topology.c +++ b/kernel/sched/topology.c @@ -669,6 +669,9 @@ DEFINE_PER_CPU(struct sched_domain __rcu *, sd_numa); DEFINE_PER_CPU(struct sched_domain __rcu *, sd_asym_packing); DEFINE_PER_CPU(struct sched_domain __rcu *, sd_asym_cpucapacity); DEFINE_STATIC_KEY_FALSE(sched_asym_cpucapacity); +#ifdef CONFIG_IPC_CLASSES +DEFINE_STATIC_KEY_FALSE(sched_ipcc); +#endif static void update_top_cache_domain(int cpu) { @@ -2388,6 +2391,11 @@ build_sched_domains(const struct cpumask *cpu_map, struct sched_domain_attr *att if (has_asym) static_branch_inc_cpuslocked(&sched_asym_cpucapacity); +#ifdef CONFIG_IPC_CLASSES + if (arch_has_ipc_classes()) + static_branch_enable_cpuslocked(&sched_ipcc); +#endif + if (rq && sched_debug_verbose) { pr_info("root domain span: %*pbl (max cpu_capacity = %lu)\n", cpumask_pr_args(cpu_map), rq->rd->max_cpu_capacity); From patchwork Mon Nov 28 13:20:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 26751 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5656855wrr; Mon, 28 Nov 2022 05:14:32 -0800 (PST) X-Google-Smtp-Source: AA0mqf7QwonLSHtCMPFBNW64JVMSMx8phpUZn2AKFmOHB6JLtaOxePu29mjQ741hzZQmgqaFdp2+ X-Received: by 2002:a17:902:ea91:b0:189:6f76:9b5f with SMTP id x17-20020a170902ea9100b001896f769b5fmr13529936plb.56.1669641272047; Mon, 28 Nov 2022 05:14:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669641272; cv=none; d=google.com; s=arc-20160816; b=MljBVezg1afmdBiVzUY9UuSLK4zzct5HuGZzAK7meyk8XPcEiTLMJv9bbPJ6tAdhi7 S3vCU7wxf3xmcqAuGbQ1sT+RUaaOlmhj+5KxBIpo1sCmIB2tyfJWhKyIQ6cYDaTbuvC2 qGinYd+9wcm4aE/KGoBGXJ8/1cTVe0QhDBlmGU3rXIuMKZ3CQkKI1l2jk3cTnBIroV1H CAmHKMwzYjn7/W5kpz9++plB7bu/8R9CP0J6GY2HFzTV61HylsyrF0SoGf3a6hwyJ0/B CranZs1e80B9PwxPQihS1Gug8exwJpNpD+IFOMMhnhSCdgo/Il3nbTXuDdovnDgPj7eM Rx7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=W32Vi/LD1bOMM2BjPlo4QEBd1f/nyEH4e6c1SrnqUso=; b=AmR3k9hZSPQMe++E2DIxRF9aQ4ozGv64AD+ZPqTGLBeqxCuK3P7ztnHk+do/nZkqKW VRaXa6NmEFGbeyK9Z4M1W9vG3QZd7rWIMS1yoAgGLvAxhKTn/RAb77SaHxfwuOnqYmsh ycUXVQ2iSLxfBHxYbkRqvkoKlo9j/xmbGwlh4uUr8QdDJAOc+aNOdZorgzjdDHa7fgBQ rbulRa8Tg8EkvArIbqyfgzObww6OVbOF1AUT1RjLkkHaJMOb1owU8LpskT/EOYcQENCt TOClhXFno+kqQvZONExVUU4LL5pUHD195YCSW5UVxzy2ZD7gox6ZM9GQ2G2L2194cGY5 p6nQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=V03l0WTH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Shankar" , Ben Segall , Daniel Bristot de Oliveira , Dietmar Eggemann , Len Brown , Mel Gorman , "Rafael J. Wysocki" , Srinivas Pandruvada , Steven Rostedt , Tim Chen , Valentin Schneider , x86@kernel.org, "Joel Fernandes (Google)" , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Ricardo Neri , "Tim C . Chen" Subject: [PATCH v2 03/22] sched/core: Initialize the IPC class of a new task Date: Mon, 28 Nov 2022 05:20:41 -0800 Message-Id: <20221128132100.30253-4-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> References: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750745766369044092?= X-GMAIL-MSGID: =?utf-8?q?1750745766369044092?= New tasks shall start life as unclassified. They will be classified by hardware when they run. Cc: Ben Segall Cc: Daniel Bristot de Oliveira Cc: Dietmar Eggemann Cc: Joel Fernandes (Google) Cc: Len Brown Cc: Mel Gorman Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Steven Rostedt Cc: Tim C. Chen Cc: Valentin Schneider Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ricardo Neri --- Changes since v1: * None --- kernel/sched/core.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/kernel/sched/core.c b/kernel/sched/core.c index 78b2d5cabcc5..8dd43ee05534 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -4372,6 +4372,9 @@ static void __sched_fork(unsigned long clone_flags, struct task_struct *p) p->se.prev_sum_exec_runtime = 0; p->se.nr_migrations = 0; p->se.vruntime = 0; +#ifdef CONFIG_IPC_CLASSES + p->ipcc = IPC_CLASS_UNCLASSIFIED; +#endif INIT_LIST_HEAD(&p->se.group_node); #ifdef CONFIG_FAIR_GROUP_SCHED From patchwork Mon Nov 28 13:20:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 26753 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5657016wrr; Mon, 28 Nov 2022 05:14:44 -0800 (PST) X-Google-Smtp-Source: AA0mqf5a5kagtOvmby+3Ra9ERR6FqIDYyDvHm4Q4CDAK94K9ZUmyq7iWGWR2LynLQbY9voDXHzvu X-Received: by 2002:a17:90a:8d02:b0:219:1ffc:143c with SMTP id c2-20020a17090a8d0200b002191ffc143cmr10451503pjo.9.1669641284000; Mon, 28 Nov 2022 05:14:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669641283; cv=none; d=google.com; s=arc-20160816; b=CoYedSP5iWc8NEVoACVMPGGdxWQ7vgEZ7HU4kGsGvT/gRYVROj+9jLKEDQtHXP95Jv GSuiaW6rdAAuiL9qKBHdjAO76Yfxhn8bCdIMYPcelB2h1c8pOBAFGOOHsK1UgeKDR0Xm AlATWBavYg5QPnbsO0nHiI4N37QfWecdLpmSTX9LRlpswJHQtjBi66Z9ni0VSjxZjfl3 caFAN6y1v7qyBScE/EIfOPznZYDpMbFX1uC0xtmiKXcUb0odEYT1MxmyIY+84pQmjWBd fDsuajQPPqEoATkca87+ku3Uy8Od2rUPH09k1xULngCjzemkzl4ZmGH2WQfr7yi5xKit yOEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=6pPsulVC8b9yNYNqEg9I5BMIX3bXiY4OPVkqTr1S22g=; b=FT9Zc8EPKHWBwXHNEo1HPhJYC9dtDAmYz5yQjHJ95/HFLyFBdjwi9YstTlJtAsCh5J SEeKhWBQgfBVgKuj9+354zryHTEFZjy1EujewuLzGGUAAPNy8YkKaSVj4/6VTBpA5hoA wX3C6HYgd7ALh5iRYwx2kGGRWL2oevrJQpKrSRD3g36h9wAet7YpdmS1i2sy2z5FyJHF aj8recqVfbT+MfP4Y8FW4LFeIZTDZ6XAgwwQCa1n1d1cQbwguAnD9SrKRIHtkwrFIRBx J+gaopKq+QAPSKX6ChYg15I4gO00rFAL1w47spArVxKWEAiO1gNrxi1EW6kBdhyGYmHH B6ug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=CIquFBho; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Shankar" , Ben Segall , Daniel Bristot de Oliveira , Dietmar Eggemann , Len Brown , Mel Gorman , "Rafael J. Wysocki" , Srinivas Pandruvada , Steven Rostedt , Tim Chen , Valentin Schneider , x86@kernel.org, "Joel Fernandes (Google)" , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Ricardo Neri , "Tim C . Chen" Subject: [PATCH v2 04/22] sched/core: Add user_tick as argument to scheduler_tick() Date: Mon, 28 Nov 2022 05:20:42 -0800 Message-Id: <20221128132100.30253-5-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> References: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750745778653704288?= X-GMAIL-MSGID: =?utf-8?q?1750745778653704288?= Differentiate between user and kernel ticks so that the scheduler updates the IPC class of the current task during the latter. Cc: Ben Segall Cc: Daniel Bristot de Oliveira Cc: Dietmar Eggemann Cc: Joel Fernandes (Google) Cc: Len Brown Cc: Mel Gorman Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Steven Rostedt Cc: Tim C. Chen Cc: Valentin Schneider Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ricardo Neri --- Changes since v1: * None --- include/linux/sched.h | 2 +- kernel/sched/core.c | 2 +- kernel/time/timer.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/linux/sched.h b/include/linux/sched.h index 47ae3557ba07..ddabc7449edd 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -293,7 +293,7 @@ enum { TASK_COMM_LEN = 16, }; -extern void scheduler_tick(void); +extern void scheduler_tick(bool user_tick); #define MAX_SCHEDULE_TIMEOUT LONG_MAX diff --git a/kernel/sched/core.c b/kernel/sched/core.c index 8dd43ee05534..8bb6f597c42b 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -5487,7 +5487,7 @@ static inline u64 cpu_resched_latency(struct rq *rq) { return 0; } * This function gets called by the timer code, with HZ frequency. * We call it with interrupts disabled. */ -void scheduler_tick(void) +void scheduler_tick(bool user_tick) { int cpu = smp_processor_id(); struct rq *rq = cpu_rq(cpu); diff --git a/kernel/time/timer.c b/kernel/time/timer.c index 63a8ce7177dd..e15e24105891 100644 --- a/kernel/time/timer.c +++ b/kernel/time/timer.c @@ -2073,7 +2073,7 @@ void update_process_times(int user_tick) if (in_irq()) irq_work_tick(); #endif - scheduler_tick(); + scheduler_tick(user_tick); if (IS_ENABLED(CONFIG_POSIX_TIMERS)) run_posix_cpu_timers(); } From patchwork Mon Nov 28 13:20:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 26752 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5656941wrr; Mon, 28 Nov 2022 05:14:38 -0800 (PST) X-Google-Smtp-Source: AA0mqf6LS3MIsFubnbICcGdpCxyuHJxaLjMHT5bCLD9DiG1BZ5TTvTfTEVVuDpSi+FjxrSOdFUtS X-Received: by 2002:a63:155e:0:b0:476:95a8:de91 with SMTP id 30-20020a63155e000000b0047695a8de91mr26997887pgv.102.1669641278035; Mon, 28 Nov 2022 05:14:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669641278; cv=none; d=google.com; s=arc-20160816; b=u/0XEDndZdJG1ghVBjXEyMtj1hHbVmXOHFSqe3eynDEyFHMw7BN9vYatHa6VxtFC8D dkpxk3eJXKkrn3lTN/dhy9E9Td2N+uIrotjb8iNyo0Uuaw1o0WkojUajjsHMHvNQnTvP /7Lg5kXQXkTRUOp4kSkom15Cwpi3QjT6NlXgGBgJ+Zavi7wEQuDDtnq+aPGqLgt+kP2E yFJV6fv54R1qexE6b2Q1IUFFFyPczijoQ2AgwyNyziUoz0vokLDqyJOKnTcYkJEDNbDH BawXeHN4y720XsMwDW8UPwdaL91AF+l7wo+fh7Y47LbZA9UStwq/YU+e+BHiOtc7tcXh uyUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=oPK1MF5KUETm/siFAkp5nqNalPGNEYIoQPdZ+1qM8N0=; b=wHvJ2ERC41L3pKB2LGiRbhxXnG8yaZawPVgwajacdMuqIXqrNvXDLxXmOKXHBUuxPp 4FlYwn0GGRcHwDJbzeA8VCRsIOwKxogKakuJ9bYQtx1qWDPXKLUk/XLRB19ikJIuhBYy GJqJX+YhgHewOSwOtWhkDPiBcTz50y+Ft3Y1R5X55aypS9atzLrEd2RyhBgKHddRwUSs 76QE34oV7LK5n56iWznG8TrQkWyTP9tTE6gfs63EyUs7qtKWIrNizGv5W9Qdp0rUuLsY +nqjGlw8R1ojBRC8/hN50Kx8dMxmkU3JP9lGWkReZ/8fXF2iHFudYf+uozKGqVQ4DX+r ExNA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="MFqN/Seu"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Shankar" , Ben Segall , Daniel Bristot de Oliveira , Dietmar Eggemann , Len Brown , Mel Gorman , "Rafael J. Wysocki" , Srinivas Pandruvada , Steven Rostedt , Tim Chen , Valentin Schneider , x86@kernel.org, "Joel Fernandes (Google)" , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Ricardo Neri , "Tim C . Chen" Subject: [PATCH v2 05/22] sched/core: Update the IPC class of the current task Date: Mon, 28 Nov 2022 05:20:43 -0800 Message-Id: <20221128132100.30253-6-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> References: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750745772873199800?= X-GMAIL-MSGID: =?utf-8?q?1750745772873199800?= When supported, hardware monitors the instruction stream to classify the current task. Hence, at userspace tick, we are ready to read the most recent classification result for the current task. Cc: Ben Segall Cc: Daniel Bristot de Oliveira Cc: Dietmar Eggemann Cc: Joel Fernandes (Google) Cc: Len Brown Cc: Mel Gorman Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Steven Rostedt Cc: Tim C. Chen Cc: Valentin Schneider Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ricardo Neri --- Changes since v1: * Removed argument smt_siblings_idle from call to arch_ipcc_update(). * Used the new IPCC interfaces names. --- kernel/sched/core.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/kernel/sched/core.c b/kernel/sched/core.c index 8bb6f597c42b..2cd409536b72 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -5496,6 +5496,9 @@ void scheduler_tick(bool user_tick) unsigned long thermal_pressure; u64 resched_latency; + if (sched_ipcc_enabled() && user_tick) + arch_update_ipcc(curr); + arch_scale_freq_tick(); sched_clock_tick(); From patchwork Mon Nov 28 13:20:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 26757 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5657156wrr; Mon, 28 Nov 2022 05:14:56 -0800 (PST) X-Google-Smtp-Source: AA0mqf4DcEibPmq0U7wvoCegBs5e1ndsomCQ/b2DuTgak0PHr5ZrmB13ibxTZx6CHZn5beLk72KM X-Received: by 2002:a17:902:db09:b0:186:f36a:63b2 with SMTP id m9-20020a170902db0900b00186f36a63b2mr31241989plx.128.1669641295933; Mon, 28 Nov 2022 05:14:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669641295; cv=none; d=google.com; s=arc-20160816; b=k3FX3j0cGgDHYQtqgUKoy5uZxql3wzgCtPnDc+V7T1oTLzbNkxAv0hlx0VPqqGozVy vHEkz4K/xoPl3EpR+C42mKGcLmQjoAAqriuBFwbcek9ub4xxd2YaqK+Y0yo6q/te9LK6 hZzNyH2avMRI5jqmRqTaIUoPyvz4GDeK/SBSd3i5EusUw+hkKy3hqDLEBjXEYK9O9MGf iFLKSJSichQGcNrHgI09s1Qt5jMAQWAZ/mCI4V3/bjNUiyRYEs09iJxg/g8r8WWr1xPb IMA1H/tb0a7uHQKrP52kFgEiEHuqqavb3ngOrP3KgwuT3N8y4/VGt+csQgWQxucXAvGe MvNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=fKZU95c2uKxJI8rZ3Vl0PXFq89vThodeMl2Ndj88Gmc=; b=hJkrCcFhtAvGJN4IE+5A8Esz3L3QLRvVAYFxWCdihTEPWZyxNCVaATwXFEHD48vmJb Z7sewFpW2mLdINt7plNEMZiX0Z9sg/wKAn9jiPQ4qEw1hvQAtarCCWESJjNFiYY9ZZMX F+KSgvWlWBhqBwj6540lOfAT10FMIBOkNLxi8zS5sIn/oQyddUW8/vd0t+5unuEUGZkQ 9G96+S0F4GoY2pBNqJ2KAF0pfhvI6xiATZGZClqsrnQLKVC709wgAkTIfnkqlaNeymH6 lk2xf+VgFp3OPjn3TklHV5SqOF5VQYO1gs2rxAtfBZR0UPYTiPS/pufdWkaLhL3ITBqz b2GQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=aS5gpUB5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id k185-20020a6384c2000000b00476c369eaa9si12621965pgd.146.2022.11.28.05.14.41; Mon, 28 Nov 2022 05:14:55 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=aS5gpUB5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231818AbiK1NOQ (ORCPT + 99 others); Mon, 28 Nov 2022 08:14:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40088 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231660AbiK1NNi (ORCPT ); Mon, 28 Nov 2022 08:13:38 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 80F121D675; Mon, 28 Nov 2022 05:13:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669641217; x=1701177217; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=bGQyQKNPbV4jkYdbDYkNg5GZCIoRHz5qvQ3UspaGSq0=; b=aS5gpUB51cG2KwtKRyqqMPr/zzbMb3muopZIkuvj2n9GJlu08ulRQAVM sp/YONifCZxsl+vDaQaHzCMLfWRCxyvsKL9MBdwNKXxMQJNZikhQ58SgZ 8YtqjHIxJ2Nn9PegIYdj7xa3Qi9fnWrv9OvRxJ/hFIGEQThkBC7Y4PigB 5TtYthlWfGoAzzCyXn47u6Gb5yn3Z9bWzaC3kf5Uax9XOm0ZdqkfZdrGp 7hCFNA5sKqV3pJmdBIyArMg6TUnW7W2F+0QIETBZGZwISm7/d0BT+ikr3 AGiZ8qPbIRU9uCIcyGKtuKQ6WoXZntzLVhTRezo3FoPV84ak0JiRNXPk/ Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10544"; a="401117105" X-IronPort-AV: E=Sophos;i="5.96,200,1665471600"; d="scan'208";a="401117105" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Nov 2022 05:13:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10544"; a="749381342" X-IronPort-AV: E=Sophos;i="5.96,200,1665471600"; d="scan'208";a="749381342" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga002.fm.intel.com with ESMTP; 28 Nov 2022 05:13:32 -0800 From: Ricardo Neri To: "Peter Zijlstra (Intel)" , Juri Lelli , Vincent Guittot Cc: Ricardo Neri , "Ravi V. Shankar" , Ben Segall , Daniel Bristot de Oliveira , Dietmar Eggemann , Len Brown , Mel Gorman , "Rafael J. Wysocki" , Srinivas Pandruvada , Steven Rostedt , Tim Chen , Valentin Schneider , x86@kernel.org, "Joel Fernandes (Google)" , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Ricardo Neri , "Tim C . Chen" Subject: [PATCH v2 06/22] sched/fair: Collect load-balancing stats for IPC classes Date: Mon, 28 Nov 2022 05:20:44 -0800 Message-Id: <20221128132100.30253-7-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> References: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750745791744900425?= X-GMAIL-MSGID: =?utf-8?q?1750745791744900425?= When selecting a busiest scheduling group, the IPC class of the current task can be used to select between two scheduling groups of equal asym_packing priority and number of running tasks. Compute a new IPC class performance score for a scheduling group. It is the sum of the performance of the current tasks of all the runqueues. Also, keep track of the task with the lowest IPC class score on the scheduling group. These two metrics will be used during idle load balancing to compute the current and the prospective task-class performance of a scheduling group. Cc: Ben Segall Cc: Daniel Bristot de Oliveira Cc: Dietmar Eggemann Cc: Joel Fernandes (Google) Cc: Len Brown Cc: Mel Gorman Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Steven Rostedt Cc: Tim C. Chen Cc: Valentin Schneider Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ricardo Neri --- Changes since v1: * Implemented cleanups and reworks from PeterZ. Thanks! * Used the new interface names. --- kernel/sched/fair.c | 55 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index 224107278471..3a1d6c50a19b 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -9100,6 +9100,57 @@ group_type group_classify(unsigned int imbalance_pct, return group_has_spare; } +struct sg_lb_ipcc_stats { + int min_score; /* Min(score(rq->curr->ipcc)) */ + int min_ipcc; /* Min(rq->curr->ipcc) */ + long sum_score; /* Sum(score(rq->curr->ipcc)) */ +}; + +#ifdef CONFIG_IPC_CLASSES +static void init_rq_ipcc_stats(struct sg_lb_ipcc_stats *sgcs) +{ + *sgcs = (struct sg_lb_ipcc_stats) { + .min_score = INT_MAX, + }; +} + +/** Called only if cpu_of(@rq) is not idle and has tasks running. */ +static void update_sg_lb_ipcc_stats(struct sg_lb_ipcc_stats *sgcs, + struct rq *rq) +{ + struct task_struct *curr; + unsigned short ipcc; + int score; + + if (!sched_ipcc_enabled()) + return; + + curr = rcu_dereference(rq->curr); + if (!curr || (curr->flags & PF_EXITING) || is_idle_task(curr)) + return; + + ipcc = curr->ipcc; + score = arch_get_ipcc_score(ipcc, cpu_of(rq)); + + sgcs->sum_score += score; + + if (score < sgcs->min_score) { + sgcs->min_score = score; + sgcs->min_ipcc = ipcc; + } +} + +#else /* CONFIG_IPC_CLASSES */ +static void update_sg_lb_ipcc_stats(struct sg_lb_ipcc_stats *sgcs, + struct rq *rq) +{ +} + +static void init_rq_ipcc_stats(struct sg_lb_ipcc_stats *class_sgs) +{ +} +#endif /* CONFIG_IPC_CLASSES */ + /** * asym_smt_can_pull_tasks - Check whether the load balancing CPU can pull tasks * @dst_cpu: Destination CPU of the load balancing @@ -9212,9 +9263,11 @@ static inline void update_sg_lb_stats(struct lb_env *env, struct sg_lb_stats *sgs, int *sg_status) { + struct sg_lb_ipcc_stats sgcs; int i, nr_running, local_group; memset(sgs, 0, sizeof(*sgs)); + init_rq_ipcc_stats(&sgcs); local_group = group == sds->local; @@ -9264,6 +9317,8 @@ static inline void update_sg_lb_stats(struct lb_env *env, if (sgs->group_misfit_task_load < load) sgs->group_misfit_task_load = load; } + + update_sg_lb_ipcc_stats(&sgcs, rq); } sgs->group_capacity = group->sgc->capacity; From patchwork Mon Nov 28 13:20:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 26755 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5657112wrr; Mon, 28 Nov 2022 05:14:51 -0800 (PST) X-Google-Smtp-Source: AA0mqf4M2RXzls+KMNPn/s7a0Gwwd72iRc1si3P3ScnomIQkwZRcRGbb8WTA1j7bHpRL7H3PL+B4 X-Received: by 2002:a17:902:b20f:b0:188:d4ea:251f with SMTP id t15-20020a170902b20f00b00188d4ea251fmr44345087plr.36.1669641291237; Mon, 28 Nov 2022 05:14:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669641291; cv=none; d=google.com; s=arc-20160816; b=MCTqJCw3ckpXEW3MRt0tIlUrtD8Fnfq7DpM1DYZke8bnJA9QEH9zN9B5i2iRYmskKR uP8RxKSPwV6DrONAITPoBzup8hhzxkKyarL8EHPZZRSqRFUmetZEvDPY1Apjw8eAQUgJ 4gGLZ1WhPNIXDXIt2mmMTsiuZP7hQWMl43QKOEew1kuLxdFPsD8ENKnq6+pJkDSj1z7d lomt+WcXstPAIaE1W0yhxcEkEowC4+MOUnD0ntF47Wa3eRqxie9KjW5YObv6FAeeQ7LT m1yIv2/R3C59nygJHNz8eDDQQxLWR0X5RHWN3fFbVkb9+yq3qit4DeoAoBIsOf0xLBJI Nrpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=J2/oF+mdjqb+42cc7Aj5SPoRfJDqnvZ1A7r4imzOzJU=; b=JokUTvdPj1TmjJt/XiMp3co+B6na/kxY2ICewNtT+c8ZCAejsX5gGfOkNZoaKYHDfL n9ouiB0cINutysxaMhusCneX+U70PbtM6UEHW1KsX2GPSzzH3lg4w2y4x+ySLAESAVRa UuYJYhc4/lJixD0XCWof6fb9+MZj5NV2AoAJjv5efX7U+BdL3H4R62wmKnYVSw0o68k7 U7ndg7DydWX7TH5G4l079/jjXwauUihIWf8CXDSk8LKUoXpQZCoW2aTaFkYvSxqvpd8o 4241gft5gFr+lJtzk5UAEa6IHSMlwHji2Kgqtkm0Jkzz3Yp6QNp3+E2hDxF3i/3SZWxI Xj0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=W2mD71dO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Shankar" , Ben Segall , Daniel Bristot de Oliveira , Dietmar Eggemann , Len Brown , Mel Gorman , "Rafael J. Wysocki" , Srinivas Pandruvada , Steven Rostedt , Tim Chen , Valentin Schneider , x86@kernel.org, "Joel Fernandes (Google)" , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Ricardo Neri , "Tim C . Chen" Subject: [PATCH v2 07/22] sched/fair: Compute IPC class scores for load balancing Date: Mon, 28 Nov 2022 05:20:45 -0800 Message-Id: <20221128132100.30253-8-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> References: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750745786156015088?= X-GMAIL-MSGID: =?utf-8?q?1750745786156015088?= Compute the joint total (both current and prospective) IPC class score of a scheduling group and the local scheduling group. These IPCC statistics are used during asym_packing load balancing. It implies that the candidate sched group will have one fewer busy CPU after load balancing. This observation is important for physical cores with SMT support. The IPCC score of scheduling groups composed of SMT siblings needs to consider that the siblings share CPU resources. When computing the total IPCC score of the scheduling group, divide score from each sibilng by the number of busy siblings. Cc: Ben Segall Cc: Daniel Bristot de Oliveira Cc: Dietmar Eggemann Cc: Joel Fernandes (Google) Cc: Len Brown Cc: Mel Gorman Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Steven Rostedt Cc: Tim C. Chen Cc: Valentin Schneider Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ricardo Neri --- Changes since v1: * Implemented cleanups and reworks from PeterZ. I took all his suggestions, except the computation of the IPC score before and after load balancing. We are computing not the average score, but the *total*. * Check for the SD_SHARE_CPUCAPACITY to compute the throughput of the SMT siblings of a physical core. * Used the new interface names. * Reworded commit message for clarity. --- kernel/sched/fair.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index 3a1d6c50a19b..e333f9623b3a 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -8766,6 +8766,10 @@ struct sg_lb_stats { unsigned int nr_numa_running; unsigned int nr_preferred_running; #endif +#ifdef CONFIG_IPC_CLASSES + long ipcc_score_after; /* Prospective IPCC score after load balancing */ + long ipcc_score_before; /* IPCC score before load balancing */ +#endif }; /* @@ -9140,6 +9144,38 @@ static void update_sg_lb_ipcc_stats(struct sg_lb_ipcc_stats *sgcs, } } +static void update_sg_lb_stats_scores(struct sg_lb_ipcc_stats *sgcs, + struct sg_lb_stats *sgs, + struct sched_group *sg, + int dst_cpu) +{ + int busy_cpus, score_on_dst_cpu; + long before, after; + + if (!sched_ipcc_enabled()) + return; + + busy_cpus = sgs->group_weight - sgs->idle_cpus; + /* No busy CPUs in the group. No tasks to move. */ + if (!busy_cpus) + return; + + score_on_dst_cpu = arch_get_ipcc_score(sgcs->min_ipcc, dst_cpu); + + before = sgcs->sum_score; + after = before - sgcs->min_score; + + /* SMT siblings share throughput. */ + if (busy_cpus > 1 && sg->flags & SD_SHARE_CPUCAPACITY) { + before /= busy_cpus; + /* One sibling will become idle after load balance. */ + after /= busy_cpus - 1; + } + + sgs->ipcc_score_after = after + score_on_dst_cpu; + sgs->ipcc_score_before = before; +} + #else /* CONFIG_IPC_CLASSES */ static void update_sg_lb_ipcc_stats(struct sg_lb_ipcc_stats *sgcs, struct rq *rq) @@ -9149,6 +9185,14 @@ static void update_sg_lb_ipcc_stats(struct sg_lb_ipcc_stats *sgcs, static void init_rq_ipcc_stats(struct sg_lb_ipcc_stats *class_sgs) { } + +static void update_sg_lb_stats_scores(struct sg_lb_ipcc_stats *sgcs, + struct sg_lb_stats *sgs, + struct sched_group *sg, + int dst_cpu) +{ +} + #endif /* CONFIG_IPC_CLASSES */ /** @@ -9329,6 +9373,7 @@ static inline void update_sg_lb_stats(struct lb_env *env, if (!local_group && env->sd->flags & SD_ASYM_PACKING && env->idle != CPU_NOT_IDLE && sgs->sum_h_nr_running && sched_asym(env, sds, sgs, group)) { + update_sg_lb_stats_scores(&sgcs, sgs, group, env->dst_cpu); sgs->group_asym_packing = 1; } From patchwork Mon Nov 28 13:20:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 26756 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5657119wrr; Mon, 28 Nov 2022 05:14:52 -0800 (PST) X-Google-Smtp-Source: AA0mqf6Vgql+K5C7GY2PgTX+wPjcFvGzG+GBRzIvJpdAjArnnbCZ7XLo7URK0262UCmbwhuC7dmG X-Received: by 2002:a17:902:b691:b0:17e:3f0f:5ad0 with SMTP id c17-20020a170902b69100b0017e3f0f5ad0mr36332327pls.162.1669641292023; Mon, 28 Nov 2022 05:14:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669641292; cv=none; d=google.com; s=arc-20160816; b=JDd5ZFEnJQE+6sgLGYp6AKZL3zto6BCg+iZBuDZGyuiDyoA5KQq52zbFJLNCH4LQkz Coh1UDWLzk4A+kSkou0+6bLJYBt8S7aX9OkngYzQyiX3k6b6EzYetItMj6+xNSyDokp4 lh08nRD9BAn4MmRceeLCqs4gWXoVNhq9eXUgxSeMcHQeyRV4zJxLGBkzRYFInRhKBSp9 DSWCXjXH5TALusGn8IM4srIBPF7rY5zUCROjPDOA/djRSezbxlFc2lLk6pBRoAkBnZ9Y y59S9AlxB4ig+hhgSFy/iTKUOKlprUTDGkqLEZT1nHmVRJgH8IizSvKeRKFcqM9bGrvi 7J6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=CuNc1i9UujAyyFlEJy7WoOA1I9zLz3jyDog95QdXu+s=; b=H8HJDYJSWCRSEcVLBYu6Ct56iyQj0W8/S2dTiSVj5itPzK0qMiARaH/pI7Qh9yzwbU faRClEgD8Db6tdYqmBpVGTNeZ1wjkGpRhmbXAKZzHb1+pBbl8F5rtGxzICpkn+iE1YSN aOr6rFPdcW8xkIbNIMkD38DJoZ7T9+evC8p+7R9SsCbq//40V8GL6417VWHkiSN9I4Mb BKtHBeIqJb/G15EnfYXM37HTC5lltyClK4xgCy3MIJo+9DMH6By2wBGTn8wHPXh/QQu2 877UDZsDaGpkN0wHr8UTps1P2TG2M/3LcpkqdmMgdw9aJBecEGzuvqm1cSCSRUa22Odg SRpg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Mpkr6eFS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Shankar" , Ben Segall , Daniel Bristot de Oliveira , Dietmar Eggemann , Len Brown , Mel Gorman , "Rafael J. Wysocki" , Srinivas Pandruvada , Steven Rostedt , Tim Chen , Valentin Schneider , x86@kernel.org, "Joel Fernandes (Google)" , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Ricardo Neri , "Tim C . Chen" Subject: [PATCH v2 08/22] sched/fair: Use IPC class to pick the busiest group Date: Mon, 28 Nov 2022 05:20:46 -0800 Message-Id: <20221128132100.30253-9-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> References: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750745787600468947?= X-GMAIL-MSGID: =?utf-8?q?1750745787600468947?= As it iterates, update_sd_pick_busiest() keeps on selecting as busiest sched groups of identical priority. Since both groups have the same priority, either group is a good choice. The IPCC score of the tasks placed a sched group can break this tie. Pick as busiest the sched group that yields a higher IPCC score after load balancing. Cc: Ben Segall Cc: Daniel Bristot de Oliveira Cc: Dietmar Eggemann Cc: Joel Fernandes (Google) Cc: Len Brown Cc: Mel Gorman Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Steven Rostedt Cc: Tim C. Chen Cc: Valentin Schneider Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ricardo Neri --- Changes since v1: * Added a comment to clarify why sched_asym_prefer() needs a tie breaker only in update_sd_pick_busiest(). (PeterZ) * Renamed functions for accuracy: sched_asym_class_prefer() >> sched_asym_ipcc_prefer() sched_asym_class_pick() >> sched_asym_ipcc_pick() * Reworded commit message for clarity. --- kernel/sched/fair.c | 75 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index e333f9623b3a..e8b181c31842 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -9176,6 +9176,63 @@ static void update_sg_lb_stats_scores(struct sg_lb_ipcc_stats *sgcs, sgs->ipcc_score_before = before; } +/** + * sched_asym_ipcc_prefer - Select a sched group based on its IPCC score + * @a: Load balancing statistics of @sg_a + * @b: Load balancing statistics of @sg_b + * + * Returns: true if preferring @a has a higher IPCC score than @b after + * balancing load. Returns false otherwise. + */ +static bool sched_asym_ipcc_prefer(struct sg_lb_stats *a, + struct sg_lb_stats *b) +{ + if (!sched_ipcc_enabled()) + return false; + + /* @a increases overall throughput after load balance. */ + if (a->ipcc_score_after > b->ipcc_score_after) + return true; + + /* + * If @a and @b yield the same overall throughput, pick @a if + * its current throughput is lower than that of @b. + */ + if (a->ipcc_score_after == b->ipcc_score_after) + return a->ipcc_score_before < b->ipcc_score_before; + + return false; +} + +/** + * sched_asym_ipcc_pick - Select a sched group based on its IPCC score + * @a: A scheduling group + * @b: A second scheduling group + * @a_stats: Load balancing statistics of @a + * @b_stats: Load balancing statistics of @b + * + * Returns: true if @a has the same priority and @a has tasks with IPCC classes + * that yield higher overall throughput after load balance. + * Returns false otherwise. + */ +static bool sched_asym_ipcc_pick(struct sched_group *a, + struct sched_group *b, + struct sg_lb_stats *a_stats, + struct sg_lb_stats *b_stats) +{ + /* + * Only use the class-specific preference selection if both sched + * groups have the same priority. We are not looking at a specific + * CPU. We do not care about the idle state of the groups' + * preferred CPU. + */ + if (arch_asym_cpu_priority(a->asym_prefer_cpu, false) != + arch_asym_cpu_priority(b->asym_prefer_cpu, false)) + return false; + + return sched_asym_ipcc_prefer(a_stats, b_stats); +} + #else /* CONFIG_IPC_CLASSES */ static void update_sg_lb_ipcc_stats(struct sg_lb_ipcc_stats *sgcs, struct rq *rq) @@ -9193,6 +9250,14 @@ static void update_sg_lb_stats_scores(struct sg_lb_ipcc_stats *sgcs, { } +static bool sched_asym_ipcc_pick(struct sched_group *a, + struct sched_group *b, + struct sg_lb_stats *a_stats, + struct sg_lb_stats *b_stats) +{ + return false; +} + #endif /* CONFIG_IPC_CLASSES */ /** @@ -9452,6 +9517,16 @@ static bool update_sd_pick_busiest(struct lb_env *env, sds->busiest->asym_prefer_cpu, false)) return false; + + /* + * Unlike other callers of sched_asym_prefer(), here both @sg + * and @sds::busiest have tasks running. When they have equal + * priority, their IPC class scores can be used to select a + * better busiest. + */ + if (sched_asym_ipcc_pick(sds->busiest, sg, &sds->busiest_stat, sgs)) + return false; + break; case group_misfit_task: From patchwork Mon Nov 28 13:20:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 26760 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5657506wrr; Mon, 28 Nov 2022 05:15:20 -0800 (PST) X-Google-Smtp-Source: AA0mqf4UiD8U3yeAdCrrrQuEl21IXOQDi/XQ6wea7Gsq6boRP/QlsJs4L41UJEcFLE8O46nGGuga X-Received: by 2002:a63:f5a:0:b0:470:18d4:f18d with SMTP id 26-20020a630f5a000000b0047018d4f18dmr27445974pgp.295.1669641320553; Mon, 28 Nov 2022 05:15:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669641320; cv=none; d=google.com; s=arc-20160816; b=kAEZMartdQ1nVOf+PcZotGMM58Nr/0WSEu1PBHU/CJPEDJxjJiIMgURK3k7N167Yhi k59Lrgt2MaO7phf9OcPj+HN/xlTIjYTqq3z+2ngVeBfkwEDxOv3MZQSmedzCqDX2+R+Q C/8UvFwsYym4kD4AVqykmt+HsR2XA3tDOVDIw112tG1WtT3PyIm5StJbMjP5QHIV3v9q PDxw5jtSzGV0a1/GT9eTo1Nk3cIQifq1G1gXLlPTILzWEjaCxWHNPyCjCV2pkrxTl7Tx QVklLF4bOLGo745B3adKb99+x7BWm1tcZxtDL+FKmssgI0d0GribvTAazO7RTwmQsNKX RQnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=Wj9/IxYjURYHpcVfR0uyKjtR4fqlrTUk40P8zS6/Cws=; b=zOxn1nhrCS2p3BiiytUUMMCDRqOzBU6qWYMZKVqsyI5m9rFXETq7ztzXGE/0wFOjh1 lZ4UfKBConDZ8FU0C7fav0xn/z7niFs0u+qkhCpG5xMYGAKaDvXZvWo1jyZxsVeMkS/t 2U4mW24C5RBVJ2lEkYswEjI2G3rCbUgLZ1Vj//sD5ZC7UUFLIE8NVDNKsM9ZPT7Vfk+0 bnGnHq32BGvIQWla1O0FmcSxR1rvHiF12IMNa30vWBKq/H42pRXVZv8V1E/mY6pgADIv HeGiwyUyouLcEx29/Lqdly1FkCp9aneAw6uqGJFkWSDsBFKRgAjt6h5ilA+a90Wvd6A+ ehWg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=TIsGMRdx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Shankar" , Ben Segall , Daniel Bristot de Oliveira , Dietmar Eggemann , Len Brown , Mel Gorman , "Rafael J. Wysocki" , Srinivas Pandruvada , Steven Rostedt , Tim Chen , Valentin Schneider , x86@kernel.org, "Joel Fernandes (Google)" , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Ricardo Neri , "Tim C . Chen" Subject: [PATCH v2 09/22] sched/fair: Use IPC class score to select a busiest runqueue Date: Mon, 28 Nov 2022 05:20:47 -0800 Message-Id: <20221128132100.30253-10-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> References: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750745817532651359?= X-GMAIL-MSGID: =?utf-8?q?1750745817532651359?= For two runqueues of equal priority and equal number of running of tasks, select the one whose current task would have the highest IPC class score if placed on the destination CPU. Cc: Ben Segall Cc: Daniel Bristot de Oliveira Cc: Dietmar Eggemann Cc: Joel Fernandes (Google) Cc: Len Brown Cc: Mel Gorman Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Steven Rostedt Cc: Tim C. Chen Cc: Valentin Schneider Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ricardo Neri --- Changes since v1: * Fixed a bug when selecting a busiest runqueue: when comparing two runqueues with equal nr_running, we must compute the IPCC score delta of both. * Renamed local variables to improve the layout of the code block. (PeterZ) * Used the new interface names. --- kernel/sched/fair.c | 54 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 53 insertions(+), 1 deletion(-) diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index e8b181c31842..113470bbd7a5 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -9233,6 +9233,24 @@ static bool sched_asym_ipcc_pick(struct sched_group *a, return sched_asym_ipcc_prefer(a_stats, b_stats); } +/** + * ipcc_score_delta - Get the IPCC score delta on a different CPU + * @p: A task + * @alt_cpu: A prospective CPU to place @p + * + * Returns: The IPCC score delta that @p would get if placed on @alt_cpu + */ +static int ipcc_score_delta(struct task_struct *p, int alt_cpu) +{ + unsigned long ipcc = p->ipcc; + + if (!sched_ipcc_enabled()) + return INT_MIN; + + return arch_get_ipcc_score(ipcc, alt_cpu) - + arch_get_ipcc_score(ipcc, task_cpu(p)); +} + #else /* CONFIG_IPC_CLASSES */ static void update_sg_lb_ipcc_stats(struct sg_lb_ipcc_stats *sgcs, struct rq *rq) @@ -9258,6 +9276,11 @@ static bool sched_asym_ipcc_pick(struct sched_group *a, return false; } +static int ipcc_score_delta(struct task_struct *p, int alt_cpu) +{ + return INT_MIN; +} + #endif /* CONFIG_IPC_CLASSES */ /** @@ -10419,8 +10442,8 @@ static struct rq *find_busiest_queue(struct lb_env *env, { struct rq *busiest = NULL, *rq; unsigned long busiest_util = 0, busiest_load = 0, busiest_capacity = 1; + int i, busiest_ipcc_delta = INT_MIN; unsigned int busiest_nr = 0; - int i; for_each_cpu_and(i, sched_group_span(group), env->cpus) { unsigned long capacity, load, util; @@ -10526,8 +10549,37 @@ static struct rq *find_busiest_queue(struct lb_env *env, case migrate_task: if (busiest_nr < nr_running) { + struct task_struct *curr; + busiest_nr = nr_running; busiest = rq; + + /* + * Remember the IPC score delta of busiest::curr. + * We may need it to break a tie with other queues + * with equal nr_running. + */ + curr = rcu_dereference(busiest->curr); + busiest_ipcc_delta = ipcc_score_delta(curr, + env->dst_cpu); + /* + * If rq and busiest have the same number of running + * tasks, pick rq if doing so would give rq::curr a + * bigger IPC boost on dst_cpu. + */ + } else if (sched_ipcc_enabled() && + busiest_nr == nr_running) { + struct task_struct *curr; + int delta; + + curr = rcu_dereference(rq->curr); + delta = ipcc_score_delta(curr, env->dst_cpu); + + if (busiest_ipcc_delta < delta) { + busiest_ipcc_delta = delta; + busiest_nr = nr_running; + busiest = rq; + } } break; From patchwork Mon Nov 28 13:20:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 26758 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5657241wrr; Mon, 28 Nov 2022 05:15:02 -0800 (PST) X-Google-Smtp-Source: AA0mqf5YpKl6Kh5PEFUp53Ulm/mYHfx3bcR+c9mFfX7PSfBKEaqVSljKUXzXfRllstij36+fuff2 X-Received: by 2002:a17:902:6b89:b0:188:bb79:4892 with SMTP id p9-20020a1709026b8900b00188bb794892mr34136845plk.60.1669641302344; Mon, 28 Nov 2022 05:15:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669641302; cv=none; d=google.com; s=arc-20160816; b=zoWI4Vmxj8yiLePTn3ck0j9MIMJRJcRj7LpkkE/wMhfhjc2wR3bEAed20sQEfaSg6U +3F21IzybOi8Vz4RZ8jjWhhwYYQ97oLzatdBzQ9+tuDfophqmqgdEAxvHEGqY13dlwbT uCupmJ9VpfrMGu6b5vd+GAvN6bi9v/FoTUBv8365E8NWbwz2TZPBunUDQymBnaPEoul6 JC2SfsmUzFM85I7KhooMy1nhosrzBflhTifL8QoJba7t7ms4UmeyG60YHAG/p+D2KcFT K7lQmMfDJEuvNw7SElH91UZltjZAAs3Lmf1eFvp24YlrwS92rSNLhEIwPz/qbI8va6XH yLDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=NlmfhQvq5kKgJLgrSLZWDc8p68MpwerAr4LFSdDNKQQ=; b=X0s5My6P0TNlhy3dv/Ut75xLFtdL+TfAEcTzxmoz2Jgz+I570MxtpK07jLGDZ7b4y8 oiqsAYv/t8siQAshN/O4KeMjfQ/EqhfhwRgy8SNZ801sTvb6rXUIWcbTExErZoSQ7NZo KA38oC54/35GBBE880v4FVQHBki+mXTsZ/wFqPxiabUu5r1NQaT452Cbb5fFNeEyMSes cKT3LtR2zSbtpFwq3NA4ElTjHUcwLzuCZliI9scV6FyyknfOXFKdn2epsoI1oaOPAacF 8iTmnAssGb9r8OHwqU3/PngS88mg5NMAy0MHaD4dSTdG2sv6p0j5GTHae/kNsqWSSBg6 dv7Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=dUhTCKb9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Shankar" , Ben Segall , Daniel Bristot de Oliveira , Dietmar Eggemann , Len Brown , Mel Gorman , "Rafael J. Wysocki" , Srinivas Pandruvada , Steven Rostedt , Tim Chen , Valentin Schneider , x86@kernel.org, "Joel Fernandes (Google)" , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Ricardo Neri , "Tim C . Chen" Subject: [PATCH v2 10/22] thermal: intel: hfi: Introduce Intel Thread Director classes Date: Mon, 28 Nov 2022 05:20:48 -0800 Message-Id: <20221128132100.30253-11-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> References: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750745798417954523?= X-GMAIL-MSGID: =?utf-8?q?1750745798417954523?= On Intel hybrid parts, each type of CPU has specific performance and energy efficiency capabilities. The Intel Thread Director technology extends the Hardware Feedback Interface (HFI) to provide performance and energy efficiency data for advanced classes of instructions. Add support to parse and parse per-class capabilities. Cc: Ben Segall Cc: Daniel Bristot de Oliveira Cc: Dietmar Eggemann Cc: Joel Fernandes (Google) Cc: Len Brown Cc: Mel Gorman Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Steven Rostedt Cc: Tim C. Chen Cc: Valentin Schneider Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ricardo Neri --- Changes since v1: * Removed a now obsolete comment. --- drivers/thermal/intel/intel_hfi.c | 30 ++++++++++++++++++++++++------ 1 file changed, 24 insertions(+), 6 deletions(-) diff --git a/drivers/thermal/intel/intel_hfi.c b/drivers/thermal/intel/intel_hfi.c index a0640f762dc5..df4dc50e19fb 100644 --- a/drivers/thermal/intel/intel_hfi.c +++ b/drivers/thermal/intel/intel_hfi.c @@ -79,7 +79,7 @@ union cpuid6_edx { * @ee_cap: Energy efficiency capability * * Capabilities of a logical processor in the HFI table. These capabilities are - * unitless. + * unitless and specific to each HFI class. */ struct hfi_cpu_data { u8 perf_cap; @@ -91,7 +91,8 @@ struct hfi_cpu_data { * @perf_updated: Hardware updated performance capabilities * @ee_updated: Hardware updated energy efficiency capabilities * - * Properties of the data in an HFI table. + * Properties of the data in an HFI table. There exists one header per each + * HFI class. */ struct hfi_hdr { u8 perf_updated; @@ -129,16 +130,21 @@ struct hfi_instance { /** * struct hfi_features - Supported HFI features + * @nr_classes: Number of classes supported * @nr_table_pages: Size of the HFI table in 4KB pages * @cpu_stride: Stride size to locate the capability data of a logical * processor within the table (i.e., row stride) + * @class_stride: Stride size to locate a class within the capability + * data of a logical processor or the HFI table header * @hdr_size: Size of the table header * * Parameters and supported features that are common to all HFI instances */ struct hfi_features { + unsigned int nr_classes; unsigned int nr_table_pages; unsigned int cpu_stride; + unsigned int class_stride; unsigned int hdr_size; }; @@ -325,8 +331,8 @@ static void init_hfi_cpu_index(struct hfi_cpu_info *info) } /* - * The format of the HFI table depends on the number of capabilities that the - * hardware supports. Keep a data structure to navigate the table. + * The format of the HFI table depends on the number of capabilities and classes + * that the hardware supports. Keep a data structure to navigate the table. */ static void init_hfi_instance(struct hfi_instance *hfi_instance) { @@ -507,18 +513,30 @@ static __init int hfi_parse_features(void) /* The number of 4KB pages required by the table */ hfi_features.nr_table_pages = edx.split.table_pages + 1; + /* + * Capability fields of an HFI class are grouped together. Classes are + * contiguous in memory. Hence, use the number of supported features to + * locate a specific class. + */ + hfi_features.class_stride = nr_capabilities; + + /* For now, use only one class of the HFI table */ + hfi_features.nr_classes = 1; + /* * The header contains change indications for each supported feature. * The size of the table header is rounded up to be a multiple of 8 * bytes. */ - hfi_features.hdr_size = DIV_ROUND_UP(nr_capabilities, 8) * 8; + hfi_features.hdr_size = DIV_ROUND_UP(nr_capabilities * + hfi_features.nr_classes, 8) * 8; /* * Data of each logical processor is also rounded up to be a multiple * of 8 bytes. */ - hfi_features.cpu_stride = DIV_ROUND_UP(nr_capabilities, 8) * 8; + hfi_features.cpu_stride = DIV_ROUND_UP(nr_capabilities * + hfi_features.nr_classes, 8) * 8; return 0; } From patchwork Mon Nov 28 13:20:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 26763 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5657799wrr; Mon, 28 Nov 2022 05:15:41 -0800 (PST) X-Google-Smtp-Source: AA0mqf4nStr6G9RCBHvF45hnMnZvRrdvfBqg7pS6wFdq0XOVVQNxC7RZm/7xyfaJ+8c7PJ3tqo8a X-Received: by 2002:a63:4726:0:b0:478:1c87:7fe3 with SMTP id u38-20020a634726000000b004781c877fe3mr4389964pga.233.1669641341567; Mon, 28 Nov 2022 05:15:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669641341; cv=none; d=google.com; s=arc-20160816; b=DC8QCf3q7Y5WX6ZEapj6XtM1mVkgW5DKfkhzJq4uEUhQRZ3knzvPRCbbvmXiuK8c6L MO8oFQCcwJmIcn8rgTHfqzD6Ni3jTYdNhidpFBkYxqVS0eCjxD0Eq+g2NOeceb5CbVqs cVJ0eJz9UdpSBwnEdp6GPXBcvlSi2HNeDfSAtJaLO4BVzavYUSKHVRmFcX9ieov2YFLN qybEW+v9e8hoVDOnhiptDr4cbL56We9lmeUab0Ta7seZd0PIvBHkQSJ2b1OB0jYeIJqB sEBX6hLZ5FYPPPIgpTepgEr+iyB9Vz2gvsrudDp2o8DxYHxGgwK9Gd54l1pMOWxw1Wui LLLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=77Ne8ZGc84HF+iHm8c8ICSuI+Uc7CNCZjIVGtiQ5axM=; b=gCzcrWHnwWPNWSPMRS9P3bd6ieicsH/6M2C6AiFUEbn8/fJDXC8f4IEL/ydJQeCB/3 0t5EGOWTVZKUmYEZjot1aYu7h6BE7l8EGlQLXfwxuUTHMkzLxX3b8ivDX2Qg0QJtc7FO 8ibQAKVDbgfxxsZ6WmgVsRxtpD31QXyV+ouofjAbtlTiOe/nAzurZY2r/bKApw5LK+3s oy5w7miGlthLR1jL0+b1m9yhriDLBaV+TglXhxEHakih2IMXJJW6Xy4WyPcdSQsJ6FJp 9nOGQInQ8/VRlrvN6Ye4e6CjWpPY3Fepzd+32ndBUEpmBJGnjMXM3x4T84eBJEsOJ2qT u6GA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="eP3if2/1"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Shankar" , Ben Segall , Daniel Bristot de Oliveira , Dietmar Eggemann , Len Brown , Mel Gorman , "Rafael J. Wysocki" , Srinivas Pandruvada , Steven Rostedt , Tim Chen , Valentin Schneider , x86@kernel.org, "Joel Fernandes (Google)" , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Ricardo Neri , "Tim C . Chen" Subject: [PATCH v2 11/22] thermal: intel: hfi: Store per-CPU IPCC scores Date: Mon, 28 Nov 2022 05:20:49 -0800 Message-Id: <20221128132100.30253-12-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> References: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750745839513748319?= X-GMAIL-MSGID: =?utf-8?q?1750745839513748319?= The scheduler reads the IPCC scores when balancing load. These reads can be quite frequent. Hardware can also update the HFI table frequently. Concurrent access may cause a lot of contention. It gets worse as the number of CPUs increases. Instead, create separate per-CPU IPCC scores that the scheduler can read without the HFI table lock. Cc: Ben Segall Cc: Daniel Bristot de Oliveira Cc: Dietmar Eggemann Cc: Joel Fernandes (Google) Cc: Len Brown Cc: Mel Gorman Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Steven Rostedt Cc: Tim C. Chen Cc: Valentin Schneider Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Suggested-by: Peter Zijlstra (Intel) Signed-off-by: Ricardo Neri --- Changes since v1: * Added this patch. --- drivers/thermal/intel/intel_hfi.c | 38 +++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/thermal/intel/intel_hfi.c b/drivers/thermal/intel/intel_hfi.c index df4dc50e19fb..56dba967849c 100644 --- a/drivers/thermal/intel/intel_hfi.c +++ b/drivers/thermal/intel/intel_hfi.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -172,6 +173,35 @@ static struct workqueue_struct *hfi_updates_wq; #define HFI_UPDATE_INTERVAL HZ #define HFI_MAX_THERM_NOTIFY_COUNT 16 +#ifdef CONFIG_IPC_CLASSES +static int __percpu *hfi_ipcc_scores; + +static int alloc_hfi_ipcc_scores(void) +{ + hfi_ipcc_scores = __alloc_percpu(sizeof(*hfi_ipcc_scores) * + hfi_features.nr_classes, + sizeof(*hfi_ipcc_scores)); + + return !hfi_ipcc_scores; +} + +static void set_hfi_ipcc_score(void *caps, int cpu) +{ + int i, *hfi_class = per_cpu_ptr(hfi_ipcc_scores, cpu); + + for (i = 0; i < hfi_features.nr_classes; i++) { + struct hfi_cpu_data *class_caps; + + class_caps = caps + i * hfi_features.class_stride; + WRITE_ONCE(hfi_class[i], class_caps->perf_cap); + } +} + +#else +static int alloc_hfi_ipcc_scores(void) { return 0; } +static void set_hfi_ipcc_score(void *caps, int cpu) { } +#endif /* CONFIG_IPC_CLASSES */ + static void get_hfi_caps(struct hfi_instance *hfi_instance, struct thermal_genl_cpu_caps *cpu_caps) { @@ -194,6 +224,8 @@ static void get_hfi_caps(struct hfi_instance *hfi_instance, cpu_caps[i].efficiency = caps->ee_cap << 2; ++i; + + set_hfi_ipcc_score(caps, cpu); } raw_spin_unlock_irq(&hfi_instance->table_lock); } @@ -572,8 +604,14 @@ void __init intel_hfi_init(void) if (!hfi_updates_wq) goto err_nomem; + if (alloc_hfi_ipcc_scores()) + goto err_ipcc; + return; +err_ipcc: + destroy_workqueue(hfi_updates_wq); + err_nomem: for (j = 0; j < i; ++j) { hfi_instance = &hfi_instances[j]; From patchwork Mon Nov 28 13:20:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 26759 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5657460wrr; Mon, 28 Nov 2022 05:15:17 -0800 (PST) X-Google-Smtp-Source: AA0mqf5PE/HrmDaPprbzqXj43OjKfkdr7JCt1gpFbzc2cX838Cx64JsRaJ+3WcRETSBOfw3ZApbw X-Received: by 2002:a62:1413:0:b0:574:e84e:d7a1 with SMTP id 19-20020a621413000000b00574e84ed7a1mr11147430pfu.83.1669641316978; Mon, 28 Nov 2022 05:15:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669641316; cv=none; d=google.com; s=arc-20160816; b=pF5LHxocu4FyL0btYRRUQu/bKrDhxBWEsiO0D3q5HHi/hXSiKzcSlP/2dZ+rs1ucTY JOnp+J0YBu6eaVxuU/yIBt4gw01mrsEZiyi/R1gAl+zr5/NeA724IN+h3U2Tea18TG8B X040hSKNRo0YwSswnM29xJn+b0horQ1c+M49xBIvvqSaNkSQX5xO1K/X+cntVCgOCBOZ XMmmmcv0OtF09mb7jee8d8cSkKnROOnHMRAPs++h1++bbBz8xurA6yDxZ/eRTIq3WdQ5 Ms1eWL3aN8/jx1NB1+Mem1jnIrxirjuzHrEIHwS7g8k95fxcU2CXTc+zPePuUokxqkXg dU0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=jQ1DXAVwj+Ivs2AA3yuC+OjIPLs9DN1UNld7uzJ+aK4=; b=U5o5mAoNowUNcuXwun1Yf8mwSWbdJ6DVB0JSRbXkFpG6xlPw9ZXN14jxUBPGmd8TIi 6UmckT5HQzPaVixG2HTHvD68y3iDGZK/xOkd4+BQ3ECEus2ztAbuKeovDiHNg3BG4MpX AUeFjfqY/Gsp23wvS/EZXSRDtifoeQ5gC9FsbpeGbWwr5DZueWLiPVK7YKmOoaqRelEN +VOf/OCqfmZ32og63jpGgjblxtT97FH+sEscF2XLJZEXLKfm3x0j5iblgpm1AyUYCcPC Z1F3Cu9hdkuuw2u+9l7JJbxTl8LogtHSOohbGl4TK0S4ZBDw9IMkGZoym0cNHmFXepMP YvIA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=j1tgSnHG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Shankar" , Ben Segall , Daniel Bristot de Oliveira , Dietmar Eggemann , Len Brown , Mel Gorman , "Rafael J. Wysocki" , Srinivas Pandruvada , Steven Rostedt , Tim Chen , Valentin Schneider , x86@kernel.org, "Joel Fernandes (Google)" , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Ricardo Neri , "Tim C . Chen" Subject: [PATCH v2 12/22] x86/cpufeatures: Add the Intel Thread Director feature definitions Date: Mon, 28 Nov 2022 05:20:50 -0800 Message-Id: <20221128132100.30253-13-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> References: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750745813703070071?= X-GMAIL-MSGID: =?utf-8?q?1750745813703070071?= Intel Thread Director (ITD) provides hardware resources to classify the current task. The classification reflects the type of instructions that a task currently executes. ITD extends the Hardware Feedback Interface table to provide performance and energy efficiency capabilities for each of the supported classes of tasks. Cc: Ben Segall Cc: Daniel Bristot de Oliveira Cc: Dietmar Eggemann Cc: Joel Fernandes (Google) Cc: Len Brown Cc: Mel Gorman Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Steven Rostedt Cc: Tim C. Chen Cc: Valentin Schneider Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ricardo Neri --- Changes since v1: * Removed dependency on CONFIG_INTEL_THREAD_DIRECTOR. Instead, depend on CONFIG_IPC_CLASSES. * Added DISABLE_ITD to the correct DISABLE_MASK: 14 instead of 13. --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/disabled-features.h | 8 +++++++- arch/x86/kernel/cpu/cpuid-deps.c | 1 + 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index b6525491a41b..80b2beafc81e 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -344,6 +344,7 @@ #define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */ #define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */ #define X86_FEATURE_HFI (14*32+19) /* Hardware Feedback Interface */ +#define X86_FEATURE_ITD (14*32+23) /* Intel Thread Director */ /* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */ #define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */ diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h index c44b56f7ffba..0edd9bef7f2e 100644 --- a/arch/x86/include/asm/disabled-features.h +++ b/arch/x86/include/asm/disabled-features.h @@ -99,6 +99,12 @@ # define DISABLE_TDX_GUEST (1 << (X86_FEATURE_TDX_GUEST & 31)) #endif +#ifdef CONFIG_IPC_CLASSES +# define DISABLE_ITD 0 +#else +# define DISABLE_ITD (1 << (X86_FEATURE_ITD & 31)) +#endif + /* * Make sure to add features to the correct mask */ @@ -117,7 +123,7 @@ DISABLE_CALL_DEPTH_TRACKING) #define DISABLED_MASK12 0 #define DISABLED_MASK13 0 -#define DISABLED_MASK14 0 +#define DISABLED_MASK14 (DISABLE_ITD) #define DISABLED_MASK15 0 #define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UMIP| \ DISABLE_ENQCMD) diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-deps.c index d95221117129..277f157e067e 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -79,6 +79,7 @@ static const struct cpuid_dep cpuid_deps[] = { { X86_FEATURE_XFD, X86_FEATURE_XSAVES }, { X86_FEATURE_XFD, X86_FEATURE_XGETBV1 }, { X86_FEATURE_AMX_TILE, X86_FEATURE_XFD }, + { X86_FEATURE_ITD, X86_FEATURE_HFI }, {} }; From patchwork Mon Nov 28 13:20:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 26761 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5657514wrr; Mon, 28 Nov 2022 05:15:21 -0800 (PST) X-Google-Smtp-Source: AA0mqf5d8/55RmpMwLTYgIo6D6XgPDxX3yxKhCCy1SyACaaniZuVRVVyyjcXNxsXizLpRrcN/mud X-Received: by 2002:a63:4d0d:0:b0:477:14ea:cee6 with SMTP id a13-20020a634d0d000000b0047714eacee6mr26751940pgb.303.1669641320776; Mon, 28 Nov 2022 05:15:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669641320; cv=none; d=google.com; s=arc-20160816; b=eDB1/hWn1bkRDT44Nrn+XoGQW66+7dBx8JSUy4ZLvtxtjPzi6g9oDK/GBUnxaAKLY0 TdLTrZDCyiwYILtwM8ONGe6dKjVgWoUIeQBLdLwTgcu1M0YYJE4PzxIfiHggUrpvo36M 1kiPTyHJcDTlLuHygDosQ4oJxja/KITqiJVp9msu1WYBKRHTWWckeTYeCdGVW/nzffxw sPKWkz8RFNkNli5MW4zlepuMNhUkxsHZyZlPaLHkJhkQR+hhmpMlZz5aBiFcaYGIVCbj d3RV6snWaJaRpbVZQbuHHhnUSfR4ZQtkU1ZfWHF1HiziQq0m9MszK5x0CmKKrl5mqWDu xa0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=Q5g+SkK7SMS0wRfzaqwAP6IW6cEVIex09RzeAgTPI5k=; b=EVuvLxYzv1Mhd5PA71b1nGrWzDZF1xggLarcgICd5QIf+Wwz5aWMuYPRsD36m3eD4l uiBd6VOmn8mFEA96MPL/YUX9Oo2Xy0t3gu/8DWLA4UgNPJAm9YlFViMqNR3rP0agnG3A dV6a3gPMGpMo73sL6rrVNeAK9gq+QdoDIwk02Q0Eaw80UweAqMxE3Wv/K79vEU0RHxol yRbwbaYt9R2+CcJbS1RS5nfY8Au6QltC+zuDQ8npiECYqkMf6uDYLsvNwscWE3upt+gg XE8lfoIuXiFviU2eJJnq3wDMqqT0urO2+VY2Y/M5DDuPIZA7wSlEGUmPKk9YKkxlSV35 7wSg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Ku9+ujnj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Shankar" , Ben Segall , Daniel Bristot de Oliveira , Dietmar Eggemann , Len Brown , Mel Gorman , "Rafael J. Wysocki" , Srinivas Pandruvada , Steven Rostedt , Tim Chen , Valentin Schneider , x86@kernel.org, "Joel Fernandes (Google)" , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Ricardo Neri , "Tim C . Chen" Subject: [PATCH v2 13/22] thermal: intel: hfi: Update the IPC class of the current task Date: Mon, 28 Nov 2022 05:20:51 -0800 Message-Id: <20221128132100.30253-14-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> References: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750745817412737459?= X-GMAIL-MSGID: =?utf-8?q?1750745817412737459?= Use Intel Thread Director classification to update the IPC class of a task. Implement the needed scheduler interfaces. Cc: Ben Segall Cc: Daniel Bristot de Oliveira Cc: Dietmar Eggemann Cc: Joel Fernandes (Google) Cc: Len Brown Cc: Mel Gorman Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Steven Rostedt Cc: Tim C. Chen Cc: Valentin Schneider Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ricardo Neri --- Changes since v1: * Adjusted the result the classification of Intel Thread Director to start at class 1. Class 0 for the scheduler means that the task is unclassified. * Redefined union hfi_thread_feedback_char_msr to ensure all bit-fields are packed. (PeterZ) * Removed CONFIG_INTEL_THREAD_DIRECTOR. (PeterZ) * Shortened the names of the functions that implement IPC classes. * Removed argument smt_siblings_idle from intel_hfi_update_ipcc(). (PeterZ) --- arch/x86/include/asm/topology.h | 8 +++++++ drivers/thermal/intel/intel_hfi.c | 37 +++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h index 458c891a8273..cf46a3aea283 100644 --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -227,4 +227,12 @@ void init_freq_invariance_cppc(void); #define arch_init_invariance_cppc init_freq_invariance_cppc #endif +#if defined(CONFIG_IPC_CLASSES) && defined(CONFIG_INTEL_HFI_THERMAL) +int intel_hfi_has_ipc_classes(void); +void intel_hfi_update_ipcc(struct task_struct *curr); + +#define arch_has_ipc_classes intel_hfi_has_ipc_classes +#define arch_update_ipcc intel_hfi_update_ipcc +#endif /* defined(CONFIG_IPC_CLASSES) && defined(CONFIG_INTEL_HFI_THERMAL) */ + #endif /* _ASM_X86_TOPOLOGY_H */ diff --git a/drivers/thermal/intel/intel_hfi.c b/drivers/thermal/intel/intel_hfi.c index 56dba967849c..f85394b532a7 100644 --- a/drivers/thermal/intel/intel_hfi.c +++ b/drivers/thermal/intel/intel_hfi.c @@ -74,6 +74,17 @@ union cpuid6_edx { u32 full; }; +#ifdef CONFIG_IPC_CLASSES +union hfi_thread_feedback_char_msr { + struct { + u64 classid : 8; + u64 __reserved : 55; + u64 valid : 1; + } split; + u64 full; +}; +#endif + /** * struct hfi_cpu_data - HFI capabilities per CPU * @perf_cap: Performance capability @@ -176,6 +187,32 @@ static struct workqueue_struct *hfi_updates_wq; #ifdef CONFIG_IPC_CLASSES static int __percpu *hfi_ipcc_scores; +int intel_hfi_has_ipc_classes(void) +{ + return cpu_feature_enabled(X86_FEATURE_ITD); +} + +void intel_hfi_update_ipcc(struct task_struct *curr) +{ + union hfi_thread_feedback_char_msr msr; + + /* We should not be here if ITD is not supported. */ + if (!cpu_feature_enabled(X86_FEATURE_ITD)) { + pr_warn_once("task classification requested but not supported!"); + return; + } + + rdmsrl(MSR_IA32_HW_FEEDBACK_CHAR, msr.full); + if (!msr.split.valid) + return; + + /* + * 0 is a valid classification for Intel Thread Director. A scheduler + * IPCC class of 0 means that the task is unclassified. Adjust. + */ + curr->ipcc = msr.split.classid + 1; +} + static int alloc_hfi_ipcc_scores(void) { hfi_ipcc_scores = __alloc_percpu(sizeof(*hfi_ipcc_scores) * From patchwork Mon Nov 28 13:20:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 26765 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5658904wrr; Mon, 28 Nov 2022 05:17:06 -0800 (PST) X-Google-Smtp-Source: AA0mqf6B/7JJMw6QPA2lQaCAg3V3BvEn+bselhYXzauwE4mX8Mste/6D47PTPhpKqGuEnuGPy8PR X-Received: by 2002:a17:902:b416:b0:186:a22a:177e with SMTP id x22-20020a170902b41600b00186a22a177emr31374122plr.163.1669641425990; Mon, 28 Nov 2022 05:17:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669641425; cv=none; d=google.com; s=arc-20160816; b=EKDmt/Ox4wLhnRNCMZG4imSNt60tmzQqZUgCkjOTAD6KXvpyDEbweJmWM6mT2Rzt1M yOW5kX4yqMrC/HHCZ+RVFewKpJazjjp4JqDkGUGvpJG5N1WkenQpX49PnKqUyW/Gj2hJ fYpqpw72lo2276RBF9qRixmyD9lKMogjnkdWmTh98ccdbJFG5Kb92V5QBULCqwoAaxjF FErRP29SPFeeAsH3IpAQDqalGTSmLx9XCU0UJdmP3LjsVcFOXrjGI0D9bQ1KD+JsGB0c JN+86Xc+wR7WafNKYZz0O6MJB2WwW2Vu/gsGfC3xRX8g0nR/DnkLoNbhOTMQWT81Kes5 ma1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=yGj+KBTbhNAmuwPZNplpfsHW3hVpPO8ODSOYvBb9tpE=; b=QDcR1WIUcFsDqqejg6UuPeRZHrUZOxOjcppVJLgUo9jZ7g2uwCvF+NNmHzRm3t7YQR xidokZCodGC09XarVWMY80dMUvyn9NRxckV1HxjtIwYfLIXKcnrXlYZlwewPqbV7KeZO Q8ScsGu5GqbNUHy4tar1cR+7K+YtnwCc31nFBrfd6fuWyM9tHptn8yWsYQtwnsp91SDG X0kS06iFobVhohndbgjT9CS8TPhEQ5ry0Jz31gehPMQTcZr2rlMAcUrqcYH6emHB5/HX 9LudrmFhtwbxLGdeCjSroLQVADUvk9jrHxc4K4muae+SMlqFvtyvdH0BEEOPE5TqcCth mf9g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=ePLdhY1i; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Shankar" , Ben Segall , Daniel Bristot de Oliveira , Dietmar Eggemann , Len Brown , Mel Gorman , "Rafael J. Wysocki" , Srinivas Pandruvada , Steven Rostedt , Tim Chen , Valentin Schneider , x86@kernel.org, "Joel Fernandes (Google)" , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Ricardo Neri , "Tim C . Chen" Subject: [PATCH v2 14/22] thermal: intel: hfi: Report the IPC class score of a CPU Date: Mon, 28 Nov 2022 05:20:52 -0800 Message-Id: <20221128132100.30253-15-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> References: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750745927892329649?= X-GMAIL-MSGID: =?utf-8?q?1750745927892329649?= Implement the arch_get_ipcc_score() interface of the scheduler. Use the performance capabilities of the extended Hardware Feedback Interface table as the IPC score of a class of tasks when placed on a given CPU. Cc: Ben Segall Cc: Daniel Bristot de Oliveira Cc: Dietmar Eggemann Cc: Joel Fernandes (Google) Cc: Len Brown Cc: Mel Gorman Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Steven Rostedt Cc: Tim C. Chen Cc: Valentin Schneider Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ricardo Neri --- Changes since v1: * Adjusted the returned HFI class (which starts at 0) to match the scheduler IPCC class (which starts at 1). (PeterZ) * Used the new interface names. --- arch/x86/include/asm/topology.h | 2 ++ drivers/thermal/intel/intel_hfi.c | 27 +++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h index cf46a3aea283..0fae13058f01 100644 --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -230,9 +230,11 @@ void init_freq_invariance_cppc(void); #if defined(CONFIG_IPC_CLASSES) && defined(CONFIG_INTEL_HFI_THERMAL) int intel_hfi_has_ipc_classes(void); void intel_hfi_update_ipcc(struct task_struct *curr); +int intel_hfi_get_ipcc_score(unsigned short ipcc, int cpu); #define arch_has_ipc_classes intel_hfi_has_ipc_classes #define arch_update_ipcc intel_hfi_update_ipcc +#define arch_get_ipcc_score intel_hfi_get_ipcc_score #endif /* defined(CONFIG_IPC_CLASSES) && defined(CONFIG_INTEL_HFI_THERMAL) */ #endif /* _ASM_X86_TOPOLOGY_H */ diff --git a/drivers/thermal/intel/intel_hfi.c b/drivers/thermal/intel/intel_hfi.c index f85394b532a7..1f7b18198bd4 100644 --- a/drivers/thermal/intel/intel_hfi.c +++ b/drivers/thermal/intel/intel_hfi.c @@ -213,6 +213,33 @@ void intel_hfi_update_ipcc(struct task_struct *curr) curr->ipcc = msr.split.classid + 1; } +int intel_hfi_get_ipcc_score(unsigned short ipcc, int cpu) +{ + unsigned short hfi_class; + int *scores; + + if (cpu < 0 || cpu >= nr_cpu_ids) + return -EINVAL; + + if (ipcc == IPC_CLASS_UNCLASSIFIED) + return -EINVAL; + + /* + * Scheduler IPC classes start at 1. HFI classes start at 0. + * See note intel_hfi_update_ipcc(). + */ + hfi_class = ipcc - 1; + + if (hfi_class >= hfi_features.nr_classes) + return -EINVAL; + + scores = per_cpu_ptr(hfi_ipcc_scores, cpu); + if (!scores) + return -ENODEV; + + return READ_ONCE(scores[hfi_class]); +} + static int alloc_hfi_ipcc_scores(void) { hfi_ipcc_scores = __alloc_percpu(sizeof(*hfi_ipcc_scores) * From patchwork Mon Nov 28 13:20:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 26769 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5659930wrr; Mon, 28 Nov 2022 05:18:28 -0800 (PST) X-Google-Smtp-Source: AA0mqf6xjQrQ3EUhrQ53/iR0AyQ1wFz7ZcNTzw+7CBgAA/ehXHNewQ90XMYBtMfuYQ5e93TltwHz X-Received: by 2002:a17:906:924e:b0:782:2d3e:6340 with SMTP id c14-20020a170906924e00b007822d3e6340mr43608707ejx.234.1669641508095; Mon, 28 Nov 2022 05:18:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669641508; cv=none; d=google.com; s=arc-20160816; b=C/lw5TfqyN5XujfWu94nvWSfgcFELZcft0OY43PqwYlvFOzkNEaYSY/Jnhr+qhpmYG 1iw0R/3CrXe1erqoJgjUuXkLCICyY4o7sxTrJ88KOPNSJRf4gEbulQqd+8StGEleXAZg 4Nxvsd1f3yCDzMr0qy1J3czU5mUuCKzZDDr13/jv3gEb8HFUgP4u67FycgYFIPV9OCXC BLB8UC5qOKROVtl5hMOth7e7pNaUWA/hj/stsxCWaNWGwfpDQfainYMXWKSsVLl/O9yY dUDBDGfwIr45DX95XVUlHmWnqqVk4rnfxCDN9ARe3inHuk/bNwXrmST9uVhFJ+HsBkWB B2Cw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=Ada04ubPXLWlSUHTAsHzYqMgDnhmaYVx2WIce9Sb3nc=; b=b560Uj4uPc4koQf14wuxdQxY9cUVcTCBxDWQV7T/khHuyjguv3ALkbRsojmBhEDT7P XVG4EimNsvLEV4zdRO9uwbDcY2KxqsRBunCBPE2gvKeYVaKp8zKkNzRcXG8r/KQIql1n d3Zg8TjQ8tcsdiRrog6etATcuCUiKHuSC//jfVyC7RgV9gHnq0qxCtQ/QsNsbRgaAnkG tt+i8k0IELgAM4oirtUL06qKvDZmO2jXeZd4ClLgazG2XDltn5KA0d81Klq6o3tYrCmN CtvxvtaEIKqBrJzsiRVDyDyVRcVxEoxr4y4RAHpd/A/NqBCFIzSuL92pes4j2hT1gJ53 d+pA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=SQSfzVDV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Shankar" , Ben Segall , Daniel Bristot de Oliveira , Dietmar Eggemann , Len Brown , Mel Gorman , "Rafael J. Wysocki" , Srinivas Pandruvada , Steven Rostedt , Tim Chen , Valentin Schneider , x86@kernel.org, "Joel Fernandes (Google)" , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Ricardo Neri , "Tim C . Chen" Subject: [PATCH v2 15/22] thermal: intel: hfi: Define a default class for unclassified tasks Date: Mon, 28 Nov 2022 05:20:53 -0800 Message-Id: <20221128132100.30253-16-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> References: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750746013730811250?= X-GMAIL-MSGID: =?utf-8?q?1750746013730811250?= A task may be unclassified if it has been recently created, spend most of its lifetime sleeping, or hardware has not provided a classification. Most tasks will be eventually classified as scheduler's IPC class 1 (HFI class 0). This class corresponds to the capabilities in the legacy, classless, HFI table. IPC class 1 is a reasonable choice until hardware provides an actual classification. Meanwhile, the scheduler will place other tasks with higher scores on higher-performance CPUs. Cc: Ben Segall Cc: Daniel Bristot de Oliveira Cc: Dietmar Eggemann Cc: Len Brown Cc: Mel Gorman Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Steven Rostedt Cc: Tim C. Chen Cc: Valentin Schneider Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ricardo Neri --- Changes since v1: * Now the default class is 1. --- drivers/thermal/intel/intel_hfi.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/intel/intel_hfi.c b/drivers/thermal/intel/intel_hfi.c index 1f7b18198bd4..1b3fd704ae9a 100644 --- a/drivers/thermal/intel/intel_hfi.c +++ b/drivers/thermal/intel/intel_hfi.c @@ -187,6 +187,19 @@ static struct workqueue_struct *hfi_updates_wq; #ifdef CONFIG_IPC_CLASSES static int __percpu *hfi_ipcc_scores; +/* + * A task may be unclassified if it has been recently created, spend most of + * its lifetime sleeping, or hardware has not provided a classification. + * + * Most tasks will be classified as scheduler's IPC class 1 (HFI class 0) + * eventually. Meanwhile, the scheduler will place tasks of higher IPC score + * on higher-performance CPUs. + * + * IPC class 1 is a reasonable choice. It matches the performance capability + * of the legacy, classless, HFI table. + */ +#define HFI_UNCLASSIFIED_DEFAULT 1 + int intel_hfi_has_ipc_classes(void) { return cpu_feature_enabled(X86_FEATURE_ITD); @@ -222,7 +235,7 @@ int intel_hfi_get_ipcc_score(unsigned short ipcc, int cpu) return -EINVAL; if (ipcc == IPC_CLASS_UNCLASSIFIED) - return -EINVAL; + ipcc = HFI_UNCLASSIFIED_DEFAULT; /* * Scheduler IPC classes start at 1. HFI classes start at 0. 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id c3-20020a170903234300b0017f7faef235si13895097plh.148.2022.11.28.05.15.14; Mon, 28 Nov 2022 05:15:33 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=OzSNHXal; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231880AbiK1NOh (ORCPT + 99 others); Mon, 28 Nov 2022 08:14:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40118 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231567AbiK1NNk (ORCPT ); Mon, 28 Nov 2022 08:13:40 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A62372DCD; Mon, 28 Nov 2022 05:13:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669641219; x=1701177219; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=6edsBDhndxufd+3EwJXKfsHyRlYl4SM2zX6wq8H/56U=; b=OzSNHXalsHBm3jZdROfgz1/kUfd36h+u4RkznczD5jae31akEp2HLtoI GU+8kO2KdFMWV/HLxBZHebThJKcj54O8vgTIp6AIv3RjhGDVpcWya+MQ8 YujLMP2fiO6j9iWyTx3yhzoG49/IJ85wd8/UgYwGCOmpMzHVID0HzgDCO 6o7mGpKPv3+u7ia2XzUBjywjqdp4RZbUJG6Ur0LyrhvbAH9eoPw+g5uus gZcbH+OewhalZbqqqkwGIsd/OlZusxkcJDFvV8r0Qt/Yv1NQ7GIvDQGJQ N4kZyvB1OpvwGWwM0hwA9zun0qqIl7cz6tgPTlL07cHkHyEFYOH6a86WR g==; X-IronPort-AV: E=McAfee;i="6500,9779,10544"; a="401117214" X-IronPort-AV: E=Sophos;i="5.96,200,1665471600"; d="scan'208";a="401117214" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Nov 2022 05:13:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10544"; a="749381384" X-IronPort-AV: E=Sophos;i="5.96,200,1665471600"; d="scan'208";a="749381384" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga002.fm.intel.com with ESMTP; 28 Nov 2022 05:13:35 -0800 From: Ricardo Neri To: "Peter Zijlstra (Intel)" , Juri Lelli , Vincent Guittot Cc: Ricardo Neri , "Ravi V. Shankar" , Ben Segall , Daniel Bristot de Oliveira , Dietmar Eggemann , Len Brown , Mel Gorman , "Rafael J. Wysocki" , Srinivas Pandruvada , Steven Rostedt , Tim Chen , Valentin Schneider , x86@kernel.org, "Joel Fernandes (Google)" , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Ricardo Neri , "Tim C . Chen" Subject: [PATCH v2 16/22] thermal: intel: hfi: Enable the Intel Thread Director Date: Mon, 28 Nov 2022 05:20:54 -0800 Message-Id: <20221128132100.30253-17-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> References: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750745831049235077?= X-GMAIL-MSGID: =?utf-8?q?1750745831049235077?= Enable Intel Thread Director from the CPU hotplug callback: globally from CPU0 and then enable the thread-classification hardware in each logical processor individually. Also, initialize the number of classes supported. Cc: Ben Segall Cc: Daniel Bristot de Oliveira Cc: Dietmar Eggemann Cc: Joel Fernandes (Google) Cc: Len Brown Cc: Mel Gorman Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Steven Rostedt Cc: Tim C. Chen Cc: Valentin Schneider Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ricardo Neri --- Changes since v1: * None --- arch/x86/include/asm/msr-index.h | 2 ++ drivers/thermal/intel/intel_hfi.c | 30 ++++++++++++++++++++++++++++-- 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 37ff47552bcb..96303330223b 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1075,6 +1075,8 @@ /* Hardware Feedback Interface */ #define MSR_IA32_HW_FEEDBACK_PTR 0x17d0 #define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1 +#define MSR_IA32_HW_FEEDBACK_THREAD_CONFIG 0x17d4 +#define MSR_IA32_HW_FEEDBACK_CHAR 0x17d2 /* x2APIC locked status */ #define MSR_IA32_XAPIC_DISABLE_STATUS 0xBD diff --git a/drivers/thermal/intel/intel_hfi.c b/drivers/thermal/intel/intel_hfi.c index 1b3fd704ae9a..8287bfd7d6b6 100644 --- a/drivers/thermal/intel/intel_hfi.c +++ b/drivers/thermal/intel/intel_hfi.c @@ -50,6 +50,8 @@ /* Hardware Feedback Interface MSR configuration bits */ #define HW_FEEDBACK_PTR_VALID_BIT BIT(0) #define HW_FEEDBACK_CONFIG_HFI_ENABLE_BIT BIT(0) +#define HW_FEEDBACK_CONFIG_ITD_ENABLE_BIT BIT(1) +#define HW_FEEDBACK_THREAD_CONFIG_ENABLE_BIT BIT(0) /* CPUID detection and enumeration definitions for HFI */ @@ -74,6 +76,15 @@ union cpuid6_edx { u32 full; }; +union cpuid6_ecx { + struct { + u32 dont_care0:8; + u32 nr_classes:8; + u32 dont_care1:16; + } split; + u32 full; +}; + #ifdef CONFIG_IPC_CLASSES union hfi_thread_feedback_char_msr { struct { @@ -495,6 +506,11 @@ void intel_hfi_online(unsigned int cpu) init_hfi_cpu_index(info); + if (cpu_feature_enabled(X86_FEATURE_ITD)) { + msr_val = HW_FEEDBACK_THREAD_CONFIG_ENABLE_BIT; + wrmsrl(MSR_IA32_HW_FEEDBACK_THREAD_CONFIG, msr_val); + } + /* * Now check if the HFI instance of the package/die of @cpu has been * initialized (by checking its header). In such case, all we have to @@ -550,6 +566,10 @@ void intel_hfi_online(unsigned int cpu) */ rdmsrl(MSR_IA32_HW_FEEDBACK_CONFIG, msr_val); msr_val |= HW_FEEDBACK_CONFIG_HFI_ENABLE_BIT; + + if (cpu_feature_enabled(X86_FEATURE_ITD)) + msr_val |= HW_FEEDBACK_CONFIG_ITD_ENABLE_BIT; + wrmsrl(MSR_IA32_HW_FEEDBACK_CONFIG, msr_val); unlock: @@ -629,8 +649,14 @@ static __init int hfi_parse_features(void) */ hfi_features.class_stride = nr_capabilities; - /* For now, use only one class of the HFI table */ - hfi_features.nr_classes = 1; + if (cpu_feature_enabled(X86_FEATURE_ITD)) { + union cpuid6_ecx ecx; + + ecx.full = cpuid_ecx(CPUID_HFI_LEAF); + hfi_features.nr_classes = ecx.split.nr_classes; + } else { + hfi_features.nr_classes = 1; + } /* * The header contains change indications for each supported feature. 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Shankar" , Ben Segall , Daniel Bristot de Oliveira , Dietmar Eggemann , Len Brown , Mel Gorman , "Rafael J. Wysocki" , Srinivas Pandruvada , Steven Rostedt , Tim Chen , Valentin Schneider , x86@kernel.org, "Joel Fernandes (Google)" , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Ricardo Neri , "Tim C . Chen" Subject: [PATCH v2 17/22] sched/task_struct: Add helpers for IPC classification Date: Mon, 28 Nov 2022 05:20:55 -0800 Message-Id: <20221128132100.30253-18-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> References: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750745960914471023?= X-GMAIL-MSGID: =?utf-8?q?1750745960914471023?= The unprocessed classification that hardware provides for a task may not be usable by the scheduler: the classification may change too frequently or architectures may want to consider extra factors. For instance, some processors with Intel Thread Director need to consider the state of the SMT siblings of a core. Provide per-task helper variables that architectures can use to post- process the classification that hardware provides. Cc: Ben Segall Cc: Daniel Bristot de Oliveira Cc: Dietmar Eggemann Cc: Joel Fernandes (Google) Cc: Len Brown Cc: Mel Gorman Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Steven Rostedt Cc: Tim C. Chen Cc: Valentin Schneider Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ricardo Neri --- Changes since v1: * Used bit-fields to fit all the IPC class data in 4 bytes. (PeterZ) * Shortened names of the helpers. * Renamed helpers with the ipcc_ prefix. * Reworded commit message for clarity --- include/linux/sched.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/include/linux/sched.h b/include/linux/sched.h index ddabc7449edd..8a99aa316c37 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -1532,7 +1532,17 @@ struct task_struct { * A hardware-defined classification of task based on the number * of instructions per cycle. */ - unsigned int ipcc; + unsigned int ipcc : 9; + /* + * A candidate classification that arch-specific implementations + * qualify for correctness. + */ + unsigned int ipcc_tmp : 9; + /* + * Counter to filter out transient the candidate classification + * of a task + */ + unsigned int ipcc_cntr : 14; #endif /* From patchwork Mon Nov 28 13:20:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 26771 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5660354wrr; Mon, 28 Nov 2022 05:19:07 -0800 (PST) X-Google-Smtp-Source: AA0mqf6Qalm5MdUTRn4oqYIlLxfE1JP7LseUR8/0xEgzlpFECO68SwmlW4RarYlAVbQGLsCbderV X-Received: by 2002:a17:906:369b:b0:78d:34a:f466 with SMTP id a27-20020a170906369b00b0078d034af466mr43403451ejc.162.1669641547424; Mon, 28 Nov 2022 05:19:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669641547; cv=none; d=google.com; s=arc-20160816; b=MtvpJDzIPQ+EXBemUzTbzSb48O6QrO/S1EgtBOe65Seq6tP5pr/2GswSFXWVz36fmI ck9s5DM8C1vLN+WhrEhpVO2mejRpV8oUU1XH+DTcMMjgLNNTE83p+2MYBXFAHPZs1DK8 u8a+2U//TYWPoCLbkMhRLTJIKvljYW8ROgM0NoA62MDs1gSmeFJHduAwvGeirQdVU1yx UBLKEPtDlOa/ljspQnWBYhOVWar/zXTKA15KAXwZFWHCmJT8qJuV5GvpZEbw3ZZtQItC ArNBE9zkkdkbbGoXH2cpTs74JbLo8BwTsiZ9u3H9r0TCCWysf2ndInpNkdvOf3fhVLhR pehg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=l0Og+97tjoyIeAXEmLPaKdFxMadZY/7w1s9wmvaIQpI=; b=ZwPOzV04RTnJ/Uh5JTRuAPO9swlZ7njEQaoSMBfR85jtGcxqzMvQElrNyjXL3dernz qFE4svp78CPlDEhDXg2ajzac1Don58zu95NgFAJDXAChWrZTprzYst4nbeKotYJ/BIcv JrWbz40jDs259O6dEfXVD0mPswaYWm4M0MSpfVRoIRg8B1mff0BfcJGVMs46sZBGfP/0 9PxlVBMN1vZ7wxt87HdLYHz+VowlR8zmc6zqVvU1lGwhxXytRArtrI58jsjRCJ4unmgd Ei7tbbavbF4kl3yRPk3hkvpPekhBFU4Gw6KsMgkPTwY/OOQuF/kLhbJA0NY5E1ogkf8l x98Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=gNCDRFyd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id z3-20020a1709067e4300b007b9eeb4879asi7705459ejr.419.2022.11.28.05.18.42; Mon, 28 Nov 2022 05:19:07 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=gNCDRFyd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231700AbiK1NOz (ORCPT + 99 others); Mon, 28 Nov 2022 08:14:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231607AbiK1NNl (ORCPT ); Mon, 28 Nov 2022 08:13:41 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C07FE1CFC2; Mon, 28 Nov 2022 05:13:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669641220; x=1701177220; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=KWVB7nlsf20aLmkJw9PMc9fnASyxtCkpqLu/IPZ9sIY=; b=gNCDRFydNHxGrZ32vgvgI8pBRG7LjpNHtdZzMzyuZ8fXB50Uwp9lS3kA zRoRQPUFn5de46HRr7ZQ0XtAZjS5JTFIKMxG6YaJQ8yhdeAb692U3a5lz ddTIozmiUIT/bUIamOMSsrzn2+clHiq2Bbf27x66B0kySRWFuc+HrSSI3 AUQXSVS4riThDleOtdzqdRFCp1EU8JYHP/JptWOUl42lRUMyceLqsS+cS WlehERQ4rOdZkTyepAbsEHN1ulF3wM+Q7NBexfVzod03maujcwqaCd/fT MQl2rA2qzsFcYqON4Vzc9K56Rj4InE42wLT0QjnYCqvOH+kp1+kp0uZ6x A==; X-IronPort-AV: E=McAfee;i="6500,9779,10544"; a="401117238" X-IronPort-AV: E=Sophos;i="5.96,200,1665471600"; d="scan'208";a="401117238" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Nov 2022 05:13:36 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10544"; a="749381390" X-IronPort-AV: E=Sophos;i="5.96,200,1665471600"; d="scan'208";a="749381390" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga002.fm.intel.com with ESMTP; 28 Nov 2022 05:13:35 -0800 From: Ricardo Neri To: "Peter Zijlstra (Intel)" , Juri Lelli , Vincent Guittot Cc: Ricardo Neri , "Ravi V. Shankar" , Ben Segall , Daniel Bristot de Oliveira , Dietmar Eggemann , Len Brown , Mel Gorman , "Rafael J. Wysocki" , Srinivas Pandruvada , Steven Rostedt , Tim Chen , Valentin Schneider , x86@kernel.org, "Joel Fernandes (Google)" , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Ricardo Neri , "Tim C . Chen" Subject: [PATCH v2 18/22] sched/core: Initialize helpers of task classification Date: Mon, 28 Nov 2022 05:20:56 -0800 Message-Id: <20221128132100.30253-19-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> References: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750746055220853933?= X-GMAIL-MSGID: =?utf-8?q?1750746055220853933?= Just as tasks start life unclassified, initialize the classification auxiliar variables. Cc: Ben Segall Cc: Daniel Bristot de Oliveira Cc: Dietmar Eggemann Cc: Joel Fernandes (Google) Cc: Len Brown Cc: Mel Gorman Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Steven Rostedt Cc: Tim C. Chen Cc: Valentin Schneider Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ricardo Neri --- Changes since v1: * None --- kernel/sched/core.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/kernel/sched/core.c b/kernel/sched/core.c index 2cd409536b72..0406b07c51a0 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -4374,6 +4374,8 @@ static void __sched_fork(unsigned long clone_flags, struct task_struct *p) p->se.vruntime = 0; #ifdef CONFIG_IPC_CLASSES p->ipcc = IPC_CLASS_UNCLASSIFIED; + p->ipcc_tmp = IPC_CLASS_UNCLASSIFIED; + p->ipcc_cntr = 0; #endif INIT_LIST_HEAD(&p->se.group_node); From patchwork Mon Nov 28 13:20:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 26764 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5658637wrr; Mon, 28 Nov 2022 05:16:46 -0800 (PST) X-Google-Smtp-Source: AA0mqf72ThEUsJ4Bzc+d8z6Dg9ouVLR6/nwtvxyt28121uO6kZhkUt2nqYpuJKD8ddGrHuDNbEMo X-Received: by 2002:a17:902:a514:b0:189:97c3:6382 with SMTP id s20-20020a170902a51400b0018997c36382mr60142plq.168.1669641405799; Mon, 28 Nov 2022 05:16:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669641405; cv=none; d=google.com; s=arc-20160816; b=rQtGYjFVLACpE0Gp8Nm88m3SdVYQw6MJ8sbZX54kE/JZshGsUsmqMHDrToPjKUxlSf Y+/HMjjajSwa/LE48ZMQtvsK5et4um87l1QYFvSv26M/27jFQaBKglVfVMsXpoQ6rh2b vIKA17+RY2LL+y/nDJ1eNOspINWev7r99FM/LqfQ0Anp0yaSv1uhcLj2VVz0iAnVchpW jZQQeZ0Ku/rPG8ggkuV02UdHR6VoObRtt2cvYCqmbsfIBxc28rs+X936gsSN/gxYzIeU CC/Bd7rCj66dYAfk3Z1KkAuileeqGLofwkF8Sb+zZcTPlIm8lQ0FtuUKTB6vd1//FLtM gOAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=VjaTWZV01qae2eSB11xOlwaKTA3Es1Na+6uJqUtfh6o=; b=nckOs4wy61dnuNliPdOtncxdtOFG00S8Pk1T4yrZcuZtpRSFchVT5o2jqvMQ/AZoOk pTRKmRBb4d/FWN29dx0ObnVzR7bdZAgOuflLgGd+U9/an+fpI10PJxGa/xaaZrHWoc5D Sh6YAZhZLGA4sF6zVN8K016D3VRgMe4jTmf0qlczhJ9TboV6NUh65pgJGDwv+Aluz6id ctbAZpzzj6s/0YDKRpEYvSJTdBKyZcMQ9rR/YHprL+3iG8k/O2fu/n54GjskywALWr53 vgq6CdCMVxwGU4r/DsfYUXqHHkMyz2NqMkZKW7LWjx4zxO+QZAgLpg8YCL9E6Gsqi9Ux w9oA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=amtFdyXM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id p8-20020a170902b08800b00189244a7217si10985911plr.106.2022.11.28.05.16.11; Mon, 28 Nov 2022 05:16:45 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=amtFdyXM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231895AbiK1NOv (ORCPT + 99 others); Mon, 28 Nov 2022 08:14:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39878 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231258AbiK1NNl (ORCPT ); Mon, 28 Nov 2022 08:13:41 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C06A41CB37; Mon, 28 Nov 2022 05:13:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669641220; x=1701177220; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=6bnvjZwJXP3wVx/GzfxHDbk1nNW034G+XQZFyKkDwVI=; b=amtFdyXMYRlgqZ6C2IJoEYMFqv7J+hI5ztwU8lFKkAn6ZsCKsJ7iJI31 76gQv550LresMwB59yQfho+lV3JuSd2+VWD4eJlgGxhMGnjP1+ltI6CoZ ESJ+Nb6v0BM5B1yigVQLtxul6plcd7magRzbu3XQMIJBU3odV4uBFgs6T w9zb7VflXdnNwYfJExNjRi58n4bQbEXk6P5rq/G7ALyoNBs/v2Hv6YTW6 juTbRSK8QOCS04SY/Hv41JXvRvCvAicaYTn1kgQfGh+szSCXm7r4ugsJn Rd5DnlCWbL0Ziwn4vXFUqIfNLS7gVzmWli7LSp5SKo55Gm9aFnuY2xz1m Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10544"; a="401117249" X-IronPort-AV: E=Sophos;i="5.96,200,1665471600"; d="scan'208";a="401117249" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Nov 2022 05:13:36 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10544"; a="749381393" X-IronPort-AV: E=Sophos;i="5.96,200,1665471600"; d="scan'208";a="749381393" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga002.fm.intel.com with ESMTP; 28 Nov 2022 05:13:35 -0800 From: Ricardo Neri To: "Peter Zijlstra (Intel)" , Juri Lelli , Vincent Guittot Cc: Ricardo Neri , "Ravi V. Shankar" , Ben Segall , Daniel Bristot de Oliveira , Dietmar Eggemann , Len Brown , Mel Gorman , "Rafael J. Wysocki" , Srinivas Pandruvada , Steven Rostedt , Tim Chen , Valentin Schneider , x86@kernel.org, "Joel Fernandes (Google)" , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Ricardo Neri , "Tim C . Chen" Subject: [PATCH v2 19/22] thermal: intel: hfi: Implement model-specific checks for task classification Date: Mon, 28 Nov 2022 05:20:57 -0800 Message-Id: <20221128132100.30253-20-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> References: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750745906479188690?= X-GMAIL-MSGID: =?utf-8?q?1750745906479188690?= In Alderlake and Raptorlake, the result of thread classification is more accurate when only one SMT sibling is busy. Classification results for class 2 and 3 that are always reliable. To avoid unnecessary migrations, only update the class of a task if it has been the same during 4 consecutive ticks. Cc: Ben Segall Cc: Daniel Bristot de Oliveira Cc: Dietmar Eggemann Cc: Joel Fernandes (Google) Cc: Len Brown Cc: Mel Gorman Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Steven Rostedt Cc: Tim C. Chen Cc: Valentin Schneider Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ricardo Neri --- Changes since v1: * Adjusted the result the classification of Intel Thread Director to start at class 1. Class 0 for the scheduler means that the task is unclassified. * Used the new names of the IPC classes members in task_struct. * Reworked helper functions to use sched_smt_siblings_idle() to query the idle state of the SMT siblings of a CPU. --- drivers/thermal/intel/intel_hfi.c | 60 ++++++++++++++++++++++++++++++- 1 file changed, 59 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/intel/intel_hfi.c b/drivers/thermal/intel/intel_hfi.c index 8287bfd7d6b6..a9ae09036909 100644 --- a/drivers/thermal/intel/intel_hfi.c +++ b/drivers/thermal/intel/intel_hfi.c @@ -40,6 +40,7 @@ #include #include +#include #include "../thermal_core.h" #include "intel_hfi.h" @@ -216,9 +217,64 @@ int intel_hfi_has_ipc_classes(void) return cpu_feature_enabled(X86_FEATURE_ITD); } +#define CLASS_DEBOUNCER_SKIPS 4 + +/** + * debounce_and_update_class() - Process and update a task's classification + * + * @p: The task of which the classification will be updated + * @new_ipcc: The new IPC classification + * + * Update the classification of @p with the new value that hardware provides. + * Only update the classification of @p if it has been the same during + * CLASS_DEBOUNCER_SKIPS consecutive ticks. + */ +static void debounce_and_update_class(struct task_struct *p, u8 new_ipcc) +{ + u16 debounce_skip; + + /* The class of @p changed, only restart the debounce counter. */ + if (p->ipcc_tmp != new_ipcc) { + p->ipcc_cntr = 1; + goto out; + } + + /* + * The class of @p did not change. Update it if it has been the same + * for CLASS_DEBOUNCER_SKIPS user ticks. + */ + debounce_skip = p->ipcc_cntr + 1; + if (debounce_skip < CLASS_DEBOUNCER_SKIPS) + p->ipcc_cntr++; + else + p->ipcc = new_ipcc; + +out: + p->ipcc_tmp = new_ipcc; +} + +static bool classification_is_accurate(u8 hfi_class, bool smt_siblings_idle) +{ + switch (boot_cpu_data.x86_model) { + case INTEL_FAM6_ALDERLAKE: + case INTEL_FAM6_ALDERLAKE_L: + case INTEL_FAM6_RAPTORLAKE: + case INTEL_FAM6_RAPTORLAKE_P: + case INTEL_FAM6_RAPTORLAKE_S: + if (hfi_class == 3 || hfi_class == 2 || smt_siblings_idle) + return true; + + return false; + + default: + return true; + } +} + void intel_hfi_update_ipcc(struct task_struct *curr) { union hfi_thread_feedback_char_msr msr; + bool idle; /* We should not be here if ITD is not supported. */ if (!cpu_feature_enabled(X86_FEATURE_ITD)) { @@ -234,7 +290,9 @@ void intel_hfi_update_ipcc(struct task_struct *curr) * 0 is a valid classification for Intel Thread Director. A scheduler * IPCC class of 0 means that the task is unclassified. Adjust. */ - curr->ipcc = msr.split.classid + 1; + idle = sched_smt_siblings_idle(task_cpu(curr)); + if (classification_is_accurate(msr.split.classid, idle)) + debounce_and_update_class(curr, msr.split.classid + 1); } int intel_hfi_get_ipcc_score(unsigned short ipcc, int cpu) From patchwork Mon Nov 28 13:20:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 26767 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5659692wrr; Mon, 28 Nov 2022 05:18:09 -0800 (PST) X-Google-Smtp-Source: AA0mqf4bPQjz3BJyP+gosi2sB9Xj4ZnNKzfs5gV8rDLxnzQuBQL0k4dYh49dTYzq9TIp+OoiW3pQ X-Received: by 2002:a17:90b:3748:b0:218:e0bf:9385 with SMTP id ne8-20020a17090b374800b00218e0bf9385mr27703810pjb.208.1669641488923; Mon, 28 Nov 2022 05:18:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669641488; cv=none; d=google.com; s=arc-20160816; b=TzKaAsRpPAK5uoskg+EroC4a4FJVS5/A8sxCV6q4WZ1ztcApemUFF56blUGu5mP+Jq DShUf81kA3II57TVJJttcduq0QkKK78sEdUoX2LA/s3hqCrHrCdlfLCxxSgpHYkx/MVt mHCYIAicJ1PhS7bydf/1BGcKYK+GCZ9QpUyZoDgQ1C6loSttD7cR7eFphilNLnE7MiZj RUCKF3cHNp3RHgrclqUkswRgvEtOCFSzBPvxOoi7c9d9aufuQRX+8X8BKyRSKesk9PIa Y9oe92y4RKun9DnVoLv8AbCS2DRPLmhUhgKzAUHmvRlyX86swIK432Vvqs38T4h9teIv Fzow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=jfo3kb7/aroJhndJuKNk5BK4ugNx5UrtHD2JFuDdRJI=; b=Z56DzO58Ruf6XSi+hFx3fdXjgV6OH+Kqp6SxCOlC/yhbXU/RNK/dMaq+v97MsYddsK mKOQrlKbfSHw104luo8GqCZi3PQ1r+lybOIIrfBHl4EkwOYfx7g3qMkj9B0iVij14Qk3 /SRglAAcFiPB7UdK1myvPTvGRhOajuYDFcPCnier3j3mrDawcM1FtmdMN3M7fYEbmLIr h4A8Ehy0hieybyAo6RPBWpqIiNGuI9gBFa46vxJPzdYwOvWoAAHF82kp/MquWW1BXXCa nxeQC/v/fkMqI61pkU08puIMiRmDNqtaQeXj9Kd/wiVt2rJR+nuQdrTmdPriJvaroFsi MkWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=d1X0izXQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Shankar" , Ben Segall , Daniel Bristot de Oliveira , Dietmar Eggemann , Len Brown , Mel Gorman , "Rafael J. Wysocki" , Srinivas Pandruvada , Steven Rostedt , Tim Chen , Valentin Schneider , x86@kernel.org, "Joel Fernandes (Google)" , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Ricardo Neri , "Tim C . Chen" Subject: [PATCH v2 20/22] x86/cpufeatures: Add feature bit for HRESET Date: Mon, 28 Nov 2022 05:20:58 -0800 Message-Id: <20221128132100.30253-21-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> References: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750745994030889344?= X-GMAIL-MSGID: =?utf-8?q?1750745994030889344?= The HRESET instruction prevents the classification of the current task from influencing the classification of the next task when running serially on the same logical processor. Cc: Ben Segall Cc: Daniel Bristot de Oliveira Cc: Dietmar Eggemann Cc: Joel Fernandes (Google) Cc: Len Brown Cc: Mel Gorman Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Steven Rostedt Cc: Tim C. Chen Cc: Valentin Schneider Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ricardo Neri --- Changes since v1: * None --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/msr-index.h | 4 +++- arch/x86/kernel/cpu/scattered.c | 1 + 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 80b2beafc81e..281a7c861b8d 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -308,6 +308,7 @@ #define X86_FEATURE_CALL_DEPTH (11*32+19) /* "" Call depth tracking for RSB stuffing */ #define X86_FEATURE_MSR_TSX_CTRL (11*32+20) /* "" MSR IA32_TSX_CTRL (Intel) implemented */ +#define X86_FEATURE_HRESET (11*32+21) /* Hardware history reset instruction */ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 96303330223b..7a3ff73164bd 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1078,6 +1078,9 @@ #define MSR_IA32_HW_FEEDBACK_THREAD_CONFIG 0x17d4 #define MSR_IA32_HW_FEEDBACK_CHAR 0x17d2 +/* Hardware History Reset */ +#define MSR_IA32_HW_HRESET_ENABLE 0x17da + /* x2APIC locked status */ #define MSR_IA32_XAPIC_DISABLE_STATUS 0xBD #define LEGACY_XAPIC_DISABLED BIT(0) /* @@ -1085,5 +1088,4 @@ * disabling x2APIC will cause * a #GP */ - #endif /* _ASM_X86_MSR_INDEX_H */ diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index f53944fb8f7f..66bc5713644d 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -28,6 +28,7 @@ static const struct cpuid_bit cpuid_bits[] = { { X86_FEATURE_EPB, CPUID_ECX, 3, 0x00000006, 0 }, { X86_FEATURE_INTEL_PPIN, CPUID_EBX, 0, 0x00000007, 1 }, { X86_FEATURE_RRSBA_CTRL, CPUID_EDX, 2, 0x00000007, 2 }, + { X86_FEATURE_HRESET, CPUID_EAX, 22, 0x00000007, 1 }, { X86_FEATURE_CQM_LLC, CPUID_EDX, 1, 0x0000000f, 0 }, { X86_FEATURE_CQM_OCCUP_LLC, CPUID_EDX, 0, 0x0000000f, 1 }, { X86_FEATURE_CQM_MBM_TOTAL, CPUID_EDX, 1, 0x0000000f, 1 }, From patchwork Mon Nov 28 13:20:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 26768 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5659817wrr; Mon, 28 Nov 2022 05:18:19 -0800 (PST) X-Google-Smtp-Source: AA0mqf7h5wO9pk2yrLN4Rvzb1QWayJirFxZhc+AjX1CqzzzShOVB040LWKmu5DS9C8fkkU5JFfgO X-Received: by 2002:a63:1054:0:b0:42b:9219:d14e with SMTP id 20-20020a631054000000b0042b9219d14emr27803574pgq.176.1669641498898; Mon, 28 Nov 2022 05:18:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669641498; cv=none; d=google.com; s=arc-20160816; b=sUDMm+SO0fuW+sIvB5ST3WZJHALsvEhfV8kPJQbZDcIxLCMsoiZb3Vb0Lx5DvQP55q 2eikbn2FQ5Gsmhos6Okx3Tn93gN/rcBoU+PGPa7LYCy9UFlg7OLIwZoWXlIY3rbq6YZQ anvG/1ZelkbPLxTLQsU+Up8H/0tAa13AZYA8wXuRF9Z1HpYNO8u1iv81dX/qEjSvn8zQ WLQvMMpN9wrBKzU0ZpwFIjTO4ZDvM2S/It43NpsnWKVsNzJKzfg8i+wOdj0TmxvdThij Du4ivxHodYp7ItpoMKGiI6OH1eMzLqHzmWErb45SrffEd10Asu+ssofGFeY/IsXzl2lG xS+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=ZHF9kcgHoGtOkitgsN4qZ3DjWfkzZA3mpRnXIQCo69s=; b=na/JsQUqYAE8uTGq/4y7wdfoLdY2j+4ZqxqtPpelyVTl3E3mKPrVjNmZqPxkXEzXpk P6fH56LpnQ3Xn2/XjwYfkASeHIf+VD8QXUFEjymn59ygqFKqQ2prJIjgv4y9ENn/i+Ab o3ejYpifqQEbEEnRHcC8BZxoJfWGIAzIgGEQ8r/i9VPWb7jZuiibYD4KbtwFPoCCIA02 azTxcp8jaImNji58QpUCK58eh/3fqpFQNqIoTO/NE5HRa7jRPdvuuEJH1m0xX9Ijd/yl sEi5p7mVXrtO5TnpdQ6pvD9j14qQi1RAReYvUu0WkxBowLC1tQ72h0oM4L8KDaI3saVX ctAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="E/Bedru4"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Shankar" , Ben Segall , Daniel Bristot de Oliveira , Dietmar Eggemann , Len Brown , Mel Gorman , "Rafael J. Wysocki" , Srinivas Pandruvada , Steven Rostedt , Tim Chen , Valentin Schneider , x86@kernel.org, "Joel Fernandes (Google)" , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Ricardo Neri , "Tim C . Chen" Subject: [PATCH v2 21/22] x86/hreset: Configure history reset Date: Mon, 28 Nov 2022 05:20:59 -0800 Message-Id: <20221128132100.30253-22-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> References: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750746004159358047?= X-GMAIL-MSGID: =?utf-8?q?1750746004159358047?= Configure the MSR that controls the behavior of HRESET on each logical processor. Cc: Ben Segall Cc: Daniel Bristot de Oliveira Cc: Dietmar Eggemann Cc: Joel Fernandes (Google) Cc: Len Brown Cc: Mel Gorman Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Steven Rostedt Cc: Tim C. Chen Cc: Valentin Schneider Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ricardo Neri --- Changes since v1: * Marked hardware_history_features as __ro_after_init instead of __read_mostly. (PeterZ) --- arch/x86/kernel/cpu/common.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 73cc546e024d..f8630da2a6dd 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -412,6 +412,26 @@ static __always_inline void setup_umip(struct cpuinfo_x86 *c) cr4_clear_bits(X86_CR4_UMIP); } +static u32 hardware_history_features __ro_after_init; + +static __always_inline void setup_hreset(struct cpuinfo_x86 *c) +{ + if (!cpu_feature_enabled(X86_FEATURE_HRESET)) + return; + + /* + * Use on all CPUs the hardware history features that the boot + * CPU supports. + */ + if (c == &boot_cpu_data) + hardware_history_features = cpuid_ebx(0x20); + + if (!hardware_history_features) + return; + + wrmsrl(MSR_IA32_HW_HRESET_ENABLE, hardware_history_features); +} + /* These bits should not change their value after CPU init is finished. */ static const unsigned long cr4_pinned_mask = X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | @@ -1844,10 +1864,11 @@ static void identify_cpu(struct cpuinfo_x86 *c) /* Disable the PN if appropriate */ squash_the_stupid_serial_number(c); - /* Set up SMEP/SMAP/UMIP */ + /* Set up SMEP/SMAP/UMIP/HRESET */ setup_smep(c); setup_smap(c); setup_umip(c); + setup_hreset(c); /* Enable FSGSBASE instructions if available. */ if (cpu_has(c, X86_FEATURE_FSGSBASE)) { From patchwork Mon Nov 28 13:21:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 26770 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5660174wrr; Mon, 28 Nov 2022 05:18:51 -0800 (PST) X-Google-Smtp-Source: AA0mqf6l92f3GWdW43gUbbAollfSWCU/rcZDBs3gODL2AkET989vmrrI0TjeeiLvuEwKI5PcgsmL X-Received: by 2002:a17:902:eb88:b0:189:8d87:efac with SMTP id q8-20020a170902eb8800b001898d87efacmr4082252plg.33.1669641530850; Mon, 28 Nov 2022 05:18:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669641530; cv=none; d=google.com; s=arc-20160816; b=lu2OUaZB4qFT5ZCcRzGRZ03deDQj5jgLLwVTDLbn+Y+q5bagLndRdytc8W9xCmcE+z WVsBz1e9wGcetWlLFVYKcgopgNZRiyAyQLlACXMaPQ1PKT+7RVclX2DIlT0cPeKgJS0O V8AzBe8MMcuTWuMOfG2MXZOw7s2Wp90ctFl7ioWy/2pHVCvNBb4TbTFAkdVe62OB46TS vDEUQKHHgbhzpgXcjrlKzjm+Ip9KJ4/DUJGV4cPsLzSqHlpjXCjJcDubvErlHcDKGXgP ifyRwGTxG2TZUPetjg6t0VzP1LdwzeqmQ+osZaNI0XNH/xTSEYDyWiAbAXoR3jL2NJys no/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=LaicvLSMhBIQPRdH5aGWWF+tJcqfMdq6kwq6z+4z+9o=; b=mNYhmjbotborp4BT9ZD7ZZNsg43lVRFcLqmAhfljsC+TXvvQ5oM6dITfQpODmVakSS pQ5poaWphByFL04aTcp1DUY8HWeheGCUJgj24rMXTuOIlVmY4R/aIRNOisyCqvNk8E6V sO1E6vZ2f/Lewnhy6N5xZkhvszfLf2IRYnzy5m4hxLCqdWJuO4z6pwmsEPPjX6QChSae BlDXRJfh3s2tA3RPJCKHUC99rR7gi6u7Wvv8j53c+8DzNbK1Sjv0FZoWAORwLuwN04m4 DHnq6WEDS0RyTyoWI4WVszNsxqk9VnHv71vU22753x3tzvYBWEogTJfmcEePLLzNPiZK LYvA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Dgkl7iS7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Shankar" , Ben Segall , Daniel Bristot de Oliveira , Dietmar Eggemann , Len Brown , Mel Gorman , "Rafael J. Wysocki" , Srinivas Pandruvada , Steven Rostedt , Tim Chen , Valentin Schneider , x86@kernel.org, "Joel Fernandes (Google)" , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Ricardo Neri , "Tim C . Chen" Subject: [PATCH v2 22/22] x86/process: Reset hardware history in context switch Date: Mon, 28 Nov 2022 05:21:00 -0800 Message-Id: <20221128132100.30253-23-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> References: <20221128132100.30253-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750746037654064696?= X-GMAIL-MSGID: =?utf-8?q?1750746037654064696?= Reset the classification history of the current task when switching to the next task. Hardware will start the classification of the next task from scratch. Cc: Ben Segall Cc: Daniel Bristot de Oliveira Cc: Dietmar Eggemann Cc: Joel Fernandes (Google) Cc: Len Brown Cc: Mel Gorman Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Steven Rostedt Cc: Tim C. Chen Cc: Valentin Schneider Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ricardo Neri --- Changes since v1: * Measurements of the cost of the HRESET instruction Methodology: I created a tight loop with interrupts and preemption disabled. I recorded the value of the TSC counter before and after executing HRESET or RDTSC. I repeated the measurement 100,000 times. I performed the experiment using an Alder Lake S system. I set the frequency of the CPUs at a fixed value. The table below compares the cost of HRESET with RDTSC (expressed in the elapsed TSC count). The cost of the two instructions is comparable. PCore ECore Frequency (GHz) 5.0 3.8 HRESET (avg) 28.5 44.7 HRESET (stdev %) 3.6 2.3 RDTSC (avg) 25.2 35.7 RDTSC (stdev %) 3.9 2.6 * Used an ALTERNATIVE macro instead of static_cpu_has() to execute HRESET when supported. (PeterZ) --- arch/x86/include/asm/hreset.h | 30 ++++++++++++++++++++++++++++++ arch/x86/kernel/cpu/common.c | 7 +++++++ arch/x86/kernel/process_32.c | 3 +++ arch/x86/kernel/process_64.c | 3 +++ 4 files changed, 43 insertions(+) create mode 100644 arch/x86/include/asm/hreset.h diff --git a/arch/x86/include/asm/hreset.h b/arch/x86/include/asm/hreset.h new file mode 100644 index 000000000000..d68ca2fb8642 --- /dev/null +++ b/arch/x86/include/asm/hreset.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_X86_HRESET_H + +/** + * HRESET - History reset. Available since binutils v2.36. + * + * Request the processor to reset the history of task classification on the + * current logical processor. The history components to be + * reset are specified in %eax. Only bits specified in CPUID(0x20).EBX + * and enabled in the IA32_HRESET_ENABLE MSR can be selected. + * + * The assembly code looks like: + * + * hreset %eax + * + * The corresponding machine code looks like: + * + * F3 0F 3A F0 ModRM Imm + * + * The value of ModRM is 0xc0 to specify %eax register addressing. + * The ignored immediate operand is set to 0. + * + * The instruction is documented in the Intel SDM. + */ + +#define __ASM_HRESET ".byte 0xf3, 0xf, 0x3a, 0xf0, 0xc0, 0x0" + +void reset_hardware_history(void); + +#endif /* _ASM_X86_HRESET_H */ diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index f8630da2a6dd..6c2b9768698e 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -53,6 +53,7 @@ #include #include #include +#include #include #include #include @@ -414,6 +415,12 @@ static __always_inline void setup_umip(struct cpuinfo_x86 *c) static u32 hardware_history_features __ro_after_init; +void reset_hardware_history(void) +{ + asm_inline volatile (ALTERNATIVE("", __ASM_HRESET, X86_FEATURE_HRESET) + : : "a" (hardware_history_features) : "memory"); +} + static __always_inline void setup_hreset(struct cpuinfo_x86 *c) { if (!cpu_feature_enabled(X86_FEATURE_HRESET)) diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c index 470c128759ea..397a6e6f4e61 100644 --- a/arch/x86/kernel/process_32.c +++ b/arch/x86/kernel/process_32.c @@ -52,6 +52,7 @@ #include #include #include +#include #include #include "process.h" @@ -214,6 +215,8 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) /* Load the Intel cache allocation PQR MSR. */ resctrl_sched_in(); + reset_hardware_history(); + return prev_p; } diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 084ec467dbb1..ac9b3d44c1bd 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -53,6 +53,7 @@ #include #include #include +#include #include #include #ifdef CONFIG_IA32_EMULATION @@ -658,6 +659,8 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) /* Load the Intel cache allocation PQR MSR. */ resctrl_sched_in(); + reset_hardware_history(); + return prev_p; }