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[46.135.44.69]) by smtp.gmail.com with ESMTPSA id g3-20020adffc83000000b0024207ed4ce0sm7711817wrr.58.2022.11.28.03.17.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Nov 2022 03:17:57 -0800 (PST) Sender: Tomeu Vizoso From: Tomeu Vizoso Cc: italonicola@collabora.com, Tomeu Vizoso , Neil Armstrong , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Amlogic Meson SoC support), linux-amlogic@lists.infradead.org (open list:ARM/Amlogic Meson SoC support), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 1/5] dt-bindings: reset: meson-g12a: Add missing NNA reset Date: Mon, 28 Nov 2022 12:17:34 +0100 Message-Id: <20221128111740.39003-2-tomeu.vizoso@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221128111740.39003-1-tomeu.vizoso@collabora.com> References: <20221128111740.39003-1-tomeu.vizoso@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750739267655454937?= X-GMAIL-MSGID: =?utf-8?q?1750739267655454937?= Doesn't appear in the TRM I have, but it is used by the downstream galcore driver. Signed-off-by: Tomeu Vizoso Acked-by: Neil Armstrong --- include/dt-bindings/reset/amlogic,meson-g12a-reset.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h index 6d487c5eba2c..45f6b8a951d0 100644 --- a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h +++ b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h @@ -69,7 +69,9 @@ #define RESET_PARSER_FETCH 72 #define RESET_CTL 73 #define RESET_PARSER_TOP 74 -/* 75-77 */ +/* 75 */ +#define RESET_NNA 76 +/* 77 */ #define RESET_DVALIN 78 #define RESET_HDMITX 79 /* 80-95 */ From patchwork Mon Nov 28 11:17:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomeu Vizoso X-Patchwork-Id: 26637 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5593698wrr; Mon, 28 Nov 2022 03:31:56 -0800 (PST) X-Google-Smtp-Source: AA0mqf6ANBSHWs4nxdCVQMtj7ghMyT0tc2qrKUw4/18jCIFR3qoJaOAp7OsrJezPwGRgHIq6AaU5 X-Received: by 2002:a17:906:5e49:b0:7ae:38fd:45e9 with SMTP id b9-20020a1709065e4900b007ae38fd45e9mr41091773eju.496.1669635116124; Mon, 28 Nov 2022 03:31:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669635116; cv=none; d=google.com; s=arc-20160816; b=Qxuy9hWnp6o0hMPtcYbwmQlKg8D3BwhHql9yxh4XybeGzuMWxdV3BYsNTbEkYENs/r AuG4TsHMRxfEr64rVTRHqy0as/mAmwqcRoAOan0J7ugdn358tlMzgLPqzUtY7AV0CJ5E uCnlZuBnhs345PmJZYwnkSBBYNq3eZj39yi4R9ze1BLWfuA2RMfTRWbnoLn4j/mz5A/y BfFnnNRBOhmJnZEhj8w7RNdYy+ycznKK0buuRHzq2ohnM4nlu79LiCXt+oqphi19M0EW C9hsIopGpmRGVbqf1ERhu0Kp8t1r+mvGT11utBVD+XfSNowk8g2Vu05v+Qvz/cAs308r 3JWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:to:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:from:sender :dkim-signature; bh=6UPpIU6lTdK7INRlRgvRZ2pUB9CB4XOUu+P4PTYKdZI=; b=z6QiOoko+6KYaCAsWUvyR1XgGg9E4ZnLFFmloG2kmuJEye0YjhbuNmzhPIzdyK22qd nD65enCXX0DEI+fZmZx9gIQf5PjL57rD3meyHyEATtmwLIzIicJ+vW0diLUcAEkT66F0 5hey30ejaPVGkqRRGMOXtG3K99C1hcpJs2Q+8Pup4aLHZEVBiACuSf3kChkz1hSYVUg/ vJ5Iae/FVqBTELEY7HDjEMmpcTKjpeQtpgN0b1qTp1sV4CtIL5SmEOWGQs0ExKswNx2i twaIcM+FUnjZORkPKgR8TRbhFPxt3laByrgULUhkT/JMxAyRm/SwpjMHBiILrKuj8RzO YBLA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20210112 header.b=ipUjo8xR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. 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[46.135.44.69]) by smtp.gmail.com with ESMTPSA id g3-20020adffc83000000b0024207ed4ce0sm7711817wrr.58.2022.11.28.03.17.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Nov 2022 03:17:59 -0800 (PST) Sender: Tomeu Vizoso From: Tomeu Vizoso Cc: italonicola@collabora.com, Tomeu Vizoso , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Amlogic Meson SoC support), linux-amlogic@lists.infradead.org (open list:ARM/Amlogic Meson SoC support), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 2/5] dt-bindings: power: Add NNA power domain Date: Mon, 28 Nov 2022 12:17:35 +0100 Message-Id: <20221128111740.39003-3-tomeu.vizoso@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221128111740.39003-1-tomeu.vizoso@collabora.com> References: <20221128111740.39003-1-tomeu.vizoso@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750739311729779415?= X-GMAIL-MSGID: =?utf-8?q?1750739311729779415?= Signed-off-by: Tomeu Vizoso Acked-by: Neil Armstrong --- include/dt-bindings/power/meson-g12a-power.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/power/meson-g12a-power.h b/include/dt-bindings/power/meson-g12a-power.h index bb5e67a842de..93b03bdd60b7 100644 --- a/include/dt-bindings/power/meson-g12a-power.h +++ b/include/dt-bindings/power/meson-g12a-power.h @@ -9,5 +9,6 @@ #define PWRC_G12A_VPU_ID 0 #define PWRC_G12A_ETH_ID 1 +#define PWRC_G12A_NNA_ID 2 #endif From patchwork Mon Nov 28 11:17:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomeu Vizoso X-Patchwork-Id: 26639 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5593792wrr; Mon, 28 Nov 2022 03:32:06 -0800 (PST) X-Google-Smtp-Source: AA0mqf6uAC2TKNvs/QQhIPm4z2M0AmVFiqGmazo9daN6MCuWgRWM579AAr6UlQBKHWbZCBNzRU1a X-Received: by 2002:a05:6402:5d5:b0:464:fa1:9ece with SMTP id n21-20020a05640205d500b004640fa19ecemr22219486edx.262.1669635125922; Mon, 28 Nov 2022 03:32:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669635125; cv=none; d=google.com; s=arc-20160816; b=j+DzjiQJkn4sDCfinyqktf4KZ8OnT3P5BzYB1RhZR3u5B1Noe0jMEXCy5kCQaWg6Oo +ISU3MaanTvvryNCM59813O3C8DAdjX3fAu3bj4Grc9PljkkC4iDeQoKilcCJdMNsUl6 T5AykJLkiuw//TohkwHdAAwVmF/e1frtkQABEvOUGnzVIKcy0qnW0Mqx44cL1gWSwERu p21sBss+Ezdi7f1DzAAoio3Mjw8WGsRPm5YD74SWuZsTKmRycdSni8o4sI8Vta0ao+A2 EHZa6bpZhqOprCAFm3Gzh8dnez8anII+VTu7kWo8jwYQXcoG1mmZFk789DiCE17DMjXE hzgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:to:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:from:sender :dkim-signature; bh=Cw/am3froU3IMTWG9BB3ZSyfplgImMW6lCXqrhZP2N0=; b=oaWzyPhRHiT1MGfAVGM2Jw/ao/CV3tWdozKKw5sFrAyeAH5gvDDYQWccFNTYRKJ7/G A0RXlKFMCnqETluCSKHKBz8XUbjozrm+4zTwdzx7XAzugFfv96oi50oXmd2uJptfcDRb 3akBYHBY2t/oCkluGRVyUJ1WgeB7KqxBSheCvGIx1axUxYeYr8PDI7b14amegeZYEu+J Guvrm3d1bzC5OVGUmrp3fst1FCr67uuZikBo5hbDByG0otZSyAxzM7zOkp25f86GQMI6 y+71gIUcOLwVw66Wo85k0OraCwfDt9fjLppQpDgZCeY7PpplZYdHy2AcgWxz05V6K3+o lc9g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20210112 header.b=e8gELn8I; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. 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[46.135.44.69]) by smtp.gmail.com with ESMTPSA id g3-20020adffc83000000b0024207ed4ce0sm7711817wrr.58.2022.11.28.03.18.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Nov 2022 03:18:01 -0800 (PST) Sender: Tomeu Vizoso From: Tomeu Vizoso Cc: italonicola@collabora.com, Tomeu Vizoso , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , linux-arm-kernel@lists.infradead.org (moderated list:ARM/Amlogic Meson SoC support), linux-amlogic@lists.infradead.org (open list:ARM/Amlogic Meson SoC support), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 3/5] soc: amlogic: meson-pwrc: Add NNA power domain for A311D Date: Mon, 28 Nov 2022 12:17:36 +0100 Message-Id: <20221128111740.39003-4-tomeu.vizoso@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221128111740.39003-1-tomeu.vizoso@collabora.com> References: <20221128111740.39003-1-tomeu.vizoso@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750739321643217758?= X-GMAIL-MSGID: =?utf-8?q?1750739321643217758?= Based on power initialization sequence in downstream driver. Signed-off-by: Tomeu Vizoso Reviewed-by: Neil Armstrong --- drivers/soc/amlogic/meson-ee-pwrc.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/soc/amlogic/meson-ee-pwrc.c b/drivers/soc/amlogic/meson-ee-pwrc.c index dd5f2a13ceb5..dfbf0b1c7d29 100644 --- a/drivers/soc/amlogic/meson-ee-pwrc.c +++ b/drivers/soc/amlogic/meson-ee-pwrc.c @@ -46,6 +46,9 @@ #define HHI_NANOQ_MEM_PD_REG1 (0x47 << 2) #define HHI_VPU_MEM_PD_REG2 (0x4d << 2) +#define G12A_HHI_NANOQ_MEM_PD_REG0 (0x43 << 2) +#define G12A_HHI_NANOQ_MEM_PD_REG1 (0x44 << 2) + struct meson_ee_pwrc; struct meson_ee_pwrc_domain; @@ -106,6 +109,13 @@ static struct meson_ee_pwrc_top_domain sm1_pwrc_usb = SM1_EE_PD(17); static struct meson_ee_pwrc_top_domain sm1_pwrc_pci = SM1_EE_PD(18); static struct meson_ee_pwrc_top_domain sm1_pwrc_ge2d = SM1_EE_PD(19); +static struct meson_ee_pwrc_top_domain g12a_pwrc_nna = { \ + .sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0, \ + .sleep_mask = BIT(16) | BIT(17), \ + .iso_reg = GX_AO_RTI_GEN_PWR_ISO0, \ + .iso_mask = BIT(16) | BIT(17), \ + }; + /* Memory PD Domains */ #define VPU_MEMPD(__reg) \ @@ -217,6 +227,11 @@ static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = { { HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) }, }; +static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_nna[] = { + { G12A_HHI_NANOQ_MEM_PD_REG0, GENMASK(31, 0) }, + { G12A_HHI_NANOQ_MEM_PD_REG1, GENMASK(23, 0) }, +}; + #define VPU_PD(__name, __top_pd, __mem, __is_pwr_off, __resets, __clks) \ { \ .name = __name, \ @@ -253,6 +268,8 @@ static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = { [PWRC_G12A_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, g12a_pwrc_mem_vpu, pwrc_ee_is_powered_off, 11, 2), [PWRC_G12A_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth), + [PWRC_G12A_NNA_ID] = TOP_PD("NNA", &g12a_pwrc_nna, g12a_pwrc_mem_nna, + pwrc_ee_is_powered_off), }; static struct meson_ee_pwrc_domain_desc gxbb_pwrc_domains[] = { From patchwork Mon Nov 28 11:17:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomeu Vizoso X-Patchwork-Id: 26642 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5594476wrr; Mon, 28 Nov 2022 03:33:27 -0800 (PST) X-Google-Smtp-Source: AA0mqf6uJIvdrK8wPz0+OXfS/CfMzOWAYaMMR8W04UWqI63elMV3R2Sb+R2H3earVt32tIS5opgs X-Received: by 2002:a17:902:a9c6:b0:188:52df:769e with SMTP id b6-20020a170902a9c600b0018852df769emr30824359plr.30.1669635206806; Mon, 28 Nov 2022 03:33:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669635206; cv=none; d=google.com; s=arc-20160816; b=0uVAz9K3wNYc1UlnuG3tY2U6sMFza/fahhR9Foh8YzM0hRX25r4diG1SdCkv77Lf+n rDNTq7WK9WGKdhkNJ+VydQOeoQqIvNNrsHlnRGvhFjNAozRQNouNFIdGQtYKCEKlKfau 0yqIfzX1SIMYA0kDlWBhWLiBKrUgMhcp+5vk1nahCR808YvdoZdKSdfDG6d0fvUno3C1 qW22JfYruGC0bvyz9h51Yx9pw/fxa2YOZtZyH+PgRLGj+AOXT6h36N+Ue9Sagipug4f/ HyLiAmcNowvGEnExmVK1I2gLjblhHE946ukCYWqPerkPOPBtmexGQLIvvwT5ODahfBGL hhDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:to:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:from:sender :dkim-signature; bh=MZ/yfW2uv4L2OBEMjogEawvHGxQ+pctbkljRiIAmmkE=; b=U3vsCLTvws16l3wNoiBNjyD7quvZi0nV6ML640bbjo8njSBGbPUORg+M/Jm2QNFRK9 sL+GZySbXQz3rwnKxpolnMkKdcifbwCCYMyUdTx34Ap+tlnJbAZRO96I2BM/CWEQyw7A wIdIt2kTNajsbcBRtcKU/uj7H6wKpdaXsOHgpoo6KDA9w8AmUEIjW0ulLv30FIR+mbua 45+yEcv9VF2ZEig+0f4/AvuLz5wn5Lyz2L7EUome9vytSzO1hrSFU1svQuGp//SbwQCm xri6iz5iRX67d788znmin97/OZgZhV1avvkLyKJpnetZAHXXsFH6BxIYJws1Zxl0ZEWN gJag== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20210112 header.b=hGj6yWEx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. 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[46.135.44.69]) by smtp.gmail.com with ESMTPSA id g3-20020adffc83000000b0024207ed4ce0sm7711817wrr.58.2022.11.28.03.18.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Nov 2022 03:18:03 -0800 (PST) Sender: Tomeu Vizoso From: Tomeu Vizoso Cc: italonicola@collabora.com, Tomeu Vizoso , Rob Herring , Krzysztof Kozlowski , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Amlogic Meson SoC support), linux-amlogic@lists.infradead.org (open list:ARM/Amlogic Meson SoC support), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 4/5] arm64: dts: Add DT node for the VIPNano-QI on the A311D Date: Mon, 28 Nov 2022 12:17:37 +0100 Message-Id: <20221128111740.39003-5-tomeu.vizoso@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221128111740.39003-1-tomeu.vizoso@collabora.com> References: <20221128111740.39003-1-tomeu.vizoso@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750739406679737264?= X-GMAIL-MSGID: =?utf-8?q?1750739406679737264?= This "NPU" is very similar to the Vivante GPUs and Etnaviv works well with it with just a few small changes. v2: Add reference to RESET_NNA (Neil) Signed-off-by: Tomeu Vizoso Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 11 +++++++++++ .../boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts | 4 ++++ 2 files changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index 45947c1031c4..aaa629816e41 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include / { interrupt-parent = <&gic>; @@ -2484,4 +2485,14 @@ xtal: xtal-clk { #clock-cells = <0>; }; + npu: npu@ff100000 { + compatible = "vivante,gc"; + reg = <0x0 0xff100000 0x0 0x20000>; + interrupts = <0 147 4>; + clocks = <&clkc CLKID_NNA_CORE_CLK>, + <&clkc CLKID_NNA_AXI_CLK>; + clock-names = "core", "bus"; + resets = <&reset RESET_NNA>; + power-domains = <&pwrc PWRC_G12A_NNA_ID>; + }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts index 124a80901084..73f3d87dcefd 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts @@ -15,6 +15,10 @@ / { compatible = "khadas,vim3", "amlogic,a311d", "amlogic,g12b"; }; +&npu { + status = "okay"; +}; + /* * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between From patchwork Mon Nov 28 11:17:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomeu Vizoso X-Patchwork-Id: 26645 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5595278wrr; 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[46.135.44.69]) by smtp.gmail.com with ESMTPSA id g3-20020adffc83000000b0024207ed4ce0sm7711817wrr.58.2022.11.28.03.18.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Nov 2022 03:18:04 -0800 (PST) Sender: Tomeu Vizoso From: Tomeu Vizoso Cc: italonicola@collabora.com, Tomeu Vizoso , Lucas Stach , Russell King , Christian Gmeiner , David Airlie , Daniel Vetter , etnaviv@lists.freedesktop.org (moderated list:DRM DRIVERS FOR VIVANTE GPU IP), dri-devel@lists.freedesktop.org (open list:DRM DRIVERS FOR VIVANTE GPU IP), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 5/5] drm/etnaviv: add HWDB entry for VIPNano-QI.7120.0055 Date: Mon, 28 Nov 2022 12:17:38 +0100 Message-Id: <20221128111740.39003-6-tomeu.vizoso@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221128111740.39003-1-tomeu.vizoso@collabora.com> References: <20221128111740.39003-1-tomeu.vizoso@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750739496660495991?= X-GMAIL-MSGID: =?utf-8?q?1750739496660495991?= This is a compute-only module marketed towards AI and vision acceleration. This particular version can be found on the Amlogic A311D SoC. The feature bits are taken from the Khadas downstream kernel driver 6.4.4.3.310723AAA. Signed-off-by: Tomeu Vizoso --- drivers/gpu/drm/etnaviv/etnaviv_hwdb.c | 31 ++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c b/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c index f2fc645c7956..3f6fd9a3c088 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c @@ -130,6 +130,37 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = { .minor_features10 = 0x90044250, .minor_features11 = 0x00000024, }, + { + .model = 0x8000, + .revision = 0x7120, + .product_id = 0x45080009, + .customer_id = 0x88, + .eco_id = 0, + .stream_count = 8, + .register_max = 64, + .thread_count = 256, + .shader_core_count = 1, + .vertex_cache_size = 16, + .vertex_output_buffer_size = 1024, + .pixel_pipes = 1, + .instruction_count = 512, + .num_constants = 320, + .buffer_size = 0, + .varyings_count = 16, + .features = 0xe0287cac, + .minor_features0 = 0xc1799eff, + .minor_features1 = 0xfefbfadb, + .minor_features2 = 0xeb9d6fbf, + .minor_features3 = 0xedfffced, + .minor_features4 = 0xd30dafc7, + .minor_features5 = 0x7b5ac333, + .minor_features6 = 0xfc8ee200, + .minor_features7 = 0x03fffa6f, + .minor_features8 = 0x00fe0ef0, + .minor_features9 = 0x0088003c, + .minor_features10 = 0x108048c0, + .minor_features11 = 0x00000010, + }, }; bool etnaviv_fill_identity_from_hwdb(struct etnaviv_gpu *gpu)