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[2620:137:e000::1:20]) by mx.google.com with ESMTP id e11-20020a17090658cb00b007adef1e3ba7si10566618ejs.587.2022.11.28.02.34.41; Mon, 28 Nov 2022 02:35:04 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=RhCUGrwx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230288AbiK1KdO (ORCPT + 99 others); Mon, 28 Nov 2022 05:33:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230281AbiK1KdK (ORCPT ); Mon, 28 Nov 2022 05:33:10 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A306140C1; Mon, 28 Nov 2022 02:33:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1669631585; x=1701167585; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bxT1YzwXwCRi+eKkhv8DSI+QJY1u4wLDwuWXGDFx9Ns=; b=RhCUGrwxaywhHBTKBoykKyvxivi7auTMhwGpWLUaV/UNGHMVvd2XaLYx 4mphuMaL7qh5o+rlyeoLNOF5nMR7He51unS0PoXOsa6YAH4+nB4ztQGx1 tnASPaTHaGhoQ7RKW3SRf+A/WWoHo9eiyY1r0oSvHwAEQoyUR2vbk8dEh i1kJCLQbbBdAuyFsC6Yelud/NL61n55hq+XZjT6fAsXR929z+yGWEsBqg I0477Ml1trNsNZxPE7lP4L6NusKsftPqaXYGDGjeLexPFdL7ysO1Br9+D VtoLV1ZVs9g/fHJaBhrwSVPERuSvJhHQcM45IgyctX+JMbRLpT2ir3Fqe g==; X-IronPort-AV: E=Sophos;i="5.96,200,1665471600"; d="scan'208";a="190770148" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Nov 2022 03:33:05 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 28 Nov 2022 03:33:04 -0700 Received: from CHE-LT-I17769U.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 28 Nov 2022 03:32:58 -0700 From: Arun Ramadoss To: , CC: , , , , , , , , , , , , , Subject: [Patch net-next v1 01/12] net: dsa: microchip: ptp: add the posix clock support Date: Mon, 28 Nov 2022 16:02:16 +0530 Message-ID: <20221128103227.23171-2-arun.ramadoss@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221128103227.23171-1-arun.ramadoss@microchip.com> References: <20221128103227.23171-1-arun.ramadoss@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750735734532194286?= X-GMAIL-MSGID: =?utf-8?q?1750735734532194286?= From: Christian Eggers This patch implement routines (adjfine, adjtime, gettime and settime) for manipulating the chip's PTP clock. It registers the ptp caps to posix clock register. Signed-off-by: Christian Eggers Co-developed-by: Arun Ramadoss Signed-off-by: Arun Ramadoss --- RFC v2 -> Patch v1 - Repharsed the Kconfig help text - Removed IS_ERR_OR_NULL check in ptp_clock_unregister - Add the check for ptp_data->clock in ksz_ptp_ts_info - Renamed MAX_DRIFT_CORR to KSZ_MAX_DRIFT_CORR - Removed the comments - Variables declaration in reverse christmas tree - Added the ptp_clock_optional --- drivers/net/dsa/microchip/Kconfig | 11 + drivers/net/dsa/microchip/Makefile | 5 + drivers/net/dsa/microchip/ksz_common.c | 14 +- drivers/net/dsa/microchip/ksz_common.h | 16 ++ drivers/net/dsa/microchip/ksz_ptp.c | 265 ++++++++++++++++++++++++ drivers/net/dsa/microchip/ksz_ptp.h | 45 ++++ drivers/net/dsa/microchip/ksz_ptp_reg.h | 57 +++++ 7 files changed, 412 insertions(+), 1 deletion(-) create mode 100644 drivers/net/dsa/microchip/ksz_ptp.c create mode 100644 drivers/net/dsa/microchip/ksz_ptp.h create mode 100644 drivers/net/dsa/microchip/ksz_ptp_reg.h diff --git a/drivers/net/dsa/microchip/Kconfig b/drivers/net/dsa/microchip/Kconfig index 913f83ef013c..0546c573668a 100644 --- a/drivers/net/dsa/microchip/Kconfig +++ b/drivers/net/dsa/microchip/Kconfig @@ -11,6 +11,7 @@ menuconfig NET_DSA_MICROCHIP_KSZ_COMMON config NET_DSA_MICROCHIP_KSZ9477_I2C tristate "KSZ series I2C connected switch driver" depends on NET_DSA_MICROCHIP_KSZ_COMMON && I2C + depends on PTP_1588_CLOCK_OPTIONAL select REGMAP_I2C help Select to enable support for registering switches configured through I2C. @@ -18,10 +19,20 @@ config NET_DSA_MICROCHIP_KSZ9477_I2C config NET_DSA_MICROCHIP_KSZ_SPI tristate "KSZ series SPI connected switch driver" depends on NET_DSA_MICROCHIP_KSZ_COMMON && SPI + depends on PTP_1588_CLOCK_OPTIONAL select REGMAP_SPI help Select to enable support for registering switches configured through SPI. +config NET_DSA_MICROCHIP_KSZ_PTP + bool "Support for the PTP clock on the KSZ9563/LAN937x Ethernet Switch" + depends on NET_DSA_MICROCHIP_KSZ_COMMON && PTP_1588_CLOCK + help + Select to enable support for timestamping & PTP clock manipulation in + KSZ8563/KSZ9563/LAN937x series of switches. KSZ9563/KSZ8563 supports + only one step timestamping. LAN937x switch supports both one step and + two step timestamping. + config NET_DSA_MICROCHIP_KSZ8863_SMI tristate "KSZ series SMI connected switch driver" depends on NET_DSA_MICROCHIP_KSZ_COMMON diff --git a/drivers/net/dsa/microchip/Makefile b/drivers/net/dsa/microchip/Makefile index 28873559efc2..48360cc9fc68 100644 --- a/drivers/net/dsa/microchip/Makefile +++ b/drivers/net/dsa/microchip/Makefile @@ -4,6 +4,11 @@ ksz_switch-objs := ksz_common.o ksz_switch-objs += ksz9477.o ksz_switch-objs += ksz8795.o ksz_switch-objs += lan937x_main.o + +ifdef CONFIG_NET_DSA_MICROCHIP_KSZ_PTP +ksz_switch-objs += ksz_ptp.o +endif + obj-$(CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C) += ksz9477_i2c.o obj-$(CONFIG_NET_DSA_MICROCHIP_KSZ_SPI) += ksz_spi.o obj-$(CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI) += ksz8863_smi.o diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c index 8c8db315317d..2d09cd141db6 100644 --- a/drivers/net/dsa/microchip/ksz_common.c +++ b/drivers/net/dsa/microchip/ksz_common.c @@ -24,6 +24,7 @@ #include #include "ksz_common.h" +#include "ksz_ptp.h" #include "ksz8.h" #include "ksz9477.h" #include "lan937x.h" @@ -2016,10 +2017,16 @@ static int ksz_setup(struct dsa_switch *ds) } } + ret = ksz_ptp_clock_register(ds); + if (ret) { + dev_err(dev->dev, "Failed to register PTP clock: %d\n", ret); + goto out_pirq; + } + ret = ksz_mdio_register(dev); if (ret < 0) { dev_err(dev->dev, "failed to register the mdio"); - goto out_pirq; + goto out_ptp_clock_unregister; } /* start switch */ @@ -2028,6 +2035,8 @@ static int ksz_setup(struct dsa_switch *ds) return 0; +out_ptp_clock_unregister: + ksz_ptp_clock_unregister(ds); out_pirq: if (dev->irq > 0) dsa_switch_for_each_user_port(dp, dev->ds) @@ -2044,6 +2053,8 @@ static void ksz_teardown(struct dsa_switch *ds) struct ksz_device *dev = ds->priv; struct dsa_port *dp; + ksz_ptp_clock_unregister(ds); + if (dev->irq > 0) { dsa_switch_for_each_user_port(dp, dev->ds) ksz_irq_free(&dev->ports[dp->index].pirq); @@ -2861,6 +2872,7 @@ static const struct dsa_switch_ops ksz_switch_ops = { .get_pause_stats = ksz_get_pause_stats, .port_change_mtu = ksz_change_mtu, .port_max_mtu = ksz_max_mtu, + .get_ts_info = ksz_get_ts_info, }; struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h index c6726cbd5465..5a6bfd42c6f9 100644 --- a/drivers/net/dsa/microchip/ksz_common.h +++ b/drivers/net/dsa/microchip/ksz_common.h @@ -15,6 +15,8 @@ #include #include +#include "ksz_ptp.h" + #define KSZ_MAX_NUM_PORTS 8 struct ksz_device; @@ -141,6 +143,7 @@ struct ksz_device { u16 port_mask; struct mutex lock_irq; /* IRQ Access */ struct ksz_irq girq; + struct ksz_ptp_data ptp_data; }; /* List of supported models */ @@ -444,6 +447,19 @@ static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) return ret; } +static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask, + u16 value) +{ + int ret; + + ret = regmap_update_bits(dev->regmap[1], reg, mask, value); + if (ret) + dev_err(dev->dev, "can't rmw 16bit reg: 0x%x %pe\n", reg, + ERR_PTR(ret)); + + return ret; +} + static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) { u32 val[2]; diff --git a/drivers/net/dsa/microchip/ksz_ptp.c b/drivers/net/dsa/microchip/ksz_ptp.c new file mode 100644 index 000000000000..c737635ca266 --- /dev/null +++ b/drivers/net/dsa/microchip/ksz_ptp.c @@ -0,0 +1,265 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Microchip KSZ PTP Implementation + * Copyright (C) 2022 Microchip Technology Inc. + */ + +#include +#include +#include + +#include "ksz_common.h" +#include "ksz_ptp.h" +#include "ksz_ptp_reg.h" + +#define ptp_caps_to_data(d) container_of((d), struct ksz_ptp_data, caps) +#define ptp_data_to_ksz_dev(d) container_of((d), struct ksz_device, ptp_data) + +#define KSZ_MAX_DRIFT_CORR 6250000 + +#define KSZ_PTP_INC_NS 40 /* HW clock is incremented every 40 ns (by 40) */ +#define KSZ_PTP_SUBNS_BITS 32 + +/* The function is return back the capability of timestamping feature when + * requested through ethtool -T utility + */ +int ksz_get_ts_info(struct dsa_switch *ds, int port, struct ethtool_ts_info *ts) +{ + struct ksz_device *dev = ds->priv; + struct ksz_ptp_data *ptp_data; + + ptp_data = &dev->ptp_data; + + if (!ptp_data->clock) + return -ENODEV; + + ts->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE | + SOF_TIMESTAMPING_RX_HARDWARE | + SOF_TIMESTAMPING_RAW_HARDWARE; + + ts->tx_types = BIT(HWTSTAMP_TX_OFF); + + ts->rx_filters = BIT(HWTSTAMP_FILTER_NONE); + + ts->phc_index = ptp_clock_index(ptp_data->clock); + + return 0; +} + +static int _ksz_ptp_gettime(struct ksz_device *dev, struct timespec64 *ts) +{ + u32 nanoseconds; + u32 seconds; + u8 phase; + int ret; + + /* Copy current PTP clock into shadow registers and read */ + ret = ksz_rmw16(dev, REG_PTP_CLK_CTRL, PTP_READ_TIME, PTP_READ_TIME); + if (ret) + return ret; + + ret = ksz_read8(dev, REG_PTP_RTC_SUB_NANOSEC__2, &phase); + if (ret) + return ret; + + ret = ksz_read32(dev, REG_PTP_RTC_NANOSEC, &nanoseconds); + if (ret) + return ret; + + ret = ksz_read32(dev, REG_PTP_RTC_SEC, &seconds); + if (ret) + return ret; + + ts->tv_sec = seconds; + ts->tv_nsec = nanoseconds + phase * 8; + + return 0; +} + +static int ksz_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) +{ + struct ksz_ptp_data *ptp_data = ptp_caps_to_data(ptp); + struct ksz_device *dev = ptp_data_to_ksz_dev(ptp_data); + int ret; + + mutex_lock(&ptp_data->lock); + ret = _ksz_ptp_gettime(dev, ts); + mutex_unlock(&ptp_data->lock); + + return ret; +} + +static int ksz_ptp_settime(struct ptp_clock_info *ptp, + const struct timespec64 *ts) +{ + struct ksz_ptp_data *ptp_data = ptp_caps_to_data(ptp); + struct ksz_device *dev = ptp_data_to_ksz_dev(ptp_data); + int ret; + + mutex_lock(&ptp_data->lock); + + /* Write to shadow registers and Load PTP clock */ + ret = ksz_write16(dev, REG_PTP_RTC_SUB_NANOSEC__2, PTP_RTC_0NS); + if (ret) + goto error_return; + + ret = ksz_write32(dev, REG_PTP_RTC_NANOSEC, ts->tv_nsec); + if (ret) + goto error_return; + + ret = ksz_write32(dev, REG_PTP_RTC_SEC, ts->tv_sec); + if (ret) + goto error_return; + + ret = ksz_rmw16(dev, REG_PTP_CLK_CTRL, PTP_LOAD_TIME, PTP_LOAD_TIME); + +error_return: + mutex_unlock(&ptp_data->lock); + + return ret; +} + +static int ksz_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) +{ + struct ksz_ptp_data *ptp_data = ptp_caps_to_data(ptp); + struct ksz_device *dev = ptp_data_to_ksz_dev(ptp_data); + int ret; + + mutex_lock(&ptp_data->lock); + + if (scaled_ppm) { + s64 ppb, adj; + u32 data32; + + /* see scaled_ppm_to_ppb() in ptp_clock.c for details */ + ppb = 1 + scaled_ppm; + ppb *= 125; + ppb *= KSZ_PTP_INC_NS; + ppb <<= KSZ_PTP_SUBNS_BITS - 13; + adj = div_s64(ppb, NSEC_PER_SEC); + + data32 = abs(adj); + data32 &= PTP_SUBNANOSEC_M; + if (adj >= 0) + data32 |= PTP_RATE_DIR; + + ret = ksz_write32(dev, REG_PTP_SUBNANOSEC_RATE, data32); + if (ret) + goto error_return; + + ret = ksz_rmw16(dev, REG_PTP_CLK_CTRL, PTP_CLK_ADJ_ENABLE, + PTP_CLK_ADJ_ENABLE); + if (ret) + goto error_return; + } else { + ret = ksz_rmw16(dev, REG_PTP_CLK_CTRL, PTP_CLK_ADJ_ENABLE, 0); + if (ret) + goto error_return; + } + +error_return: + mutex_unlock(&ptp_data->lock); + return ret; +} + +static int ksz_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) +{ + struct ksz_ptp_data *ptp_data = ptp_caps_to_data(ptp); + struct ksz_device *dev = ptp_data_to_ksz_dev(ptp_data); + s32 sec, nsec; + u16 data16; + int ret; + + mutex_lock(&ptp_data->lock); + + /* do not use ns_to_timespec64(), + * both sec and nsec are subtracted by hw + */ + sec = div_s64_rem(delta, NSEC_PER_SEC, &nsec); + + ret = ksz_write32(dev, REG_PTP_RTC_NANOSEC, abs(nsec)); + if (ret) + goto error_return; + + ret = ksz_write32(dev, REG_PTP_RTC_SEC, abs(sec)); + if (ret) + goto error_return; + + ret = ksz_read16(dev, REG_PTP_CLK_CTRL, &data16); + if (ret) + goto error_return; + + data16 |= PTP_STEP_ADJ; + + /*PTP_STEP_DIR -- 0: subtract, 1: add */ + if (delta < 0) + data16 &= ~PTP_STEP_DIR; + else + data16 |= PTP_STEP_DIR; + + ret = ksz_write16(dev, REG_PTP_CLK_CTRL, data16); + +error_return: + mutex_unlock(&ptp_data->lock); + return ret; +} + +static int ksz_ptp_start_clock(struct ksz_device *dev) +{ + return ksz_rmw16(dev, REG_PTP_CLK_CTRL, PTP_CLK_ENABLE, PTP_CLK_ENABLE); +} + +static const struct ptp_clock_info ksz_ptp_caps = { + .owner = THIS_MODULE, + .name = "Microchip Clock", + .max_adj = KSZ_MAX_DRIFT_CORR, + .gettime64 = ksz_ptp_gettime, + .settime64 = ksz_ptp_settime, + .adjfine = ksz_ptp_adjfine, + .adjtime = ksz_ptp_adjtime, +}; + +int ksz_ptp_clock_register(struct dsa_switch *ds) +{ + struct ksz_device *dev = ds->priv; + struct ksz_ptp_data *ptp_data; + int ret; + + ptp_data = &dev->ptp_data; + mutex_init(&ptp_data->lock); + + ptp_data->caps = ksz_ptp_caps; + + ret = ksz_ptp_start_clock(dev); + if (ret) + return ret; + + ptp_data->clock = ptp_clock_register(&ptp_data->caps, dev->dev); + if (IS_ERR_OR_NULL(ptp_data->clock)) + return PTR_ERR(ptp_data->clock); + + ret = ksz_rmw16(dev, REG_PTP_MSG_CONF1, PTP_802_1AS, PTP_802_1AS); + if (ret) + goto error_unregister_clock; + + return 0; + +error_unregister_clock: + ptp_clock_unregister(ptp_data->clock); + return ret; +} + +void ksz_ptp_clock_unregister(struct dsa_switch *ds) +{ + struct ksz_device *dev = ds->priv; + struct ksz_ptp_data *ptp_data; + + ptp_data = &dev->ptp_data; + + if (ptp_data->clock) + ptp_clock_unregister(ptp_data->clock); +} + +MODULE_AUTHOR("Christian Eggers "); +MODULE_AUTHOR("Arun Ramadoss "); +MODULE_DESCRIPTION("PTP support for KSZ switch"); +MODULE_LICENSE("GPL"); diff --git a/drivers/net/dsa/microchip/ksz_ptp.h b/drivers/net/dsa/microchip/ksz_ptp.h new file mode 100644 index 000000000000..ea9fa46caa01 --- /dev/null +++ b/drivers/net/dsa/microchip/ksz_ptp.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Microchip KSZ PTP Implementation + * Copyright (C) 2022 Microchip Technology Inc. + */ + +#ifndef _NET_DSA_DRIVERS_KSZ_PTP_H +#define _NET_DSA_DRIVERS_KSZ_PTP_H + +#if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP) + +#include + +struct ksz_ptp_data { + struct ptp_clock_info caps; + struct ptp_clock *clock; + /* Serializes all operations on the PTP hardware clock */ + struct mutex lock; +}; + +int ksz_ptp_clock_register(struct dsa_switch *ds); + +void ksz_ptp_clock_unregister(struct dsa_switch *ds); + +int ksz_get_ts_info(struct dsa_switch *ds, int port, + struct ethtool_ts_info *ts); + +#else + +struct ksz_ptp_data { + /* Serializes all operations on the PTP hardware clock */ + struct mutex lock; +}; + +static inline int ksz_ptp_clock_register(struct dsa_switch *ds) +{ + return 0; +} + +static inline void ksz_ptp_clock_unregister(struct dsa_switch *ds) { } + +#define ksz_get_ts_info NULL + +#endif /* End of CONFIG_NET_DSA_MICROCHIP_KSZ_PTP */ + +#endif diff --git a/drivers/net/dsa/microchip/ksz_ptp_reg.h b/drivers/net/dsa/microchip/ksz_ptp_reg.h new file mode 100644 index 000000000000..e578a0006ecf --- /dev/null +++ b/drivers/net/dsa/microchip/ksz_ptp_reg.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Microchip KSZ PTP register definitions + * Copyright (C) 2022 Microchip Technology Inc. + */ + +#ifndef __KSZ_PTP_REGS_H +#define __KSZ_PTP_REGS_H + +/* 5 - PTP Clock */ +#define REG_PTP_CLK_CTRL 0x0500 + +#define PTP_STEP_ADJ BIT(6) +#define PTP_STEP_DIR BIT(5) +#define PTP_READ_TIME BIT(4) +#define PTP_LOAD_TIME BIT(3) +#define PTP_CLK_ADJ_ENABLE BIT(2) +#define PTP_CLK_ENABLE BIT(1) +#define PTP_CLK_RESET BIT(0) + +#define REG_PTP_RTC_SUB_NANOSEC__2 0x0502 + +#define PTP_RTC_SUB_NANOSEC_M 0x0007 +#define PTP_RTC_0NS 0x00 + +#define REG_PTP_RTC_NANOSEC 0x0504 +#define REG_PTP_RTC_NANOSEC_H 0x0504 +#define REG_PTP_RTC_NANOSEC_L 0x0506 + +#define REG_PTP_RTC_SEC 0x0508 +#define REG_PTP_RTC_SEC_H 0x0508 +#define REG_PTP_RTC_SEC_L 0x050A + +#define REG_PTP_SUBNANOSEC_RATE 0x050C +#define REG_PTP_SUBNANOSEC_RATE_H 0x050C +#define PTP_SUBNANOSEC_M 0x3FFFFFFF + +#define PTP_RATE_DIR BIT(31) +#define PTP_TMP_RATE_ENABLE BIT(30) + +#define REG_PTP_SUBNANOSEC_RATE_L 0x050E + +#define REG_PTP_RATE_DURATION 0x0510 +#define REG_PTP_RATE_DURATION_H 0x0510 +#define REG_PTP_RATE_DURATION_L 0x0512 + +#define REG_PTP_MSG_CONF1 0x0514 + +#define PTP_802_1AS BIT(7) +#define PTP_ENABLE BIT(6) +#define PTP_ETH_ENABLE BIT(5) +#define PTP_IPV4_UDP_ENABLE BIT(4) +#define PTP_IPV6_UDP_ENABLE BIT(3) +#define PTP_TC_P2P BIT(2) +#define PTP_MASTER BIT(1) +#define PTP_1STEP BIT(0) + +#endif From patchwork Mon Nov 28 10:32:17 2022 Content-Type: text/plain; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id hs4-20020a1709073e8400b0078db3ce1e59si10143213ejc.38.2022.11.28.02.34.47; Mon, 28 Nov 2022 02:35:10 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=g4rI7Gse; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230325AbiK1Kdj (ORCPT + 99 others); Mon, 28 Nov 2022 05:33:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34658 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230314AbiK1KdT (ORCPT ); Mon, 28 Nov 2022 05:33:19 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6AE99165BF; Mon, 28 Nov 2022 02:33:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1669631595; x=1701167595; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0jWyCeJ8WBlrBWXB2TOdnjMx3E3TGNkmMzFIqVKoNmA=; b=g4rI7Gsedncb9kPuFjYwTPcYFzBntTZTOy4jvUdxT3FcoiyEkyMyfIHv z6mk6ofMpU9jw+EqelQKkfx63c/xepaGCO208LvDqaAHxRi28zU45jceX pwPamR8a5Eu1n638tRnCzx338OannrKUv6PR5c9Ncb9x73j833GGNX9wb NrvN4oIw2zNH2r+r4jK3+HUE6TGwwdASA/KCfi1+7YkGrC7IbxGuMzDAu dvp90FeoWia7UOhhPJzhEXS1qb6/Y10wHXCgF54Bymm2gma29J2NCmr0w uKYi8SgV7539Jio3Hju4+ufBuOVf/eX7uo9MWpNibQ+YNJBXEEFLVlP8P g==; X-IronPort-AV: E=Sophos;i="5.96,200,1665471600"; d="scan'208";a="125375559" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Nov 2022 03:33:14 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 28 Nov 2022 03:33:13 -0700 Received: from CHE-LT-I17769U.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 28 Nov 2022 03:33:07 -0700 From: Arun Ramadoss To: , CC: , , , , , , , , , , , , , Subject: [Patch net-next v1 02/12] net: dsa: microchip: ptp: Initial hardware time stamping support Date: Mon, 28 Nov 2022 16:02:17 +0530 Message-ID: <20221128103227.23171-3-arun.ramadoss@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221128103227.23171-1-arun.ramadoss@microchip.com> References: <20221128103227.23171-1-arun.ramadoss@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750735740350446500?= X-GMAIL-MSGID: =?utf-8?q?1750735740350446500?= From: Christian Eggers This patch adds the routine for get_ts_info, hwstamp_get, set. This enables the PTP support towards userspace applications such as linuxptp. Tx timestamping can be enabled per port and Rx timestamping enabled globally. Signed-off-by: Christian Eggers Co-developed-by: Arun Ramadoss Signed-off-by: Arun Ramadoss --- RFC v2 -> Patch v1 - moved tagger set and get function to separate patch - Removed unnecessary comments --- drivers/net/dsa/microchip/ksz_common.c | 2 + drivers/net/dsa/microchip/ksz_common.h | 4 ++ drivers/net/dsa/microchip/ksz_ptp.c | 77 +++++++++++++++++++++++++- drivers/net/dsa/microchip/ksz_ptp.h | 14 +++++ 4 files changed, 95 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c index 2d09cd141db6..7b85b258270c 100644 --- a/drivers/net/dsa/microchip/ksz_common.c +++ b/drivers/net/dsa/microchip/ksz_common.c @@ -2873,6 +2873,8 @@ static const struct dsa_switch_ops ksz_switch_ops = { .port_change_mtu = ksz_change_mtu, .port_max_mtu = ksz_max_mtu, .get_ts_info = ksz_get_ts_info, + .port_hwtstamp_get = ksz_hwtstamp_get, + .port_hwtstamp_set = ksz_hwtstamp_set, }; struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h index 5a6bfd42c6f9..cd20f39a565f 100644 --- a/drivers/net/dsa/microchip/ksz_common.h +++ b/drivers/net/dsa/microchip/ksz_common.h @@ -103,6 +103,10 @@ struct ksz_port { struct ksz_device *ksz_dev; struct ksz_irq pirq; u8 num; +#if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP) + u8 hwts_tx_en; + bool hwts_rx_en; +#endif }; struct ksz_device { diff --git a/drivers/net/dsa/microchip/ksz_ptp.c b/drivers/net/dsa/microchip/ksz_ptp.c index c737635ca266..a41418c6adf6 100644 --- a/drivers/net/dsa/microchip/ksz_ptp.c +++ b/drivers/net/dsa/microchip/ksz_ptp.c @@ -36,15 +36,88 @@ int ksz_get_ts_info(struct dsa_switch *ds, int port, struct ethtool_ts_info *ts) SOF_TIMESTAMPING_RX_HARDWARE | SOF_TIMESTAMPING_RAW_HARDWARE; - ts->tx_types = BIT(HWTSTAMP_TX_OFF); + ts->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ONESTEP_P2P); - ts->rx_filters = BIT(HWTSTAMP_FILTER_NONE); + ts->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL); ts->phc_index = ptp_clock_index(ptp_data->clock); return 0; } +int ksz_hwtstamp_get(struct dsa_switch *ds, int port, struct ifreq *ifr) +{ + struct ksz_device *dev = ds->priv; + struct hwtstamp_config config; + + config.flags = 0; + + config.tx_type = dev->ports[port].hwts_tx_en; + + if (dev->ports[port].hwts_rx_en) + config.rx_filter = HWTSTAMP_FILTER_ALL; + else + config.rx_filter = HWTSTAMP_FILTER_NONE; + + return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? + -EFAULT : 0; +} + +static int ksz_set_hwtstamp_config(struct ksz_device *dev, int port, + struct hwtstamp_config *config) +{ + struct ksz_port *prt = &dev->ports[port]; + + if (config->flags) + return -EINVAL; + + switch (config->tx_type) { + case HWTSTAMP_TX_OFF: + case HWTSTAMP_TX_ONESTEP_P2P: + prt->hwts_tx_en = config->tx_type; + break; + default: + return -ERANGE; + } + + switch (config->rx_filter) { + case HWTSTAMP_FILTER_NONE: + prt->hwts_rx_en = false; + break; + default: + prt->hwts_rx_en = true; + break; + } + + return 0; +} + +int ksz_hwtstamp_set(struct dsa_switch *ds, int port, struct ifreq *ifr) +{ + struct ksz_device *dev = ds->priv; + struct ksz_ptp_data *ptp_data; + struct hwtstamp_config config; + int ret; + + ptp_data = &dev->ptp_data; + + mutex_lock(&ptp_data->lock); + + ret = copy_from_user(&config, ifr->ifr_data, sizeof(config)); + if (ret) + goto error_return; + + ret = ksz_set_hwtstamp_config(dev, port, &config); + if (ret) + goto error_return; + + ret = copy_to_user(ifr->ifr_data, &config, sizeof(config)); + +error_return: + mutex_unlock(&ptp_data->lock); + return ret; +} + static int _ksz_ptp_gettime(struct ksz_device *dev, struct timespec64 *ts) { u32 nanoseconds; diff --git a/drivers/net/dsa/microchip/ksz_ptp.h b/drivers/net/dsa/microchip/ksz_ptp.h index ea9fa46caa01..17f455c3b2c5 100644 --- a/drivers/net/dsa/microchip/ksz_ptp.h +++ b/drivers/net/dsa/microchip/ksz_ptp.h @@ -23,6 +23,8 @@ void ksz_ptp_clock_unregister(struct dsa_switch *ds); int ksz_get_ts_info(struct dsa_switch *ds, int port, struct ethtool_ts_info *ts); +int ksz_hwtstamp_get(struct dsa_switch *ds, int port, struct ifreq *ifr); +int ksz_hwtstamp_set(struct dsa_switch *ds, int port, struct ifreq *ifr); #else @@ -40,6 +42,18 @@ static inline void ksz_ptp_clock_unregister(struct dsa_switch *ds) { } #define ksz_get_ts_info NULL +static inline int ksz_hwtstamp_get(struct dsa_switch *ds, int port, + struct ifreq *ifr) +{ + return -EOPNOTSUPP; +} + +static inline int ksz_hwtstamp_set(struct dsa_switch *ds, int port, + struct ifreq *ifr) +{ + return -EOPNOTSUPP; +} + #endif /* End of CONFIG_NET_DSA_MICROCHIP_KSZ_PTP */ #endif From patchwork Mon Nov 28 10:32:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun Ramadoss X-Patchwork-Id: 26614 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5564937wrr; Mon, 28 Nov 2022 02:35:22 -0800 (PST) X-Google-Smtp-Source: AA0mqf7w6MNAGLG+4fWYcmeYLixdEz/4s6VBf4a+VPWZhz+9tn/Y7s6HwGxHdede21FODWbg9KXk X-Received: by 2002:a17:907:9854:b0:7bc:30e0:6bea with SMTP id jj20-20020a170907985400b007bc30e06beamr14394655ejc.49.1669631722330; Mon, 28 Nov 2022 02:35:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669631722; cv=none; d=google.com; s=arc-20160816; b=zWLrCgUzKmcPyGKQl4gxxc5CJOyB6935NtafWfqi29Eordhr9VEr8Pn95/jcJdchrd +7g3+muN3n7inUFotb9JfMoZHsMCNiLrVk2j++edziI4pQ2l6GpQdqmEduMwSUguixh6 27QM4CRLPoVVI6YbaxdArWq5ASeVURsGyRNq921nrsgeYiF6U4ngjKtE+I0G7VzmTrDV 3HrPSplY405hJrJDP3be7t7GoX/db9ZVsha9eRCMSa9QCMvK3Cem1hRHxs8ADl9xxCVU 2q52UhJjQ7+pf2lT2btPswCmPku7h55kHSocNwJih3VyFuKJ+OU9L9rMGU2kmXenxz53 MQRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=1tnA5cRe5rFClAMHVVOnmfGwfvwhMy7zXz4rtSol6Gw=; b=CLc+usp5S78I1nUx9bVy9QfnZ2NXRAJ3PYdd1nUU6siHJvW4mWBJ63u0+zTMroNy9c vHoIfsAhBrQs/H4AvLdEQdK+uvE8T1kESJPJiw0wCr0Xfke4/LpuPvFjNg3SjYYm8nxx qW93l0m/icR87TG83G/mpSkabRc7HwLZ/f1duCBRGo0dIdMluzyQDxSNFxRML3+Bsl58 Uho7gczmS6wHCmW4iTtAbJ/0tPY5acP+kLdpoPUfM0ZhPDJor7dIEK9jViD/tiCwxo/4 sWwlafdQqXnv2Mytvd8D5ulQFPu0c1NawsL2sN6/6wTJTDVl4O3yGfzlqeEwdQGGWDA1 opcg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=csCtWppW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id p8-20020a50cd88000000b004672d4e4ff2si9491591edi.171.2022.11.28.02.34.58; Mon, 28 Nov 2022 02:35:22 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=csCtWppW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230317AbiK1Kd6 (ORCPT + 99 others); Mon, 28 Nov 2022 05:33:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230301AbiK1Kdh (ORCPT ); Mon, 28 Nov 2022 05:33:37 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D94DD64F7; Mon, 28 Nov 2022 02:33:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1669631607; x=1701167607; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wMKSq2q/W0rxs4b3EUijFn064uKZrYFjZjGvrT9dQCE=; b=csCtWppWbLJg49grSQQanmP7i1xNZAvhT/aLNRTB3Pkcnb64SAdKVwGY Rv5KxmocDjy1HPgvrCPJpHXX0WUQCTM673KewTjax82OldxcVHhx/kpQA TVsREWX6TJb2RplG6Fn1u///Z1OHb0F5fsXZOguyQtwL0BbTP7oxZjmOY Gpb62CgSlPT/RdfpWbVIcJABm3EQtQ2s04m/xi1i8iumfWGB0WIt1RnDE t3b8I0az0B9r0EtBC3/jBEJ7CuJhuXlUubTlGChjy0cEpi0kip1aBwkB7 dKcVIDDn3UOlfdB3M+v8/0P+ukwB0vVyCFnvGdEZTC9vc5jqHM2fNIkz7 w==; X-IronPort-AV: E=Sophos;i="5.96,200,1665471600"; d="scan'208";a="185453903" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Nov 2022 03:33:26 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 28 Nov 2022 03:33:23 -0700 Received: from CHE-LT-I17769U.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 28 Nov 2022 03:33:18 -0700 From: Arun Ramadoss To: , CC: , , , , , , , , , , , , , Subject: [Patch net-next v1 03/12] net: dsa: microchip: ptp: add 4 bytes in tail tag when ptp enabled Date: Mon, 28 Nov 2022 16:02:18 +0530 Message-ID: <20221128103227.23171-4-arun.ramadoss@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221128103227.23171-1-arun.ramadoss@microchip.com> References: <20221128103227.23171-1-arun.ramadoss@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750735752879057234?= X-GMAIL-MSGID: =?utf-8?q?1750735752879057234?= If PTP is enabled in the hardware, then 4 bytes are added in the tail tag. When PTP is enabled and 4 bytes are not added then messages are corrupted. Signed-off-by: Arun Ramadoss --- Patch v1 - Patch is new --- MAINTAINERS | 1 + drivers/net/dsa/microchip/ksz_common.h | 1 - drivers/net/dsa/microchip/ksz_ptp.c | 24 +++++-- include/linux/dsa/ksz_common.h | 23 ++++++ net/dsa/tag_ksz.c | 99 ++++++++++++++++++++++++-- 5 files changed, 136 insertions(+), 12 deletions(-) create mode 100644 include/linux/dsa/ksz_common.h diff --git a/MAINTAINERS b/MAINTAINERS index 61fe86968111..721d2c5dfa46 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13515,6 +13515,7 @@ S: Maintained F: Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml F: Documentation/devicetree/bindings/net/dsa/microchip,lan937x.yaml F: drivers/net/dsa/microchip/* +F: include/linux/dsa/ksz_common.h F: include/linux/platform_data/microchip-ksz.h F: net/dsa/tag_ksz.c diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h index cd20f39a565f..4c5b35a7883c 100644 --- a/drivers/net/dsa/microchip/ksz_common.h +++ b/drivers/net/dsa/microchip/ksz_common.h @@ -105,7 +105,6 @@ struct ksz_port { u8 num; #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP) u8 hwts_tx_en; - bool hwts_rx_en; #endif }; diff --git a/drivers/net/dsa/microchip/ksz_ptp.c b/drivers/net/dsa/microchip/ksz_ptp.c index a41418c6adf6..184aa57a8489 100644 --- a/drivers/net/dsa/microchip/ksz_ptp.c +++ b/drivers/net/dsa/microchip/ksz_ptp.c @@ -3,6 +3,7 @@ * Copyright (C) 2022 Microchip Technology Inc. */ +#include #include #include #include @@ -19,6 +20,16 @@ #define KSZ_PTP_INC_NS 40 /* HW clock is incremented every 40 ns (by 40) */ #define KSZ_PTP_SUBNS_BITS 32 +static int ksz_ptp_enable_mode(struct ksz_device *dev, bool enable) +{ + u16 data = 0; + + if (enable) + data = PTP_ENABLE; + + return ksz_rmw16(dev, REG_PTP_MSG_CONF1, PTP_ENABLE, data); +} + /* The function is return back the capability of timestamping feature when * requested through ethtool -T utility */ @@ -47,6 +58,7 @@ int ksz_get_ts_info(struct dsa_switch *ds, int port, struct ethtool_ts_info *ts) int ksz_hwtstamp_get(struct dsa_switch *ds, int port, struct ifreq *ifr) { + struct ksz_tagger_data *tagger_data = ksz_tagger_data(ds); struct ksz_device *dev = ds->priv; struct hwtstamp_config config; @@ -54,7 +66,7 @@ int ksz_hwtstamp_get(struct dsa_switch *ds, int port, struct ifreq *ifr) config.tx_type = dev->ports[port].hwts_tx_en; - if (dev->ports[port].hwts_rx_en) + if (tagger_data->hwtstamp_get_state(ds)) config.rx_filter = HWTSTAMP_FILTER_ALL; else config.rx_filter = HWTSTAMP_FILTER_NONE; @@ -66,7 +78,9 @@ int ksz_hwtstamp_get(struct dsa_switch *ds, int port, struct ifreq *ifr) static int ksz_set_hwtstamp_config(struct ksz_device *dev, int port, struct hwtstamp_config *config) { + struct ksz_tagger_data *tagger_data = ksz_tagger_data(dev->ds); struct ksz_port *prt = &dev->ports[port]; + bool rx_on; if (config->flags) return -EINVAL; @@ -82,14 +96,16 @@ static int ksz_set_hwtstamp_config(struct ksz_device *dev, int port, switch (config->rx_filter) { case HWTSTAMP_FILTER_NONE: - prt->hwts_rx_en = false; + rx_on = false; break; default: - prt->hwts_rx_en = true; + rx_on = true; break; } - return 0; + tagger_data->hwtstamp_set_state(dev->ds, rx_on); + + return ksz_ptp_enable_mode(dev, rx_on); } int ksz_hwtstamp_set(struct dsa_switch *ds, int port, struct ifreq *ifr) diff --git a/include/linux/dsa/ksz_common.h b/include/linux/dsa/ksz_common.h new file mode 100644 index 000000000000..62996860b887 --- /dev/null +++ b/include/linux/dsa/ksz_common.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Microchip switch tag common header + * + * Copyright (C) 2022 Microchip Technology Inc. + */ + +#ifndef _NET_DSA_KSZ_COMMON_H_ +#define _NET_DSA_KSZ_COMMON_H_ + +#include + +struct ksz_tagger_data { + bool (*hwtstamp_get_state)(struct dsa_switch *ds); + void (*hwtstamp_set_state)(struct dsa_switch *ds, bool on); +}; + +static inline struct ksz_tagger_data * +ksz_tagger_data(struct dsa_switch *ds) +{ + return ds->tagger_data; +} + +#endif /* _NET_DSA_KSZ_COMMON_H_ */ diff --git a/net/dsa/tag_ksz.c b/net/dsa/tag_ksz.c index 0f6ae143afc9..828af38f0598 100644 --- a/net/dsa/tag_ksz.c +++ b/net/dsa/tag_ksz.c @@ -4,6 +4,7 @@ * Copyright (c) 2017 Microchip Technology */ +#include #include #include #include @@ -16,9 +17,66 @@ #define LAN937X_NAME "lan937x" /* Typically only one byte is used for tail tag. */ +#define KSZ_PTP_TAG_LEN 4 #define KSZ_EGRESS_TAG_LEN 1 #define KSZ_INGRESS_TAG_LEN 1 +#define KSZ_HWTS_EN 0 + +struct ksz_tagger_private { + struct ksz_tagger_data data; /* Must be first */ + unsigned long state; +}; + +static struct ksz_tagger_private * +ksz_tagger_private(struct dsa_switch *ds) +{ + return ds->tagger_data; +} + +static bool ksz_hwtstamp_get_state(struct dsa_switch *ds) +{ + struct ksz_tagger_private *priv = ksz_tagger_private(ds); + + return test_bit(KSZ_HWTS_EN, &priv->state); +} + +static void ksz_hwtstamp_set_state(struct dsa_switch *ds, bool on) +{ + struct ksz_tagger_private *priv = ksz_tagger_private(ds); + + if (on) + set_bit(KSZ_HWTS_EN, &priv->state); + else + clear_bit(KSZ_HWTS_EN, &priv->state); +} + +static void ksz_disconnect(struct dsa_switch *ds) +{ + struct ksz_tagger_private *priv = ds->tagger_data; + + kfree(priv); + ds->tagger_data = NULL; +} + +static int ksz_connect(struct dsa_switch *ds) +{ + struct ksz_tagger_data *tagger_data; + struct ksz_tagger_private *priv; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + /* Export functions for switch driver use */ + tagger_data = &priv->data; + tagger_data->hwtstamp_get_state = ksz_hwtstamp_get_state; + tagger_data->hwtstamp_set_state = ksz_hwtstamp_set_state; + ds->tagger_data = priv; + + return 0; +} + static struct sk_buff *ksz_common_rcv(struct sk_buff *skb, struct net_device *dev, unsigned int port, unsigned int len) @@ -91,10 +149,11 @@ DSA_TAG_DRIVER(ksz8795_netdev_ops); MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_KSZ8795, KSZ8795_NAME); /* - * For Ingress (Host -> KSZ9477), 2 bytes are added before FCS. + * For Ingress (Host -> KSZ9477), 2/6 bytes are added before FCS. * --------------------------------------------------------------------------- - * DA(6bytes)|SA(6bytes)|....|Data(nbytes)|tag0(1byte)|tag1(1byte)|FCS(4bytes) + * DA(6bytes)|SA(6bytes)|....|Data(nbytes)|ts(4bytes)|tag0(1byte)|tag1(1byte)|FCS(4bytes) * --------------------------------------------------------------------------- + * ts : time stamp (Present only if PTP is enabled in the Hardware) * tag0 : Prioritization (not used now) * tag1 : each bit represents port (eg, 0x01=port1, 0x02=port2, 0x10=port5) * @@ -113,6 +172,19 @@ MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_KSZ8795, KSZ8795_NAME); #define KSZ9477_TAIL_TAG_OVERRIDE BIT(9) #define KSZ9477_TAIL_TAG_LOOKUP BIT(10) +/* Time stamp tag is only inserted if PTP is enabled in hardware. */ +static void ksz_xmit_timestamp(struct dsa_port *dp, struct sk_buff *skb) +{ + struct ksz_tagger_private *priv; + + priv = ksz_tagger_private(dp->ds); + + if (!test_bit(KSZ_HWTS_EN, &priv->state)) + return; + + put_unaligned_be32(0, skb_put(skb, KSZ_PTP_TAG_LEN)); +} + static struct sk_buff *ksz9477_xmit(struct sk_buff *skb, struct net_device *dev) { @@ -125,6 +197,8 @@ static struct sk_buff *ksz9477_xmit(struct sk_buff *skb, return NULL; /* Tag encoding */ + ksz_xmit_timestamp(dp, skb); + tag = skb_put(skb, KSZ9477_INGRESS_TAG_LEN); addr = skb_mac_header(skb); @@ -157,7 +231,9 @@ static const struct dsa_device_ops ksz9477_netdev_ops = { .proto = DSA_TAG_PROTO_KSZ9477, .xmit = ksz9477_xmit, .rcv = ksz9477_rcv, - .needed_tailroom = KSZ9477_INGRESS_TAG_LEN, + .connect = ksz_connect, + .disconnect = ksz_disconnect, + .needed_tailroom = KSZ9477_INGRESS_TAG_LEN + KSZ_PTP_TAG_LEN, }; DSA_TAG_DRIVER(ksz9477_netdev_ops); @@ -177,6 +253,8 @@ static struct sk_buff *ksz9893_xmit(struct sk_buff *skb, return NULL; /* Tag encoding */ + ksz_xmit_timestamp(dp, skb); + tag = skb_put(skb, KSZ_INGRESS_TAG_LEN); addr = skb_mac_header(skb); @@ -193,16 +271,19 @@ static const struct dsa_device_ops ksz9893_netdev_ops = { .proto = DSA_TAG_PROTO_KSZ9893, .xmit = ksz9893_xmit, .rcv = ksz9477_rcv, - .needed_tailroom = KSZ_INGRESS_TAG_LEN, + .connect = ksz_connect, + .disconnect = ksz_disconnect, + .needed_tailroom = KSZ_INGRESS_TAG_LEN + KSZ_PTP_TAG_LEN, }; DSA_TAG_DRIVER(ksz9893_netdev_ops); MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_KSZ9893, KSZ9893_NAME); -/* For xmit, 2 bytes are added before FCS. +/* For xmit, 2/6 bytes are added before FCS. * --------------------------------------------------------------------------- - * DA(6bytes)|SA(6bytes)|....|Data(nbytes)|tag0(1byte)|tag1(1byte)|FCS(4bytes) + * DA(6bytes)|SA(6bytes)|....|Data(nbytes)|ts(4bytes)|tag0(1byte)|tag1(1byte)|FCS(4bytes) * --------------------------------------------------------------------------- + * ts : time stamp (Present only if PTP is enabled in the Hardware) * tag0 : represents tag override, lookup and valid * tag1 : each bit represents port (eg, 0x01=port1, 0x02=port2, 0x80=port8) * @@ -231,6 +312,8 @@ static struct sk_buff *lan937x_xmit(struct sk_buff *skb, if (skb->ip_summed == CHECKSUM_PARTIAL && skb_checksum_help(skb)) return NULL; + ksz_xmit_timestamp(dp, skb); + tag = skb_put(skb, LAN937X_EGRESS_TAG_LEN); val = BIT(dp->index); @@ -251,7 +334,9 @@ static const struct dsa_device_ops lan937x_netdev_ops = { .proto = DSA_TAG_PROTO_LAN937X, .xmit = lan937x_xmit, .rcv = ksz9477_rcv, - .needed_tailroom = LAN937X_EGRESS_TAG_LEN, + .connect = ksz_connect, + .disconnect = ksz_disconnect, + .needed_tailroom = LAN937X_EGRESS_TAG_LEN + KSZ_PTP_TAG_LEN, }; DSA_TAG_DRIVER(lan937x_netdev_ops); From patchwork Mon Nov 28 10:32:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun Ramadoss X-Patchwork-Id: 26615 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5565102wrr; Mon, 28 Nov 2022 02:35:43 -0800 (PST) X-Google-Smtp-Source: AA0mqf43CMiI9PtcDQAP9YZjQcrdwDdX5Gbz/akJhoh1F3OrwzE+Zh4Jv23rTw3CoWwIjZLYMVTN X-Received: by 2002:a17:906:cedc:b0:7ad:e8dd:837c with SMTP id si28-20020a170906cedc00b007ade8dd837cmr45174209ejb.264.1669631743002; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id sb7-20020a1709076d8700b0078d85777c4fsi9788747ejc.700.2022.11.28.02.35.19; Mon, 28 Nov 2022 02:35:42 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=loicr4Yt; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230284AbiK1KeK (ORCPT + 99 others); Mon, 28 Nov 2022 05:34:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35146 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230384AbiK1Kdj (ORCPT ); Mon, 28 Nov 2022 05:33:39 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0A6059584; Mon, 28 Nov 2022 02:33:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1669631617; x=1701167617; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FVqWV4woybKDyxGqRG0ty0ONw8f1+jYYhKXZtMlz+mc=; b=loicr4YtUnGgguNHBKAjh/yFmmSl6Qegh+2nTjycHIY4oZWbv5B7Apif uKY47RckhqogCYcYdDfVQrsjcz4iKeQUdKLki/0FTziB2WDKR7SOFyz9q ny/cEwWjY2hhJoc3K1sPvtN25G9lVoCHDA411570xtC0oqauhPmJu6u47 6pfiP4/fvpkapf6Eu5B6zxmbwpBvOr3YhOWb4KBA2k7zqI7kZZnBU7Vkv prpEHUBg7mJLHPp6SWjdFm6CUQun7KBAiKPIMf91n1oHpmOK8uGQHpAOz pBYGTkCKOLPiCGP71dEao72MbPT9It+7/SBbhT6ZJx7/nrwC6qH9/NZ7O w==; X-IronPort-AV: E=Sophos;i="5.96,200,1665471600"; d="scan'208";a="125375583" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Nov 2022 03:33:36 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 28 Nov 2022 03:33:33 -0700 Received: from CHE-LT-I17769U.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 28 Nov 2022 03:33:27 -0700 From: Arun Ramadoss To: , CC: , , , , , , , , , , , , , Subject: [Patch net-next v1 04/12] net: dsa: microchip: ptp: Manipulating absolute time using ptp hw clock Date: Mon, 28 Nov 2022 16:02:19 +0530 Message-ID: <20221128103227.23171-5-arun.ramadoss@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221128103227.23171-1-arun.ramadoss@microchip.com> References: <20221128103227.23171-1-arun.ramadoss@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750735774689522942?= X-GMAIL-MSGID: =?utf-8?q?1750735774689522942?= From: Christian Eggers This patch is used for reconstructing the absolute time from the 32bit hardware time stamping value. The do_aux ioctl is used for reading the ptp hardware clock and store it to global variable. The timestamped value in tail tag during rx and register during tx are 32 bit value (2 bit seconds and 30 bit nanoseconds). The time taken to read entire ptp clock will be time consuming. In order to speed up, the software clock is maintained. This clock time will be added to 32 bit timestamp to get the absolute time stamp. Signed-off-by: Christian Eggers Co-developed-by: Arun Ramadoss Signed-off-by: Arun Ramadoss --- RFC v1 - This patch is based on Christian Eggers Initial hardware timestamping support --- drivers/net/dsa/microchip/ksz_ptp.c | 58 ++++++++++++++++++++++++++++- drivers/net/dsa/microchip/ksz_ptp.h | 3 ++ 2 files changed, 59 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/microchip/ksz_ptp.c b/drivers/net/dsa/microchip/ksz_ptp.c index 184aa57a8489..415522ef4ce9 100644 --- a/drivers/net/dsa/microchip/ksz_ptp.c +++ b/drivers/net/dsa/microchip/ksz_ptp.c @@ -22,11 +22,20 @@ static int ksz_ptp_enable_mode(struct ksz_device *dev, bool enable) { + struct ksz_ptp_data *ptp_data = &dev->ptp_data; u16 data = 0; + int ret; - if (enable) + if (enable) { data = PTP_ENABLE; + ret = ptp_schedule_worker(ptp_data->clock, 0); + if (ret) + return ret; + } else { + ptp_cancel_worker_sync(ptp_data->clock); + } + return ksz_rmw16(dev, REG_PTP_MSG_CONF1, PTP_ENABLE, data); } @@ -200,6 +209,12 @@ static int ksz_ptp_settime(struct ptp_clock_info *ptp, goto error_return; ret = ksz_rmw16(dev, REG_PTP_CLK_CTRL, PTP_LOAD_TIME, PTP_LOAD_TIME); + if (ret) + goto error_return; + + spin_lock_bh(&ptp_data->clock_lock); + ptp_data->clock_time = *ts; + spin_unlock_bh(&ptp_data->clock_lock); error_return: mutex_unlock(&ptp_data->lock); @@ -254,6 +269,7 @@ static int ksz_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) { struct ksz_ptp_data *ptp_data = ptp_caps_to_data(ptp); struct ksz_device *dev = ptp_data_to_ksz_dev(ptp_data); + struct timespec64 delta64 = ns_to_timespec64(delta); s32 sec, nsec; u16 data16; int ret; @@ -286,15 +302,51 @@ static int ksz_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) data16 |= PTP_STEP_DIR; ret = ksz_write16(dev, REG_PTP_CLK_CTRL, data16); + if (ret) + goto error_return; + + spin_lock_bh(&ptp_data->clock_lock); + ptp_data->clock_time = timespec64_add(ptp_data->clock_time, delta64); + spin_unlock_bh(&ptp_data->clock_lock); error_return: mutex_unlock(&ptp_data->lock); return ret; } +/* Function is pointer to the do_aux_work in the ptp_clock capability */ +static long ksz_ptp_do_aux_work(struct ptp_clock_info *ptp) +{ + struct ksz_ptp_data *ptp_data = ptp_caps_to_data(ptp); + struct ksz_device *dev = ptp_data_to_ksz_dev(ptp_data); + struct timespec64 ts; + + mutex_lock(&ptp_data->lock); + _ksz_ptp_gettime(dev, &ts); + mutex_unlock(&ptp_data->lock); + + spin_lock_bh(&ptp_data->clock_lock); + ptp_data->clock_time = ts; + spin_unlock_bh(&ptp_data->clock_lock); + + return HZ; /* reschedule in 1 second */ +} + static int ksz_ptp_start_clock(struct ksz_device *dev) { - return ksz_rmw16(dev, REG_PTP_CLK_CTRL, PTP_CLK_ENABLE, PTP_CLK_ENABLE); + struct ksz_ptp_data *ptp_data = &dev->ptp_data; + int ret; + + ret = ksz_rmw16(dev, REG_PTP_CLK_CTRL, PTP_CLK_ENABLE, PTP_CLK_ENABLE); + if (ret) + return ret; + + spin_lock_bh(&ptp_data->clock_lock); + ptp_data->clock_time.tv_sec = 0; + ptp_data->clock_time.tv_nsec = 0; + spin_unlock_bh(&ptp_data->clock_lock); + + return 0; } static const struct ptp_clock_info ksz_ptp_caps = { @@ -305,6 +357,7 @@ static const struct ptp_clock_info ksz_ptp_caps = { .settime64 = ksz_ptp_settime, .adjfine = ksz_ptp_adjfine, .adjtime = ksz_ptp_adjtime, + .do_aux_work = ksz_ptp_do_aux_work, }; int ksz_ptp_clock_register(struct dsa_switch *ds) @@ -315,6 +368,7 @@ int ksz_ptp_clock_register(struct dsa_switch *ds) ptp_data = &dev->ptp_data; mutex_init(&ptp_data->lock); + spin_lock_init(&ptp_data->clock_lock); ptp_data->caps = ksz_ptp_caps; diff --git a/drivers/net/dsa/microchip/ksz_ptp.h b/drivers/net/dsa/microchip/ksz_ptp.h index 17f455c3b2c5..81fa2e8b9cf4 100644 --- a/drivers/net/dsa/microchip/ksz_ptp.h +++ b/drivers/net/dsa/microchip/ksz_ptp.h @@ -15,6 +15,9 @@ struct ksz_ptp_data { struct ptp_clock *clock; /* Serializes all operations on the PTP hardware clock */ struct mutex lock; + /* lock for accessing the clock_time */ + spinlock_t clock_lock; + struct timespec64 clock_time; }; int ksz_ptp_clock_register(struct dsa_switch *ds); From patchwork Mon Nov 28 10:32:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun Ramadoss X-Patchwork-Id: 26617 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5565327wrr; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id y18-20020a056402441200b0044f2fb68fe6si11155672eda.495.2022.11.28.02.35.51; Mon, 28 Nov 2022 02:36:14 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=HOM46A7K; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230389AbiK1KeX (ORCPT + 99 others); Mon, 28 Nov 2022 05:34:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230333AbiK1Kdr (ORCPT ); Mon, 28 Nov 2022 05:33:47 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A2D4167DB; Mon, 28 Nov 2022 02:33:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1669631626; x=1701167626; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pl1Im9ZS/3dPT9AJc/jiQN8Jiapvzp9zOKaq9TXWkbw=; b=HOM46A7KslYdox6Eik/ueL1j3IjLKruiDoYu0qD5dpUhYPdgZG8gEVrY Rq8AoP9t5v3cKnfdEoHsOzbCNdFpNnVnjC1PTWNihFZhtouMVDQjYufNl 9JdK0GlwgTju9dw0WFwV0nE+2g77gC8KF4jwBemrNDQbJyhbhuG1N6Lou m3rJGZFI5hLJxF6eFTglOTe0cS3CQp1K6d9kqaklVXQ7yhIsAhKwOuOcC HKuaUiNLbupLeN4hDfA7ZJk0bztOLk18FNXgTnv4ZzNnht8G/qSvwTeap qF6rWUJfskImd9tnC6ysqYs0hH39fTi38kk73XHgo9HFeWyyGM+IrT1vG g==; X-IronPort-AV: E=Sophos;i="5.96,200,1665471600"; d="scan'208";a="125375611" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Nov 2022 03:33:45 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 28 Nov 2022 03:33:42 -0700 Received: from CHE-LT-I17769U.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 28 Nov 2022 03:33:37 -0700 From: Arun Ramadoss To: , CC: , , , , , , , , , , , , , Subject: [Patch net-next v1 05/12] net: dsa: microchip: ptp: enable interrupt for timestamping Date: Mon, 28 Nov 2022 16:02:20 +0530 Message-ID: <20221128103227.23171-6-arun.ramadoss@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221128103227.23171-1-arun.ramadoss@microchip.com> References: <20221128103227.23171-1-arun.ramadoss@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750735807828703044?= X-GMAIL-MSGID: =?utf-8?q?1750735807828703044?= PTP Interrupt mask and status register differ from the global and port interrupt mechanism by two methods. One is that for global/port interrupt enabling we have to clear the bit but for ptp interrupt we have to set the bit. And other is bit12:0 is reserver in ptp interrupt registers. This forced to not use the generic implementation of global/port interrupt method routine. This patch implement the ptp interrupt mechanism to read the timestamp register for sync, pdelay_req and pdelay_resp. Signed-off-by: Arun Ramadoss --- RFC v2 -> Patch v1 - Moved the acking of interrupts before calling the handle_nested_irq to avoid race condition between deferred xmit and Irq threads --- drivers/net/dsa/microchip/ksz_common.c | 15 +- drivers/net/dsa/microchip/ksz_common.h | 11 ++ drivers/net/dsa/microchip/ksz_ptp.c | 200 ++++++++++++++++++++++++ drivers/net/dsa/microchip/ksz_ptp.h | 9 ++ drivers/net/dsa/microchip/ksz_ptp_reg.h | 19 +++ 5 files changed, 252 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c index 7b85b258270c..9bfd7dd5cd31 100644 --- a/drivers/net/dsa/microchip/ksz_common.c +++ b/drivers/net/dsa/microchip/ksz_common.c @@ -2014,13 +2014,17 @@ static int ksz_setup(struct dsa_switch *ds) ret = ksz_pirq_setup(dev, dp->index); if (ret) goto out_girq; + + ret = ksz_ptp_irq_setup(ds, dp->index); + if (ret) + goto out_pirq; } } ret = ksz_ptp_clock_register(ds); if (ret) { dev_err(dev->dev, "Failed to register PTP clock: %d\n", ret); - goto out_pirq; + goto out_ptpirq; } ret = ksz_mdio_register(dev); @@ -2037,6 +2041,10 @@ static int ksz_setup(struct dsa_switch *ds) out_ptp_clock_unregister: ksz_ptp_clock_unregister(ds); +out_ptpirq: + if (dev->irq > 0) + dsa_switch_for_each_user_port(dp, dev->ds) + ksz_ptp_irq_free(ds, dp->index); out_pirq: if (dev->irq > 0) dsa_switch_for_each_user_port(dp, dev->ds) @@ -2056,8 +2064,11 @@ static void ksz_teardown(struct dsa_switch *ds) ksz_ptp_clock_unregister(ds); if (dev->irq > 0) { - dsa_switch_for_each_user_port(dp, dev->ds) + dsa_switch_for_each_user_port(dp, dev->ds) { + ksz_ptp_irq_free(ds, dp->index); + ksz_irq_free(&dev->ports[dp->index].pirq); + } ksz_irq_free(&dev->girq); } diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h index 4c5b35a7883c..ffb9495e1bec 100644 --- a/drivers/net/dsa/microchip/ksz_common.h +++ b/drivers/net/dsa/microchip/ksz_common.h @@ -20,6 +20,7 @@ #define KSZ_MAX_NUM_PORTS 8 struct ksz_device; +struct ksz_port; struct vlan_table { u32 table[3]; @@ -83,6 +84,13 @@ struct ksz_irq { struct ksz_device *dev; }; +struct ksz_ptp_irq { + struct ksz_port *port; + u16 ts_reg; + char name[16]; + int irq_num; +}; + struct ksz_port { bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ bool learning; @@ -105,6 +113,8 @@ struct ksz_port { u8 num; #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP) u8 hwts_tx_en; + struct ksz_irq ptpirq; + struct ksz_ptp_irq ptpmsg_irq[3]; #endif }; @@ -606,6 +616,7 @@ static inline int is_lan937x(struct ksz_device *dev) #define REG_PORT_INT_MASK 0x001F #define PORT_SRC_PHY_INT 1 +#define PORT_SRC_PTP_INT 2 /* Regmap tables generation */ #define KSZ_SPI_OP_RD 3 diff --git a/drivers/net/dsa/microchip/ksz_ptp.c b/drivers/net/dsa/microchip/ksz_ptp.c index 415522ef4ce9..515a40c9f107 100644 --- a/drivers/net/dsa/microchip/ksz_ptp.c +++ b/drivers/net/dsa/microchip/ksz_ptp.c @@ -4,6 +4,8 @@ */ #include +#include +#include #include #include #include @@ -20,6 +22,8 @@ #define KSZ_PTP_INC_NS 40 /* HW clock is incremented every 40 ns (by 40) */ #define KSZ_PTP_SUBNS_BITS 32 +#define KSZ_PTP_INT_START 13 + static int ksz_ptp_enable_mode(struct ksz_device *dev, bool enable) { struct ksz_ptp_data *ptp_data = &dev->ptp_data; @@ -402,6 +406,202 @@ void ksz_ptp_clock_unregister(struct dsa_switch *ds) ptp_clock_unregister(ptp_data->clock); } +static irqreturn_t ksz_ptp_msg_thread_fn(int irq, void *dev_id) +{ + return IRQ_NONE; +} + +static irqreturn_t ksz_ptp_irq_thread_fn(int irq, void *dev_id) +{ + struct ksz_irq *ptpirq = dev_id; + unsigned int nhandled = 0; + struct ksz_device *dev; + unsigned int sub_irq; + u16 data; + int ret; + u8 n; + + dev = ptpirq->dev; + + ret = ksz_read16(dev, ptpirq->reg_status, &data); + if (ret) + goto out; + + /* Clear the interrupts W1C */ + ret = ksz_write16(dev, ptpirq->reg_status, data); + if (ret) + return IRQ_NONE; + + for (n = 0; n < ptpirq->nirqs; ++n) { + if (data & BIT(n + KSZ_PTP_INT_START)) { + sub_irq = irq_find_mapping(ptpirq->domain, n); + handle_nested_irq(sub_irq); + ++nhandled; + } + } + +out: + return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); +} + +static void ksz_ptp_irq_mask(struct irq_data *d) +{ + struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); + + kirq->masked &= ~BIT(d->hwirq + KSZ_PTP_INT_START); +} + +static void ksz_ptp_irq_unmask(struct irq_data *d) +{ + struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); + + kirq->masked |= BIT(d->hwirq + KSZ_PTP_INT_START); +} + +static void ksz_ptp_irq_bus_lock(struct irq_data *d) +{ + struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); + + mutex_lock(&kirq->dev->lock_irq); +} + +static void ksz_ptp_irq_bus_sync_unlock(struct irq_data *d) +{ + struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); + struct ksz_device *dev = kirq->dev; + int ret; + + ret = ksz_write16(dev, kirq->reg_mask, kirq->masked); + if (ret) + dev_err(dev->dev, "failed to change IRQ mask\n"); + + mutex_unlock(&dev->lock_irq); +} + +static const struct irq_chip ksz_ptp_irq_chip = { + .name = "ksz-irq", + .irq_mask = ksz_ptp_irq_mask, + .irq_unmask = ksz_ptp_irq_unmask, + .irq_bus_lock = ksz_ptp_irq_bus_lock, + .irq_bus_sync_unlock = ksz_ptp_irq_bus_sync_unlock, +}; + +static int ksz_ptp_irq_domain_map(struct irq_domain *d, + unsigned int irq, irq_hw_number_t hwirq) +{ + irq_set_chip_data(irq, d->host_data); + irq_set_chip_and_handler(irq, &ksz_ptp_irq_chip, handle_level_irq); + irq_set_noprobe(irq); + + return 0; +} + +static const struct irq_domain_ops ksz_ptp_irq_domain_ops = { + .map = ksz_ptp_irq_domain_map, + .xlate = irq_domain_xlate_twocell, +}; + +static int ksz_ptp_msg_irq_setup(struct ksz_port *port) +{ + u16 ts_reg[] = {REG_PTP_PORT_PDRESP_TS, REG_PTP_PORT_XDELAY_TS, + REG_PTP_PORT_SYNC_TS}; + struct ksz_device *dev = port->ksz_dev; + struct ksz_irq *ptpirq = &port->ptpirq; + struct ksz_ptp_irq *ptpmsg_irq; + int ret; + u8 n; + + for (n = 0; n < ptpirq->nirqs; n++) { + ptpmsg_irq = &port->ptpmsg_irq[n]; + + ptpmsg_irq->port = port; + ptpmsg_irq->ts_reg = dev->dev_ops->get_port_addr(port->num, + ts_reg[n]); + ptpmsg_irq->irq_num = irq_create_mapping(ptpirq->domain, n); + if (ptpmsg_irq->irq_num < 0) { + ret = ptpmsg_irq->irq_num; + goto out; + } + + snprintf(ptpmsg_irq->name, sizeof(ptpmsg_irq->name), + "PTP-MSG-%d", n); + + ret = request_threaded_irq(ptpmsg_irq->irq_num, NULL, + ksz_ptp_msg_thread_fn, + IRQF_ONESHOT | IRQF_TRIGGER_FALLING, + ptpmsg_irq->name, ptpmsg_irq); + if (ret) + goto out; + } + + return 0; + +out: + while (n--) + irq_dispose_mapping(port->ptpmsg_irq[n].irq_num); + + return ret; +} + +int ksz_ptp_irq_setup(struct dsa_switch *ds, u8 p) +{ + struct ksz_device *dev = ds->priv; + const struct ksz_dev_ops *ops = dev->dev_ops; + struct ksz_port *port = &dev->ports[p]; + struct ksz_irq *ptpirq = &port->ptpirq; + int ret; + + ptpirq->dev = dev; + ptpirq->masked = 0; + ptpirq->nirqs = 3; + ptpirq->reg_mask = ops->get_port_addr(p, REG_PTP_PORT_TX_INT_ENABLE__2); + ptpirq->reg_status = ops->get_port_addr(p, + REG_PTP_PORT_TX_INT_STATUS__2); + snprintf(ptpirq->name, sizeof(ptpirq->name), "ptp_irq-%d", p); + + ptpirq->irq_num = irq_find_mapping(port->pirq.domain, PORT_SRC_PTP_INT); + if (ptpirq->irq_num < 0) + return ptpirq->irq_num; + + ptpirq->domain = irq_domain_add_simple(dev->dev->of_node, ptpirq->nirqs, + 0, &ksz_ptp_irq_domain_ops, + ptpirq); + if (!ptpirq->domain) + return -ENOMEM; + + ret = request_threaded_irq(ptpirq->irq_num, NULL, ksz_ptp_irq_thread_fn, + IRQF_ONESHOT | IRQF_TRIGGER_FALLING, + ptpirq->name, ptpirq); + if (ret) + goto out; + + ret = ksz_ptp_msg_irq_setup(port); + if (ret) + goto out; + + return 0; + +out: + irq_dispose_mapping(ptpirq->irq_num); + + return ret; +} + +void ksz_ptp_irq_free(struct dsa_switch *ds, u8 p) +{ + struct ksz_device *dev = ds->priv; + struct ksz_port *port = &dev->ports[p]; + struct ksz_irq *ptpirq = &port->ptpirq; + u8 n; + + free_irq(ptpirq->irq_num, ptpirq); + + for (n = 0; n < ptpirq->nirqs; n++) + irq_dispose_mapping(port->ptpmsg_irq[n].irq_num); + + irq_domain_remove(ptpirq->domain); +} + MODULE_AUTHOR("Christian Eggers "); MODULE_AUTHOR("Arun Ramadoss "); MODULE_DESCRIPTION("PTP support for KSZ switch"); diff --git a/drivers/net/dsa/microchip/ksz_ptp.h b/drivers/net/dsa/microchip/ksz_ptp.h index 81fa2e8b9cf4..5cec8f2e8420 100644 --- a/drivers/net/dsa/microchip/ksz_ptp.h +++ b/drivers/net/dsa/microchip/ksz_ptp.h @@ -28,6 +28,8 @@ int ksz_get_ts_info(struct dsa_switch *ds, int port, struct ethtool_ts_info *ts); int ksz_hwtstamp_get(struct dsa_switch *ds, int port, struct ifreq *ifr); int ksz_hwtstamp_set(struct dsa_switch *ds, int port, struct ifreq *ifr); +int ksz_ptp_irq_setup(struct dsa_switch *ds, u8 p); +void ksz_ptp_irq_free(struct dsa_switch *ds, u8 p); #else @@ -57,6 +59,13 @@ static inline int ksz_hwtstamp_set(struct dsa_switch *ds, int port, return -EOPNOTSUPP; } +static inline int ksz_ptp_irq_setup(struct dsa_switch *ds, u8 p) +{ + return 0; +} + +static inline void ksz_ptp_irq_free(struct dsa_switch *ds, u8 p) {} + #endif /* End of CONFIG_NET_DSA_MICROCHIP_KSZ_PTP */ #endif diff --git a/drivers/net/dsa/microchip/ksz_ptp_reg.h b/drivers/net/dsa/microchip/ksz_ptp_reg.h index e578a0006ecf..0c5a1193e1a1 100644 --- a/drivers/net/dsa/microchip/ksz_ptp_reg.h +++ b/drivers/net/dsa/microchip/ksz_ptp_reg.h @@ -54,4 +54,23 @@ #define PTP_MASTER BIT(1) #define PTP_1STEP BIT(0) +/* Port PTP Register */ +#define REG_PTP_PORT_RX_DELAY__2 0x0C00 +#define REG_PTP_PORT_TX_DELAY__2 0x0C02 +#define REG_PTP_PORT_ASYM_DELAY__2 0x0C04 + +#define REG_PTP_PORT_XDELAY_TS 0x0C08 +#define REG_PTP_PORT_SYNC_TS 0x0C0C +#define REG_PTP_PORT_PDRESP_TS 0x0C10 + +#define REG_PTP_PORT_TX_INT_STATUS__2 0x0C14 +#define REG_PTP_PORT_TX_INT_ENABLE__2 0x0C16 + +#define PTP_PORT_SYNC_INT BIT(15) +#define PTP_PORT_XDELAY_REQ_INT BIT(14) +#define PTP_PORT_PDELAY_RESP_INT BIT(13) +#define KSZ_SYNC_MSG 2 +#define KSZ_XDREQ_MSG 1 +#define KSZ_PDRES_MSG 0 + #endif From patchwork Mon Nov 28 10:32:21 2022 Content-Type: text/plain; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id u13-20020a50eacd000000b00457f9c97f13si8687646edp.581.2022.11.28.02.35.37; Mon, 28 Nov 2022 02:36:00 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=ihZ+TNtj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230398AbiK1Kej (ORCPT + 99 others); Mon, 28 Nov 2022 05:34:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230357AbiK1Kdz (ORCPT ); Mon, 28 Nov 2022 05:33:55 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0AFFF1839C; Mon, 28 Nov 2022 02:33:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1669631632; x=1701167632; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yzSQCKzqqvX1+cSg/sFYh+5Sk7VWHcMcBa7T5qXDR7E=; b=ihZ+TNtjaSLgEJoZnIj/dMRBlDzr350jP8Ga17loSDlTrYLADTKBuw7P KiIxP1HiJAcp9FlvWRiU3xwrGwRCkIL4kdQSM+cwE7zRMVj0a0VGSg9nm 8HX+BGkfsCXM0dWu07Sdd1gMu1EiQUFwV87jgFeDwjW3JnvtLPQ9iQvIz WMfh31zY/cSe44OTPz6ahuajOpvB29tcgHjW3drHic/kfh+jMK6q412CO FS1FjinF9GdfDDyesPQFu1Uh/uGfj/EAkt3pcwdAIV1d6kgMZYA+uxaYx OGE8nQNhIgRU7gLkyk9O+lMMmQ3pOIBwDM/WWAvz8wGj3L3W/mZi4cR/2 A==; X-IronPort-AV: E=Sophos;i="5.96,200,1665471600"; d="scan'208";a="201649625" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Nov 2022 03:33:51 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 28 Nov 2022 03:33:51 -0700 Received: from CHE-LT-I17769U.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 28 Nov 2022 03:33:45 -0700 From: Arun Ramadoss To: , CC: , , , , , , , , , , , , , Subject: [Patch net-next v1 06/12] net: ptp: add helper for one-step P2P clocks Date: Mon, 28 Nov 2022 16:02:21 +0530 Message-ID: <20221128103227.23171-7-arun.ramadoss@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221128103227.23171-1-arun.ramadoss@microchip.com> References: <20221128103227.23171-1-arun.ramadoss@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750735792992918603?= X-GMAIL-MSGID: =?utf-8?q?1750735792992918603?= From: Christian Eggers For P2P delay measurement, the ingress time stamp of the PDelay_Req is required for the correction field of the PDelay_Resp. The application echoes back the correction field of the PDelay_Req when sending the PDelay_Resp. Some hardware (like the ZHAW InES PTP time stamping IP core) subtracts the ingress timestamp autonomously from the correction field, so that the hardware only needs to add the egress timestamp on tx. Other hardware (like the Microchip KSZ9563) reports the ingress time stamp via an interrupt and requires that the software provides this time stamp via tail-tag on tx. In order to avoid introducing a further application interface for this, the driver can simply emulate the behavior of the InES device and subtract the ingress time stamp in software from the correction field. On egress, the correction field can either be kept as it is (and the time stamp field in the tail-tag is set to zero) or move the value from the correction field back to the tail-tag. Changing the correction field requires updating the UDP checksum (if UDP is used as transport). Signed-off-by: Christian Eggers --- include/linux/ptp_classify.h | 73 ++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/include/linux/ptp_classify.h b/include/linux/ptp_classify.h index 2b6ea36ad162..e32efe3c4d66 100644 --- a/include/linux/ptp_classify.h +++ b/include/linux/ptp_classify.h @@ -10,8 +10,12 @@ #ifndef _PTP_CLASSIFY_H_ #define _PTP_CLASSIFY_H_ +#include #include +#include #include +#include +#include #define PTP_CLASS_NONE 0x00 /* not a PTP event message */ #define PTP_CLASS_V1 0x01 /* protocol version 1 */ @@ -129,6 +133,67 @@ static inline u8 ptp_get_msgtype(const struct ptp_header *hdr, return msgtype; } +/** + * ptp_check_diff8 - Computes new checksum (when altering a 64-bit field) + * @old: old field value + * @new: new field value + * @oldsum: previous checksum + * + * This function can be used to calculate a new checksum when only a single + * field is changed. Similar as ip_vs_check_diff*() in ip_vs.h. + * + * Return: Updated checksum + */ +static inline __wsum ptp_check_diff8(__be64 old, __be64 new, __wsum oldsum) +{ + __be64 diff[2] = { ~old, new }; + + return csum_partial(diff, sizeof(diff), oldsum); +} + +/** + * ptp_header_update_correction - Update PTP header's correction field + * @skb: packet buffer + * @type: type of the packet (see ptp_classify_raw()) + * @hdr: ptp header + * @correction: new correction value + * + * This updates the correction field of a PTP header and updates the UDP + * checksum (if UDP is used as transport). It is needed for hardware capable of + * one-step P2P that does not already modify the correction field of Pdelay_Req + * event messages on ingress. + */ +static inline +void ptp_header_update_correction(struct sk_buff *skb, unsigned int type, + struct ptp_header *hdr, s64 correction) +{ + __be64 correction_old; + struct udphdr *uhdr; + + /* previous correction value is required for checksum update. */ + memcpy(&correction_old, &hdr->correction, sizeof(correction_old)); + + /* write new correction value */ + put_unaligned_be64((u64)correction, &hdr->correction); + + switch (type & PTP_CLASS_PMASK) { + case PTP_CLASS_IPV4: + case PTP_CLASS_IPV6: + /* locate udp header */ + uhdr = (struct udphdr *)((char *)hdr - sizeof(struct udphdr)); + break; + default: + return; + } + + /* update checksum */ + uhdr->check = csum_fold(ptp_check_diff8(correction_old, + hdr->correction, + ~csum_unfold(uhdr->check))); + if (!uhdr->check) + uhdr->check = CSUM_MANGLED_0; +} + /** * ptp_msg_is_sync - Evaluates whether the given skb is a PTP Sync message * @skb: packet buffer @@ -166,5 +231,13 @@ static inline bool ptp_msg_is_sync(struct sk_buff *skb, unsigned int type) { return false; } + +static inline +void ptp_onestep_p2p_move_t2_to_correction(struct sk_buff *skb, + unsigned int type, + struct ptp_header *hdr, + ktime_t t2) +{ +} #endif #endif /* _PTP_CLASSIFY_H_ */ From patchwork Mon Nov 28 10:32:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun Ramadoss X-Patchwork-Id: 26618 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5565341wrr; Mon, 28 Nov 2022 02:36:17 -0800 (PST) X-Google-Smtp-Source: AA0mqf5SSmWV4wa7RSsTcQBtiPAnn3DSOn4tajcSCBhESAyJSXjhm0Bz3P5bQwah/gdbaViUPw/e X-Received: by 2002:a17:906:a143:b0:7bd:fe2a:d0e1 with SMTP id bu3-20020a170906a14300b007bdfe2ad0e1mr8051819ejb.374.1669631777126; Mon, 28 Nov 2022 02:36:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669631777; cv=none; d=google.com; s=arc-20160816; b=l7/dIdl9akGqA1JTP1ZPzoox3cqwRiojurXsYJ8ssdapdNOdRcZNE39oLsg1RPokZs dGP4jm/M54U8RqCmeLJocm7QHB5AA5GgE/9Kx3ft61+PsbBz+rtK6Nu9lXGAGAfnMxm+ sIrkV7NQYqNPJUxBF0Ne4TYfNTHsPmecB8xqKjMhtmNsAsbqyBCtP7aW2ceXPgFNbZ6L yq0SnVY7wdcRk6BUi3AK3/R9hHpVUsEwOjod5m/K21VIBnRq7yc83SAq9Df415UFVSjn 3wiSGj6B/PBIE2vHwGBozZf2B6mhYN12bdJY+YCXLe4cJrSiq3mBnPThq86ZWPnTw2EG oKeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=higLvaf8vd9OP5ttmDwR6a+RJjYUVT/dC96NqOvgTnY=; b=okfTup/CI7me4Udyoyw+nBdMhM30cD6ipqMzLWMYIMo3p14zjI/FJl0Xr9ihAAkpo0 mmUJBt+rgnvM9ZQibKU2HtdtF4oQnLI9gxloUrvWzkjZJbp3M9j6MGf7IO/+ZJ0Jq/aU ql19GMgpmisROriibEb+/ROm3ZYrzG7sFTupGx+xoeJkeb6g5JPQfN6bKOMgffbA2zdK 50Fw46p7pAyYvhBKwIzY5aWbTnyG5sfWWHJM0QTYfKNaMDkRdK2zltOqoBC11TXTCSR1 6/jX3YHQvyfsJYss2iUM/2ItQZvatSpGw2Xuq5Sxd9LoNTNaT032pH4VzTYT27IQ+l9P MzQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=f4si6kM3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id f8-20020a0564021e8800b0045eec876883si11208006edf.229.2022.11.28.02.35.54; Mon, 28 Nov 2022 02:36:17 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=f4si6kM3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230380AbiK1Kep (ORCPT + 99 others); Mon, 28 Nov 2022 05:34:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35514 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230377AbiK1KeF (ORCPT ); Mon, 28 Nov 2022 05:34:05 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 389E71AD9F; Mon, 28 Nov 2022 02:34:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1669631645; x=1701167645; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bvM6X9bOd1PO38tem0r/LfnbOxF8+mEKu+0OPpFDaMU=; b=f4si6kM3pCYFV404OQbzUqG1qvz4WFkJhgNF7YGPU5iMXtRcuf2Us9r/ eDLLnYw6XVI82Vl982YfxT5OWaXXQINps6O9+OFzX5oTmeDZdoJoW2hLK mzwrF69tdWtpmONWFte5oP3iRT/epZexTpEAIhxxz3Nyhj2Y54JUYP/p8 4+bheeCUSXIfFz3o4aFMojtiWBRRwcTLqW2zH9nOw6vabZQvrRE0XG8ZP DSztF1ik8ZHOnqfyswlnlAriH3tErXxCSKE7qUffrqh8O3V0m0d9a0t1d pXXTVB8EcuoIrblr5F/JW90PqhqjSFLKLiPLT1PjqeN2CsSIVxJO1iNTl g==; X-IronPort-AV: E=Sophos;i="5.96,200,1665471600"; d="scan'208";a="185453976" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Nov 2022 03:34:02 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 28 Nov 2022 03:33:58 -0700 Received: from CHE-LT-I17769U.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 28 Nov 2022 03:33:52 -0700 From: Arun Ramadoss To: , CC: , , , , , , , , , , , , , Subject: [Patch net-next v1 07/12] net: dsa: microchip: ptp: add packet reception timestamping Date: Mon, 28 Nov 2022 16:02:22 +0530 Message-ID: <20221128103227.23171-8-arun.ramadoss@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221128103227.23171-1-arun.ramadoss@microchip.com> References: <20221128103227.23171-1-arun.ramadoss@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750735810050138304?= X-GMAIL-MSGID: =?utf-8?q?1750735810050138304?= From: Christian Eggers This patch adds the routines for timestamping received ptp packets. Whenever the ptp packet is received, the 4 byte hardware time stamped value is append to its packet. This 4 byte value is extracted from the tail tag and reconstructed to absolute time and assigned to skb hwtstamp. Signed-off-by: Christian Eggers Co-developed-by: Arun Ramadoss Signed-off-by: Arun Ramadoss --- RFC v2 -> Patch v1 - Fixed compilation issue --- drivers/net/dsa/microchip/ksz_common.c | 13 +++++ drivers/net/dsa/microchip/ksz_ptp.c | 28 +++++++++++ drivers/net/dsa/microchip/ksz_ptp.h | 6 +++ include/linux/dsa/ksz_common.h | 15 ++++++ net/dsa/tag_ksz.c | 68 +++++++++++++++++++++++--- 5 files changed, 124 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c index 9bfd7dd5cd31..306bdc1469d2 100644 --- a/drivers/net/dsa/microchip/ksz_common.c +++ b/drivers/net/dsa/microchip/ksz_common.c @@ -5,6 +5,7 @@ * Copyright (C) 2017-2019 Microchip Technology Inc. */ +#include #include #include #include @@ -2453,6 +2454,17 @@ static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds, return proto; } +static int ksz_connect_tag_protocol(struct dsa_switch *ds, + enum dsa_tag_protocol proto) +{ + struct ksz_tagger_data *tagger_data; + + tagger_data = ksz_tagger_data(ds); + tagger_data->meta_tstamp_handler = ksz_tstamp_reconstruct; + + return 0; +} + static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, bool flag, struct netlink_ext_ack *extack) { @@ -2849,6 +2861,7 @@ static int ksz_switch_detect(struct ksz_device *dev) static const struct dsa_switch_ops ksz_switch_ops = { .get_tag_protocol = ksz_get_tag_protocol, + .connect_tag_protocol = ksz_connect_tag_protocol, .get_phy_flags = ksz_get_phy_flags, .setup = ksz_setup, .teardown = ksz_teardown, diff --git a/drivers/net/dsa/microchip/ksz_ptp.c b/drivers/net/dsa/microchip/ksz_ptp.c index 515a40c9f107..d878e922c275 100644 --- a/drivers/net/dsa/microchip/ksz_ptp.c +++ b/drivers/net/dsa/microchip/ksz_ptp.c @@ -353,6 +353,34 @@ static int ksz_ptp_start_clock(struct ksz_device *dev) return 0; } +ktime_t ksz_tstamp_reconstruct(struct dsa_switch *ds, ktime_t tstamp) +{ + struct ksz_device *dev = ds->priv; + struct timespec64 ptp_clock_time; + struct ksz_ptp_data *ptp_data; + struct timespec64 diff; + struct timespec64 ts; + + ptp_data = &dev->ptp_data; + ts = ktime_to_timespec64(tstamp); + + spin_lock_bh(&ptp_data->clock_lock); + ptp_clock_time = ptp_data->clock_time; + spin_unlock_bh(&ptp_data->clock_lock); + + /* calculate full time from partial time stamp */ + ts.tv_sec = (ptp_clock_time.tv_sec & ~3) | ts.tv_sec; + + /* find nearest possible point in time */ + diff = timespec64_sub(ts, ptp_clock_time); + if (diff.tv_sec > 2) + ts.tv_sec -= 4; + else if (diff.tv_sec < -2) + ts.tv_sec += 4; + + return timespec64_to_ktime(ts); +} + static const struct ptp_clock_info ksz_ptp_caps = { .owner = THIS_MODULE, .name = "Microchip Clock", diff --git a/drivers/net/dsa/microchip/ksz_ptp.h b/drivers/net/dsa/microchip/ksz_ptp.h index 5cec8f2e8420..13c06c24b488 100644 --- a/drivers/net/dsa/microchip/ksz_ptp.h +++ b/drivers/net/dsa/microchip/ksz_ptp.h @@ -30,6 +30,7 @@ int ksz_hwtstamp_get(struct dsa_switch *ds, int port, struct ifreq *ifr); int ksz_hwtstamp_set(struct dsa_switch *ds, int port, struct ifreq *ifr); int ksz_ptp_irq_setup(struct dsa_switch *ds, u8 p); void ksz_ptp_irq_free(struct dsa_switch *ds, u8 p); +ktime_t ksz_tstamp_reconstruct(struct dsa_switch *ds, ktime_t tstamp); #else @@ -66,6 +67,11 @@ static inline int ksz_ptp_irq_setup(struct dsa_switch *ds, u8 p) static inline void ksz_ptp_irq_free(struct dsa_switch *ds, u8 p) {} +static inline ktime_t ksz_tstamp_reconstruct(struct dsa_switch *ds, ktime_t tstamp) +{ + return 0; +} + #endif /* End of CONFIG_NET_DSA_MICROCHIP_KSZ_PTP */ #endif diff --git a/include/linux/dsa/ksz_common.h b/include/linux/dsa/ksz_common.h index 62996860b887..0be0cd903727 100644 --- a/include/linux/dsa/ksz_common.h +++ b/include/linux/dsa/ksz_common.h @@ -9,9 +9,24 @@ #include +/* All time stamps from the KSZ consist of 2 bits for seconds and 30 bits for + * nanoseconds. This is NOT the same as 32 bits for nanoseconds. + */ +#define KSZ_TSTAMP_SEC_MASK GENMASK(31, 30) +#define KSZ_TSTAMP_NSEC_MASK GENMASK(29, 0) + +static inline ktime_t ksz_decode_tstamp(u32 tstamp) +{ + u64 ns = FIELD_GET(KSZ_TSTAMP_SEC_MASK, tstamp) * NSEC_PER_SEC + + FIELD_GET(KSZ_TSTAMP_NSEC_MASK, tstamp); + + return ns_to_ktime(ns); +} + struct ksz_tagger_data { bool (*hwtstamp_get_state)(struct dsa_switch *ds); void (*hwtstamp_set_state)(struct dsa_switch *ds, bool on); + ktime_t (*meta_tstamp_handler)(struct dsa_switch *ds, ktime_t tstamp); }; static inline struct ksz_tagger_data * diff --git a/net/dsa/tag_ksz.c b/net/dsa/tag_ksz.c index 828af38f0598..41ce5ff5ed41 100644 --- a/net/dsa/tag_ksz.c +++ b/net/dsa/tag_ksz.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include "tag.h" @@ -157,10 +158,11 @@ MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_KSZ8795, KSZ8795_NAME); * tag0 : Prioritization (not used now) * tag1 : each bit represents port (eg, 0x01=port1, 0x02=port2, 0x10=port5) * - * For Egress (KSZ9477 -> Host), 1 byte is added before FCS. + * For Egress (KSZ9477 -> Host), 1/5 bytes is added before FCS. * --------------------------------------------------------------------------- - * DA(6bytes)|SA(6bytes)|....|Data(nbytes)|tag0(1byte)|FCS(4bytes) + * DA(6bytes)|SA(6bytes)|....|Data(nbytes)|ts(4bytes)|tag0(1byte)|FCS(4bytes) * --------------------------------------------------------------------------- + * ts : time stamp (Present only if bit 7 of tag0 is set) * tag0 : zero-based value represents port * (eg, 0x00=port1, 0x02=port3, 0x06=port7) */ @@ -172,6 +174,57 @@ MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_KSZ8795, KSZ8795_NAME); #define KSZ9477_TAIL_TAG_OVERRIDE BIT(9) #define KSZ9477_TAIL_TAG_LOOKUP BIT(10) +static void ksz_rcv_timestamp(struct sk_buff *skb, u8 *tag, + struct net_device *dev, unsigned int port) +{ + struct skb_shared_hwtstamps *hwtstamps = skb_hwtstamps(skb); + struct dsa_switch *ds = dev->dsa_ptr->ds; + u8 *tstamp_raw = tag - KSZ_PTP_TAG_LEN; + struct ksz_tagger_data *tagger_data; + struct ptp_header *ptp_hdr; + unsigned int ptp_type; + u8 ptp_msg_type; + ktime_t tstamp; + s64 correction; + + tagger_data = ksz_tagger_data(ds); + if (!tagger_data->meta_tstamp_handler) + return; + + /* convert time stamp and write to skb */ + tstamp = ksz_decode_tstamp(get_unaligned_be32(tstamp_raw)); + memset(hwtstamps, 0, sizeof(*hwtstamps)); + hwtstamps->hwtstamp = tagger_data->meta_tstamp_handler(ds, tstamp); + + if (skb_headroom(skb) < ETH_HLEN) + return; + + __skb_push(skb, ETH_HLEN); + ptp_type = ptp_classify_raw(skb); + __skb_pull(skb, ETH_HLEN); + + if (ptp_type == PTP_CLASS_NONE) + return; + + ptp_hdr = ptp_parse_header(skb, ptp_type); + if (!ptp_hdr) + return; + + ptp_msg_type = ptp_get_msgtype(ptp_hdr, ptp_type); + if (ptp_msg_type != PTP_MSGTYPE_PDELAY_REQ) + return; + + /* Only subtract the partial time stamp from the correction field. When + * the hardware adds the egress time stamp to the correction field of + * the PDelay_Resp message on tx, also only the partial time stamp will + * be added. + */ + correction = (s64)get_unaligned_be64(&ptp_hdr->correction); + correction -= ktime_to_ns(tstamp) << 16; + + ptp_header_update_correction(skb, ptp_type, ptp_hdr, correction); +} + /* Time stamp tag is only inserted if PTP is enabled in hardware. */ static void ksz_xmit_timestamp(struct dsa_port *dp, struct sk_buff *skb) { @@ -220,8 +273,10 @@ static struct sk_buff *ksz9477_rcv(struct sk_buff *skb, struct net_device *dev) unsigned int len = KSZ_EGRESS_TAG_LEN; /* Extra 4-bytes PTP timestamp */ - if (tag[0] & KSZ9477_PTP_TAG_INDICATION) - len += KSZ9477_PTP_TAG_LEN; + if (tag[0] & KSZ9477_PTP_TAG_INDICATION) { + ksz_rcv_timestamp(skb, tag, dev, port); + len += KSZ_PTP_TAG_LEN; + } return ksz_common_rcv(skb, dev, port, len); } @@ -287,10 +342,11 @@ MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_KSZ9893, KSZ9893_NAME); * tag0 : represents tag override, lookup and valid * tag1 : each bit represents port (eg, 0x01=port1, 0x02=port2, 0x80=port8) * - * For rcv, 1 byte is added before FCS. + * For rcv, 1/5 bytes is added before FCS. * --------------------------------------------------------------------------- - * DA(6bytes)|SA(6bytes)|....|Data(nbytes)|tag0(1byte)|FCS(4bytes) + * DA(6bytes)|SA(6bytes)|....|Data(nbytes)|ts(4bytes)|tag0(1byte)|FCS(4bytes) * --------------------------------------------------------------------------- + * ts : time stamp (Present only if bit 7 of tag0 is set) * tag0 : zero-based value represents port * (eg, 0x00=port1, 0x02=port3, 0x07=port8) */ From patchwork Mon Nov 28 10:32:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun Ramadoss X-Patchwork-Id: 26619 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5565433wrr; Mon, 28 Nov 2022 02:36:29 -0800 (PST) X-Google-Smtp-Source: AA0mqf4Jbzx2HkecZ0R1tVkqmCMrail5YCQMiBJFtEtDPlPCkTiRHrqEFC5KSwFy8cLoQZzc/LAn X-Received: by 2002:aa7:d556:0:b0:45c:6467:94e2 with SMTP id u22-20020aa7d556000000b0045c646794e2mr46173532edr.295.1669631789483; Mon, 28 Nov 2022 02:36:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669631789; cv=none; d=google.com; s=arc-20160816; b=FDvgamLN7VYY8tz4m6lEYOJwH/6WpsDQe/KHq91ncCGgd9mIkm3cV6aucS+GKgAyzq 4wkpjckMv2OqG/iw/AM6zN/FCg4v+wVFR5S2g4DFP2z6LMy3H6ALSEFQTxpc4+UkuSAz 3UeMhTpdn0AR9+ejPJS5tQqJ9uRN9to1+RT6ka/GK7M8bpzAXpOmY7ginPHyj85Zr6Gd TqVkeCaoX4OTp2k3Cu6D4wXZ2s2tHt1A9Xd9pXuIbbNJjzHXMYP4zUg6Nw1p43C9ts0B Jn7q7SvUqVrcTGh3q962Ry0PxH+qhBDTLTDGekevUHR2mUyxOc88TOvBbcQcV+fPOaOq xkAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Nns2UP7Ksw8zlKZFp+Nqn4ZnnyPxCwspK2tDQRpYA/s=; b=u/tChqNemLzNjbfPyqzSH+yRAeYkdSBDl4uKlUsGqi9IZyLQwRniNBYFYhTzkvdTh6 s7criF+DU6maJOFRnh93hDu8Hx+9LxKblNzVDTJCg5YWpm/NLFg1RnejPkL91MJ5zIzC qyvWn0vxa1x3s1gCG0ilp/dpZugslCy7AHIKICOuuczUqVifnkyZZrBJoQXMEEmw84pS uqBs9knXIqj2MybqCXtx25bR9S4T84nIbt8RXH+XgGiBcnQaYsXfFzL/PMKXmiuhuv68 EjpOYAj1m9et6Z7GbnwWuL7aswut2JX0KjteWzeHW31otGbUHUM5LDwpEG4EHufGysNt vY7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=PQWWGxCq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id t20-20020a170906179400b0078d0f88a6e9si7218929eje.284.2022.11.28.02.36.01; Mon, 28 Nov 2022 02:36:29 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=PQWWGxCq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230444AbiK1Ke5 (ORCPT + 99 others); Mon, 28 Nov 2022 05:34:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35184 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230306AbiK1KeK (ORCPT ); Mon, 28 Nov 2022 05:34:10 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7AF6D1AF29; Mon, 28 Nov 2022 02:34:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1669631649; x=1701167649; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uDRwukzuEu6dnrTk1P6v7vhE3jxsxek7mw1/PbD87Qg=; b=PQWWGxCqwoUZBuoa5w3BrV6wd/l0mXfeSQunzLvkoVVAUghRYDAdv00u 15bQ23HrZFFWeGaQ/pOOUURlci+llRT9HC0UK1b5Eg53aggAX4oc+qaJI 4hYyNJ+XqBkWerKNrY9xJT4nXI55FjinMt30ADoMn0Iu0ax2FC5Pyqi35 hNq8Zm4nXjjxBE/lgQAe0tTZxanOl323CcVqwFIPNfR5cImUVaUIuns+u Px8rfzFzyKvdwfRsaGlAiB+EsDnOx9RMKkDIqPl50pmIR3NuIMScxYXr+ xKJ+/YdKfB5FdHizdkcjRP/dlwcjlRMiPgnBujvF4RMRSF6d/e492TOAT w==; X-IronPort-AV: E=Sophos;i="5.96,200,1665471600"; d="scan'208";a="185454007" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Nov 2022 03:34:08 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 28 Nov 2022 03:34:06 -0700 Received: from CHE-LT-I17769U.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 28 Nov 2022 03:34:00 -0700 From: Arun Ramadoss To: , CC: , , , , , , , , , , , , , Subject: [Patch net-next v1 08/12] net: dsa: microchip: ptp: add packet transmission timestamping Date: Mon, 28 Nov 2022 16:02:23 +0530 Message-ID: <20221128103227.23171-9-arun.ramadoss@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221128103227.23171-1-arun.ramadoss@microchip.com> References: <20221128103227.23171-1-arun.ramadoss@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750735823193303057?= X-GMAIL-MSGID: =?utf-8?q?1750735823193303057?= From: Christian Eggers This patch adds the routines for transmission of ptp packets. When the ptp pdelay_req packet to be transmitted, it uses the deferred xmit worker to schedule the packets. After the packet is transmitted, ISR is triggered. The time at which packet transmitted is recorded to separate register. This value is reconstructed to absolute time and posted to the user application through socket error queue. Signed-off-by: Christian Eggers Co-developed-by: Arun Ramadoss Signed-off-by: Arun Ramadoss --- RFC v2 -> Patch v1 - separated the pdelay_rsp message correction update in different patch --- drivers/net/dsa/microchip/ksz_common.c | 2 + drivers/net/dsa/microchip/ksz_common.h | 3 + drivers/net/dsa/microchip/ksz_ptp.c | 120 ++++++++++++++++++++++++- drivers/net/dsa/microchip/ksz_ptp.h | 7 ++ include/linux/dsa/ksz_common.h | 14 +++ net/dsa/tag_ksz.c | 54 ++++++++++- 6 files changed, 195 insertions(+), 5 deletions(-) diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c index 306bdc1469d2..3b578a4a33de 100644 --- a/drivers/net/dsa/microchip/ksz_common.c +++ b/drivers/net/dsa/microchip/ksz_common.c @@ -2460,6 +2460,7 @@ static int ksz_connect_tag_protocol(struct dsa_switch *ds, struct ksz_tagger_data *tagger_data; tagger_data = ksz_tagger_data(ds); + tagger_data->xmit_work_fn = ksz_port_deferred_xmit; tagger_data->meta_tstamp_handler = ksz_tstamp_reconstruct; return 0; @@ -2899,6 +2900,7 @@ static const struct dsa_switch_ops ksz_switch_ops = { .get_ts_info = ksz_get_ts_info, .port_hwtstamp_get = ksz_hwtstamp_get, .port_hwtstamp_set = ksz_hwtstamp_set, + .port_txtstamp = ksz_port_txtstamp, }; struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h index ffb9495e1bec..dbde70a8990a 100644 --- a/drivers/net/dsa/microchip/ksz_common.h +++ b/drivers/net/dsa/microchip/ksz_common.h @@ -87,6 +87,7 @@ struct ksz_irq { struct ksz_ptp_irq { struct ksz_port *port; u16 ts_reg; + bool ts_en; char name[16]; int irq_num; }; @@ -115,6 +116,8 @@ struct ksz_port { u8 hwts_tx_en; struct ksz_irq ptpirq; struct ksz_ptp_irq ptpmsg_irq[3]; + ktime_t tstamp_msg; + struct completion tstamp_msg_comp; #endif }; diff --git a/drivers/net/dsa/microchip/ksz_ptp.c b/drivers/net/dsa/microchip/ksz_ptp.c index d878e922c275..5eb5aca92556 100644 --- a/drivers/net/dsa/microchip/ksz_ptp.c +++ b/drivers/net/dsa/microchip/ksz_ptp.c @@ -100,8 +100,16 @@ static int ksz_set_hwtstamp_config(struct ksz_device *dev, int port, switch (config->tx_type) { case HWTSTAMP_TX_OFF: + prt->ptpmsg_irq[KSZ_SYNC_MSG].ts_en = 0; + prt->ptpmsg_irq[KSZ_XDREQ_MSG].ts_en = 0; + prt->ptpmsg_irq[KSZ_PDRES_MSG].ts_en = 0; + prt->hwts_tx_en = HWTSTAMP_TX_OFF; + break; case HWTSTAMP_TX_ONESTEP_P2P: - prt->hwts_tx_en = config->tx_type; + prt->ptpmsg_irq[KSZ_SYNC_MSG].ts_en = 0; + prt->ptpmsg_irq[KSZ_XDREQ_MSG].ts_en = 1; + prt->ptpmsg_irq[KSZ_PDRES_MSG].ts_en = 0; + prt->hwts_tx_en = HWTSTAMP_TX_ONESTEP_P2P; break; default: return -ERANGE; @@ -147,6 +155,47 @@ int ksz_hwtstamp_set(struct dsa_switch *ds, int port, struct ifreq *ifr) return ret; } +void ksz_port_txtstamp(struct dsa_switch *ds, int port, + struct sk_buff *skb) +{ + struct ksz_device *dev = ds->priv; + struct ptp_header *hdr; + struct sk_buff *clone; + struct ksz_port *prt; + unsigned int type; + u8 ptp_msg_type; + + prt = &dev->ports[port]; + + if (!prt->hwts_tx_en) + return; + + type = ptp_classify_raw(skb); + if (type == PTP_CLASS_NONE) + return; + + hdr = ptp_parse_header(skb, type); + if (!hdr) + return; + + ptp_msg_type = ptp_get_msgtype(hdr, type); + + switch (ptp_msg_type) { + case PTP_MSGTYPE_PDELAY_REQ: + break; + + default: + return; + } + + clone = skb_clone_sk(skb); + if (!clone) + return; + + /* caching the value to be used in later */ + KSZ_SKB_CB(skb)->clone = clone; +} + static int _ksz_ptp_gettime(struct ksz_device *dev, struct timespec64 *ts) { u32 nanoseconds; @@ -381,6 +430,49 @@ ktime_t ksz_tstamp_reconstruct(struct dsa_switch *ds, ktime_t tstamp) return timespec64_to_ktime(ts); } +static void ksz_ptp_txtstamp_skb(struct ksz_device *dev, + struct ksz_port *prt, struct sk_buff *skb) +{ + struct skb_shared_hwtstamps hwtstamps = {}; + int ret; + + skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; + + /* timeout must include tstamp latency, IRQ latency and time for + * reading the time stamp. + */ + ret = wait_for_completion_timeout(&prt->tstamp_msg_comp, + msecs_to_jiffies(100)); + if (!ret) + return; + + hwtstamps.hwtstamp = prt->tstamp_msg; + skb_complete_tx_timestamp(skb, &hwtstamps); +} + +#define work_to_xmit_work(w) \ + container_of((w), struct ksz_deferred_xmit_work, work) +void ksz_port_deferred_xmit(struct kthread_work *work) +{ + struct ksz_deferred_xmit_work *xmit_work = work_to_xmit_work(work); + struct sk_buff *clone, *skb = xmit_work->skb; + struct dsa_switch *ds = xmit_work->dp->ds; + struct ksz_device *dev = ds->priv; + struct ksz_port *prt; + + prt = &dev->ports[xmit_work->dp->index]; + + clone = KSZ_SKB_CB(skb)->clone; + + reinit_completion(&prt->tstamp_msg_comp); + + dsa_enqueue_skb(skb, skb->dev); + + ksz_ptp_txtstamp_skb(dev, prt, clone); + + kfree(xmit_work); +} + static const struct ptp_clock_info ksz_ptp_caps = { .owner = THIS_MODULE, .name = "Microchip Clock", @@ -436,7 +528,29 @@ void ksz_ptp_clock_unregister(struct dsa_switch *ds) static irqreturn_t ksz_ptp_msg_thread_fn(int irq, void *dev_id) { - return IRQ_NONE; + struct ksz_ptp_irq *ptpmsg_irq = dev_id; + struct ksz_device *dev; + struct ksz_port *port; + u32 tstamp_raw; + ktime_t tstamp; + int ret; + + port = ptpmsg_irq->port; + dev = port->ksz_dev; + + if (ptpmsg_irq->ts_en) { + ret = ksz_read32(dev, ptpmsg_irq->ts_reg, &tstamp_raw); + if (ret) + return IRQ_NONE; + + tstamp = ksz_decode_tstamp(tstamp_raw); + + port->tstamp_msg = ksz_tstamp_reconstruct(dev->ds, tstamp); + + complete(&port->tstamp_msg_comp); + } + + return IRQ_HANDLED; } static irqreturn_t ksz_ptp_irq_thread_fn(int irq, void *dev_id) @@ -587,6 +701,8 @@ int ksz_ptp_irq_setup(struct dsa_switch *ds, u8 p) REG_PTP_PORT_TX_INT_STATUS__2); snprintf(ptpirq->name, sizeof(ptpirq->name), "ptp_irq-%d", p); + init_completion(&port->tstamp_msg_comp); + ptpirq->irq_num = irq_find_mapping(port->pirq.domain, PORT_SRC_PTP_INT); if (ptpirq->irq_num < 0) return ptpirq->irq_num; diff --git a/drivers/net/dsa/microchip/ksz_ptp.h b/drivers/net/dsa/microchip/ksz_ptp.h index 13c06c24b488..8bcdd4c413a8 100644 --- a/drivers/net/dsa/microchip/ksz_ptp.h +++ b/drivers/net/dsa/microchip/ksz_ptp.h @@ -28,8 +28,10 @@ int ksz_get_ts_info(struct dsa_switch *ds, int port, struct ethtool_ts_info *ts); int ksz_hwtstamp_get(struct dsa_switch *ds, int port, struct ifreq *ifr); int ksz_hwtstamp_set(struct dsa_switch *ds, int port, struct ifreq *ifr); +void ksz_port_txtstamp(struct dsa_switch *ds, int port, struct sk_buff *skb); int ksz_ptp_irq_setup(struct dsa_switch *ds, u8 p); void ksz_ptp_irq_free(struct dsa_switch *ds, u8 p); +void ksz_port_deferred_xmit(struct kthread_work *work); ktime_t ksz_tstamp_reconstruct(struct dsa_switch *ds, ktime_t tstamp); #else @@ -60,6 +62,9 @@ static inline int ksz_hwtstamp_set(struct dsa_switch *ds, int port, return -EOPNOTSUPP; } +static inline void ksz_port_txtstamp(struct dsa_switch *ds, int port, + struct sk_buff *skb) {} + static inline int ksz_ptp_irq_setup(struct dsa_switch *ds, u8 p) { return 0; @@ -67,6 +72,8 @@ static inline int ksz_ptp_irq_setup(struct dsa_switch *ds, u8 p) static inline void ksz_ptp_irq_free(struct dsa_switch *ds, u8 p) {} +static inline void ksz_port_deferred_xmit(struct kthread_work *work) {} + static inline ktime_t ksz_tstamp_reconstruct(struct dsa_switch *ds, ktime_t tstamp) { return 0; diff --git a/include/linux/dsa/ksz_common.h b/include/linux/dsa/ksz_common.h index 0be0cd903727..5f0e0c614e94 100644 --- a/include/linux/dsa/ksz_common.h +++ b/include/linux/dsa/ksz_common.h @@ -23,12 +23,26 @@ static inline ktime_t ksz_decode_tstamp(u32 tstamp) return ns_to_ktime(ns); } +struct ksz_deferred_xmit_work { + struct dsa_port *dp; + struct sk_buff *skb; + struct kthread_work work; +}; + struct ksz_tagger_data { + void (*xmit_work_fn)(struct kthread_work *work); bool (*hwtstamp_get_state)(struct dsa_switch *ds); void (*hwtstamp_set_state)(struct dsa_switch *ds, bool on); ktime_t (*meta_tstamp_handler)(struct dsa_switch *ds, ktime_t tstamp); }; +struct ksz_skb_cb { + struct sk_buff *clone; +}; + +#define KSZ_SKB_CB(skb) \ + ((struct ksz_skb_cb *)((skb)->cb)) + static inline struct ksz_tagger_data * ksz_tagger_data(struct dsa_switch *ds) { diff --git a/net/dsa/tag_ksz.c b/net/dsa/tag_ksz.c index 41ce5ff5ed41..6ed94dc0f18e 100644 --- a/net/dsa/tag_ksz.c +++ b/net/dsa/tag_ksz.c @@ -27,6 +27,7 @@ struct ksz_tagger_private { struct ksz_tagger_data data; /* Must be first */ unsigned long state; + struct kthread_worker *xmit_worker; }; static struct ksz_tagger_private * @@ -56,6 +57,7 @@ static void ksz_disconnect(struct dsa_switch *ds) { struct ksz_tagger_private *priv = ds->tagger_data; + kthread_destroy_worker(priv->xmit_worker); kfree(priv); ds->tagger_data = NULL; } @@ -63,12 +65,23 @@ static void ksz_disconnect(struct dsa_switch *ds) static int ksz_connect(struct dsa_switch *ds) { struct ksz_tagger_data *tagger_data; + struct kthread_worker *xmit_worker; struct ksz_tagger_private *priv; + int ret; priv = kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; + xmit_worker = kthread_create_worker(0, "dsa%d:%d_xmit", + ds->dst->index, ds->index); + if (IS_ERR(xmit_worker)) { + ret = PTR_ERR(xmit_worker); + kfree(priv); + return ret; + } + + priv->xmit_worker = xmit_worker; /* Export functions for switch driver use */ tagger_data = &priv->data; tagger_data->hwtstamp_get_state = ksz_hwtstamp_get_state; @@ -238,6 +251,41 @@ static void ksz_xmit_timestamp(struct dsa_port *dp, struct sk_buff *skb) put_unaligned_be32(0, skb_put(skb, KSZ_PTP_TAG_LEN)); } +/* Defer transmit if waiting for egress time stamp is required. */ +static struct sk_buff *ksz_defer_xmit(struct dsa_port *dp, struct sk_buff *skb) +{ + struct ksz_tagger_data *tagger_data = ksz_tagger_data(dp->ds); + struct ksz_tagger_private *priv = ksz_tagger_private(dp->ds); + void (*xmit_work_fn)(struct kthread_work *work); + struct sk_buff *clone = KSZ_SKB_CB(skb)->clone; + struct ksz_deferred_xmit_work *xmit_work; + struct kthread_worker *xmit_worker; + + if (!clone) + return skb; /* no deferred xmit for this packet */ + + xmit_work_fn = tagger_data->xmit_work_fn; + xmit_worker = priv->xmit_worker; + + if (!xmit_work_fn || !xmit_worker) + return NULL; + + xmit_work = kzalloc(sizeof(*xmit_work), GFP_ATOMIC); + if (!xmit_work) + return NULL; + + kthread_init_work(&xmit_work->work, xmit_work_fn); + /* Increase refcount so the kfree_skb in dsa_slave_xmit + * won't really free the packet. + */ + xmit_work->dp = dp; + xmit_work->skb = skb_get(skb); + + kthread_queue_work(xmit_worker, &xmit_work->work); + + return NULL; +} + static struct sk_buff *ksz9477_xmit(struct sk_buff *skb, struct net_device *dev) { @@ -262,7 +310,7 @@ static struct sk_buff *ksz9477_xmit(struct sk_buff *skb, *tag = cpu_to_be16(val); - return skb; + return ksz_defer_xmit(dp, skb); } static struct sk_buff *ksz9477_rcv(struct sk_buff *skb, struct net_device *dev) @@ -318,7 +366,7 @@ static struct sk_buff *ksz9893_xmit(struct sk_buff *skb, if (is_link_local_ether_addr(addr)) *tag |= KSZ9893_TAIL_TAG_OVERRIDE; - return skb; + return ksz_defer_xmit(dp, skb); } static const struct dsa_device_ops ksz9893_netdev_ops = { @@ -382,7 +430,7 @@ static struct sk_buff *lan937x_xmit(struct sk_buff *skb, put_unaligned_be16(val, tag); - return skb; + return ksz_defer_xmit(dp, skb); } static const struct dsa_device_ops lan937x_netdev_ops = { From patchwork Mon Nov 28 10:32:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun Ramadoss X-Patchwork-Id: 26620 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5565560wrr; Mon, 28 Nov 2022 02:36:45 -0800 (PST) X-Google-Smtp-Source: AA0mqf5BgMbrb7HavZyBXsHdImtoPxYpoqB5IKwmfAMgfTYmsD0hykIk42N3Uds5TwI+shyEyRSO X-Received: by 2002:a17:907:a4c3:b0:7c0:7c22:d70d with SMTP id vq3-20020a170907a4c300b007c07c22d70dmr1378472ejc.707.1669631805655; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id qk31-20020a1709077f9f00b0073d9c412570si10342942ejc.785.2022.11.28.02.36.22; Mon, 28 Nov 2022 02:36:45 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=Q1Al9jhY; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230298AbiK1KfS (ORCPT + 99 others); Mon, 28 Nov 2022 05:35:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230429AbiK1KeX (ORCPT ); Mon, 28 Nov 2022 05:34:23 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB9691B1D5; Mon, 28 Nov 2022 02:34:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1669631655; x=1701167655; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=s+HM6nj0OeoFn549ILY3kqb/6nUWbWqKuYFv92UYWEg=; b=Q1Al9jhYaKMS1bGnLXPQdeOTysOyesGIwGAGV9Lz0lHihhHvFLsa5AsV 16uj6sCNPJ3eD4fLBlA+FYAOEbVtoqX+lZhFvH9yJztHCTPHrxs85cp5h iK9XtkHRXsekKYm+k9ex0Il6WyM6ofaYYHxZl5C6wGfyPFsEHvqfxoyIT yrAeUvjjvsyaRGibu57Whk5dYyvEDbk+dbyiRPIIuQS9vdPtsUbf00c7z amgzbM3GTPLiF76XTMZt4WeIg1Ly3i9ddqIxAKvSAIgJwVO1EHtxM2mb+ YrQFM+Nahge937uBa4PdDR1G0RxYP9l2IAsn0h4yPLLLZRLjJBE4iGldl w==; X-IronPort-AV: E=Sophos;i="5.96,200,1665471600"; d="scan'208";a="190770227" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Nov 2022 03:34:14 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 28 Nov 2022 03:34:13 -0700 Received: from CHE-LT-I17769U.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 28 Nov 2022 03:34:08 -0700 From: Arun Ramadoss To: , CC: , , , , , , , , , , , , , Subject: [Patch net-next v1 09/12] net: dsa: microchip: ptp: move pdelay_rsp correction field to tail tag Date: Mon, 28 Nov 2022 16:02:24 +0530 Message-ID: <20221128103227.23171-10-arun.ramadoss@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221128103227.23171-1-arun.ramadoss@microchip.com> References: <20221128103227.23171-1-arun.ramadoss@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750735840249857020?= X-GMAIL-MSGID: =?utf-8?q?1750735840249857020?= From: Christian Eggers For PDelay_Resp messages we will likely have a negative value in the correction field. The switch hardware cannot correctly update such values (produces an off by one error in the UDP checksum), so it must be moved to the time stamp field in the tail tag. Format of the correction field is 48 bit ns + 16 bit fractional ns. After updating the correction field, clone is no longer required hence it is freed. Signed-off-by: Christian Eggers --- RFC v3 -> Patch v1 - Patch is separated from transmission logic patch --- drivers/net/dsa/microchip/ksz_ptp.c | 3 +++ include/linux/dsa/ksz_common.h | 2 ++ net/dsa/tag_ksz.c | 42 ++++++++++++++++++++++++++++- 3 files changed, 46 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/microchip/ksz_ptp.c b/drivers/net/dsa/microchip/ksz_ptp.c index 5eb5aca92556..f0b7fcca045b 100644 --- a/drivers/net/dsa/microchip/ksz_ptp.c +++ b/drivers/net/dsa/microchip/ksz_ptp.c @@ -182,6 +182,7 @@ void ksz_port_txtstamp(struct dsa_switch *ds, int port, switch (ptp_msg_type) { case PTP_MSGTYPE_PDELAY_REQ: + case PTP_MSGTYPE_PDELAY_RESP: break; default: @@ -194,6 +195,8 @@ void ksz_port_txtstamp(struct dsa_switch *ds, int port, /* caching the value to be used in later */ KSZ_SKB_CB(skb)->clone = clone; + KSZ_SKB_CB(clone)->ptp_type = type; + KSZ_SKB_CB(clone)->ptp_msg_type = ptp_msg_type; } static int _ksz_ptp_gettime(struct ksz_device *dev, struct timespec64 *ts) diff --git a/include/linux/dsa/ksz_common.h b/include/linux/dsa/ksz_common.h index 5f0e0c614e94..370ce9b56902 100644 --- a/include/linux/dsa/ksz_common.h +++ b/include/linux/dsa/ksz_common.h @@ -38,6 +38,8 @@ struct ksz_tagger_data { struct ksz_skb_cb { struct sk_buff *clone; + unsigned int ptp_type; + u8 ptp_msg_type; }; #define KSZ_SKB_CB(skb) \ diff --git a/net/dsa/tag_ksz.c b/net/dsa/tag_ksz.c index 6ed94dc0f18e..2a08e48f41f8 100644 --- a/net/dsa/tag_ksz.c +++ b/net/dsa/tag_ksz.c @@ -241,14 +241,54 @@ static void ksz_rcv_timestamp(struct sk_buff *skb, u8 *tag, /* Time stamp tag is only inserted if PTP is enabled in hardware. */ static void ksz_xmit_timestamp(struct dsa_port *dp, struct sk_buff *skb) { + struct sk_buff *clone = KSZ_SKB_CB(skb)->clone; struct ksz_tagger_private *priv; + struct ptp_header *ptp_hdr; + unsigned int ptp_type; + u32 tstamp_raw = 0; + u8 ptp_msg_type; + s64 correction; priv = ksz_tagger_private(dp->ds); if (!test_bit(KSZ_HWTS_EN, &priv->state)) return; - put_unaligned_be32(0, skb_put(skb, KSZ_PTP_TAG_LEN)); + if (!clone) + goto output_tag; + + ptp_type = KSZ_SKB_CB(clone)->ptp_type; + if (ptp_type == PTP_CLASS_NONE) + goto output_tag; + + ptp_hdr = ptp_parse_header(skb, ptp_type); + if (!ptp_hdr) + goto output_tag; + + ptp_msg_type = KSZ_SKB_CB(clone)->ptp_msg_type; + if (ptp_msg_type != PTP_MSGTYPE_PDELAY_RESP) + goto output_tag; + + correction = (s64)get_unaligned_be64(&ptp_hdr->correction); + + if (correction < 0) { + struct timespec64 ts; + + ts = ns_to_timespec64(-correction >> 16); + tstamp_raw = ((ts.tv_sec & 3) << 30) | ts.tv_nsec; + + /* Set correction field to 0 and update UDP checksum. */ + ptp_header_update_correction(skb, ptp_type, ptp_hdr, 0); + } + + /* For PDelay_Resp messages, the clone is not required in + * skb_complete_tx_timestamp() and should be freed here. + */ + kfree_skb(clone); + KSZ_SKB_CB(skb)->clone = NULL; + +output_tag: + put_unaligned_be32(tstamp_raw, skb_put(skb, KSZ_PTP_TAG_LEN)); } /* Defer transmit if waiting for egress time stamp is required. */ From patchwork Mon Nov 28 10:32:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun Ramadoss X-Patchwork-Id: 26621 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5566252wrr; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id sa24-20020a1709076d1800b0073866c0672asi10822668ejc.73.2022.11.28.02.37.50; Mon, 28 Nov 2022 02:38:13 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=c6w4oEd7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230372AbiK1Kff (ORCPT + 99 others); Mon, 28 Nov 2022 05:35:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230321AbiK1Keh (ORCPT ); Mon, 28 Nov 2022 05:34:37 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C80041AF2D; Mon, 28 Nov 2022 02:34:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1669631662; x=1701167662; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ididD8hOsLOrjFCIWEdnmkh5wnH/n+EBu8dA7Ljne/Q=; b=c6w4oEd7qOdnIERNMIIrdogjWpwE/1Q7rUzDXg/xVWGPkIvaUCQY0Fky oyKbk73Oy37fWAtO0SSnH4K89ULkRfd/wTZUAsIyMawZrc9HIhxcfaeNF mceur/5tG40Ep/jckppeL9WAD9+RzDOyyV3zlT1uktBEXT+ev1E4Pudm/ PgljE/uoS4VpYfOSI904jmqg8ctrRGXj4GvGnjJg9FXILbiQh42uNST2l loG+aV4+0XutIFhCVICIVkje3dMRRX3kV/4DRVau3ziJyr4BgMedKQQJ6 kDNg1ocuqSARcLIUBNfMQtgXDqVA75PQWqJljKk8q9hG/cn8sGmEuLh1v A==; X-IronPort-AV: E=Sophos;i="5.96,200,1665471600"; d="scan'208";a="201649643" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Nov 2022 03:34:22 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 28 Nov 2022 03:34:21 -0700 Received: from CHE-LT-I17769U.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 28 Nov 2022 03:34:16 -0700 From: Arun Ramadoss To: , CC: , , , , , , , , , , , , , Subject: [Patch net-next v1 10/12] net: dsa: microchip: ptp: add 2 step timestamping for LAN937x Date: Mon, 28 Nov 2022 16:02:25 +0530 Message-ID: <20221128103227.23171-11-arun.ramadoss@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221128103227.23171-1-arun.ramadoss@microchip.com> References: <20221128103227.23171-1-arun.ramadoss@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750735931995301048?= X-GMAIL-MSGID: =?utf-8?q?1750735931995301048?= LAN937x series of switches support 2 step timestamping mechanism. There are timestamp correction calculation performed in ksz_rcv_timestamp and ksz_xmit_timestamp which are applicable only for p2p1step. To check whether the 2 step is enabled or not in tag_ksz.c introduced the helper function in taggger_data to query it from ksz_ptp.c. Based on whether 2 step is enabled or not, timestamp calculation are performed. Signed-off-by: Arun Ramadoss --- Patch v1 - Patch is new. --- drivers/net/dsa/microchip/ksz_common.c | 1 + drivers/net/dsa/microchip/ksz_ptp.c | 23 +++++++++++++++++++++++ drivers/net/dsa/microchip/ksz_ptp.h | 6 ++++++ include/linux/dsa/ksz_common.h | 1 + net/dsa/tag_ksz.c | 14 ++++++++++++++ 5 files changed, 45 insertions(+) diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c index 3b578a4a33de..91f998fab231 100644 --- a/drivers/net/dsa/microchip/ksz_common.c +++ b/drivers/net/dsa/microchip/ksz_common.c @@ -2462,6 +2462,7 @@ static int ksz_connect_tag_protocol(struct dsa_switch *ds, tagger_data = ksz_tagger_data(ds); tagger_data->xmit_work_fn = ksz_port_deferred_xmit; tagger_data->meta_tstamp_handler = ksz_tstamp_reconstruct; + tagger_data->is_ptp_twostep = ksz_is_ptp_twostep; return 0; } diff --git a/drivers/net/dsa/microchip/ksz_ptp.c b/drivers/net/dsa/microchip/ksz_ptp.c index f0b7fcca045b..79ed31fd1398 100644 --- a/drivers/net/dsa/microchip/ksz_ptp.c +++ b/drivers/net/dsa/microchip/ksz_ptp.c @@ -62,6 +62,9 @@ int ksz_get_ts_info(struct dsa_switch *ds, int port, struct ethtool_ts_info *ts) ts->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ONESTEP_P2P); + if (is_lan937x(dev)) + ts->tx_types |= BIT(HWTSTAMP_TX_ON); + ts->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL); ts->phc_index = ptp_clock_index(ptp_data->clock); @@ -111,6 +114,15 @@ static int ksz_set_hwtstamp_config(struct ksz_device *dev, int port, prt->ptpmsg_irq[KSZ_PDRES_MSG].ts_en = 0; prt->hwts_tx_en = HWTSTAMP_TX_ONESTEP_P2P; break; + case HWTSTAMP_TX_ON: + if (!is_lan937x(dev)) + return -ERANGE; + + prt->ptpmsg_irq[KSZ_SYNC_MSG].ts_en = 1; + prt->ptpmsg_irq[KSZ_XDREQ_MSG].ts_en = 1; + prt->ptpmsg_irq[KSZ_PDRES_MSG].ts_en = 1; + prt->hwts_tx_en = HWTSTAMP_TX_ON; + break; default: return -ERANGE; } @@ -129,6 +141,14 @@ static int ksz_set_hwtstamp_config(struct ksz_device *dev, int port, return ksz_ptp_enable_mode(dev, rx_on); } +bool ksz_is_ptp_twostep(struct dsa_switch *ds, unsigned int port) +{ + struct ksz_device *dev = ds->priv; + struct ksz_port *prt = &dev->ports[port]; + + return (prt->hwts_tx_en == HWTSTAMP_TX_ON); +} + int ksz_hwtstamp_set(struct dsa_switch *ds, int port, struct ifreq *ifr) { struct ksz_device *dev = ds->priv; @@ -181,6 +201,9 @@ void ksz_port_txtstamp(struct dsa_switch *ds, int port, ptp_msg_type = ptp_get_msgtype(hdr, type); switch (ptp_msg_type) { + case PTP_MSGTYPE_SYNC: + if (prt->hwts_tx_en == HWTSTAMP_TX_ONESTEP_P2P) + return; case PTP_MSGTYPE_PDELAY_REQ: case PTP_MSGTYPE_PDELAY_RESP: break; diff --git a/drivers/net/dsa/microchip/ksz_ptp.h b/drivers/net/dsa/microchip/ksz_ptp.h index 8bcdd4c413a8..ff169d119169 100644 --- a/drivers/net/dsa/microchip/ksz_ptp.h +++ b/drivers/net/dsa/microchip/ksz_ptp.h @@ -33,6 +33,7 @@ int ksz_ptp_irq_setup(struct dsa_switch *ds, u8 p); void ksz_ptp_irq_free(struct dsa_switch *ds, u8 p); void ksz_port_deferred_xmit(struct kthread_work *work); ktime_t ksz_tstamp_reconstruct(struct dsa_switch *ds, ktime_t tstamp); +bool ksz_is_ptp_twostep(struct dsa_switch *ds, unsigned int port); #else @@ -79,6 +80,11 @@ static inline ktime_t ksz_tstamp_reconstruct(struct dsa_switch *ds, ktime_t tsta return 0; } +static inline bool ksz_is_ptp_twostep(struct dsa_switch *ds, unsigned int port) +{ + return 0; +} + #endif /* End of CONFIG_NET_DSA_MICROCHIP_KSZ_PTP */ #endif diff --git a/include/linux/dsa/ksz_common.h b/include/linux/dsa/ksz_common.h index 370ce9b56902..45f347c2b4d4 100644 --- a/include/linux/dsa/ksz_common.h +++ b/include/linux/dsa/ksz_common.h @@ -34,6 +34,7 @@ struct ksz_tagger_data { bool (*hwtstamp_get_state)(struct dsa_switch *ds); void (*hwtstamp_set_state)(struct dsa_switch *ds, bool on); ktime_t (*meta_tstamp_handler)(struct dsa_switch *ds, ktime_t tstamp); + bool (*is_ptp_twostep)(struct dsa_switch *ds, unsigned int port); }; struct ksz_skb_cb { diff --git a/net/dsa/tag_ksz.c b/net/dsa/tag_ksz.c index 2a08e48f41f8..561fab7d19c4 100644 --- a/net/dsa/tag_ksz.c +++ b/net/dsa/tag_ksz.c @@ -223,6 +223,12 @@ static void ksz_rcv_timestamp(struct sk_buff *skb, u8 *tag, if (!ptp_hdr) return; + if (!tagger_data->is_ptp_twostep) + return; + + if (tagger_data->is_ptp_twostep(ds, port)) + return; + ptp_msg_type = ptp_get_msgtype(ptp_hdr, ptp_type); if (ptp_msg_type != PTP_MSGTYPE_PDELAY_REQ) return; @@ -242,6 +248,7 @@ static void ksz_rcv_timestamp(struct sk_buff *skb, u8 *tag, static void ksz_xmit_timestamp(struct dsa_port *dp, struct sk_buff *skb) { struct sk_buff *clone = KSZ_SKB_CB(skb)->clone; + struct ksz_tagger_data *tagger_data; struct ksz_tagger_private *priv; struct ptp_header *ptp_hdr; unsigned int ptp_type; @@ -257,6 +264,13 @@ static void ksz_xmit_timestamp(struct dsa_port *dp, struct sk_buff *skb) if (!clone) goto output_tag; + tagger_data = ksz_tagger_data(dp->ds); + if (!tagger_data->is_ptp_twostep) + goto output_tag; + + if (tagger_data->is_ptp_twostep(dp->ds, dp->index)) + goto output_tag; + ptp_type = KSZ_SKB_CB(clone)->ptp_type; if (ptp_type == PTP_CLASS_NONE) goto output_tag; From patchwork Mon Nov 28 10:32:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun Ramadoss X-Patchwork-Id: 26622 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5566527wrr; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id z15-20020a17090655cf00b007aa493b067asi7325802ejp.396.2022.11.28.02.38.27; Mon, 28 Nov 2022 02:38:52 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=sCmpIyOY; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230467AbiK1Kfx (ORCPT + 99 others); Mon, 28 Nov 2022 05:35:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35086 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230390AbiK1KfQ (ORCPT ); Mon, 28 Nov 2022 05:35:16 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE87F18E18; Mon, 28 Nov 2022 02:34:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1669631675; x=1701167675; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nEYbHaSj7KYAS8mvwDzkP3IopXLcIRYJYEIXKy9P2hU=; b=sCmpIyOYE2vBF/bid8BClgYiY8tNiZeMIigNk809ntKEIztLFYDtetVa 1XhEYBRnjg+TqvblXKZx8giZDVjGCIL/izX2Fh2D5nxpRsKCf8zVI4Mnp rBlX5ZR4L4nikoKgc4kAkdcSWF67siyiEVXl5fPOcv1Mw6LzQLa/T4a1P X+T917Yxdtde5Dx0EASWf7+WNEjHX+4adBNhPH6k+uGqLcR7ZOksVgPes tzruZDjw+wplP1Qo9AhK921TQpnBz8qYDJ6//pB80BNJCeDiPKz/OsRox kPa1ZrBsyCw1FI+ciD2tM7EpeRcFl9EOKBG5yPvV5y0zAXjWyKhTqz0Pt A==; X-IronPort-AV: E=Sophos;i="5.96,200,1665471600"; d="scan'208";a="188931372" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Nov 2022 03:34:32 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 28 Nov 2022 03:34:30 -0700 Received: from CHE-LT-I17769U.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 28 Nov 2022 03:34:25 -0700 From: Arun Ramadoss To: , CC: , , , , , , , , , , , , , Subject: [Patch net-next v1 11/12] net: dsa: microchip: ptp: add periodic output signal Date: Mon, 28 Nov 2022 16:02:26 +0530 Message-ID: <20221128103227.23171-12-arun.ramadoss@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221128103227.23171-1-arun.ramadoss@microchip.com> References: <20221128103227.23171-1-arun.ramadoss@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750735973520792633?= X-GMAIL-MSGID: =?utf-8?q?1750735973520792633?= From: Christian Eggers LAN937x and KSZ PTP supported switches has Three Trigger output unit. This TOU can used to generate the periodic signal for PTP. TOU has the cycle width register of 32 bit in size and period width register of 24 bit, each value is of 8ns so the pulse width can be maximum 125ms. Tested using ./testptp -d /dev/ptp0 -p 1000000000 -w 100000000 for generating the 10ms pulse width Signed-off-by: Christian Eggers Co-developed-by: Arun Ramadoss Signed-off-by: Arun Ramadoss --- drivers/net/dsa/microchip/ksz_common.h | 13 + drivers/net/dsa/microchip/ksz_ptp.c | 317 ++++++++++++++++++++++++ drivers/net/dsa/microchip/ksz_ptp.h | 8 + drivers/net/dsa/microchip/ksz_ptp_reg.h | 71 ++++++ 4 files changed, 409 insertions(+) diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h index dbde70a8990a..a5f5ba489186 100644 --- a/drivers/net/dsa/microchip/ksz_common.h +++ b/drivers/net/dsa/microchip/ksz_common.h @@ -476,6 +476,19 @@ static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask, return ret; } +static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask, + u32 value) +{ + int ret; + + ret = regmap_update_bits(dev->regmap[2], reg, mask, value); + if (ret) + dev_err(dev->dev, "can't rmw 32bit reg: 0x%x %pe\n", reg, + ERR_PTR(ret)); + + return ret; +} + static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) { u32 val[2]; diff --git a/drivers/net/dsa/microchip/ksz_ptp.c b/drivers/net/dsa/microchip/ksz_ptp.c index 79ed31fd1398..15b863c85cb1 100644 --- a/drivers/net/dsa/microchip/ksz_ptp.c +++ b/drivers/net/dsa/microchip/ksz_ptp.c @@ -24,6 +24,269 @@ #define KSZ_PTP_INT_START 13 +static int _ksz_ptp_gettime(struct ksz_device *dev, struct timespec64 *ts); + +static int ksz_ptp_tou_gpio(struct ksz_device *dev) +{ + int ret; + + ret = ksz_rmw32(dev, REG_SW_GLOBAL_LED_OVR__4, LED_OVR_1, LED_OVR_1); + if (ret) + return ret; + + return ksz_rmw32(dev, REG_SW_GLOBAL_LED_SRC__4, + LED_SRC_PTP_GPIO_1, LED_SRC_PTP_GPIO_1); +} + +static int ksz_ptp_tou_reset(struct ksz_device *dev, u8 unit) +{ + u32 data; + int ret; + + /* Reset trigger unit (clears TRIGGER_EN, but not GPIOSTATx) */ + ret = ksz_rmw32(dev, REG_PTP_CTRL_STAT__4, TRIG_RESET, TRIG_RESET); + + data = FIELD_PREP(TRIG_DONE_M, BIT(unit)); + ret = ksz_write32(dev, REG_PTP_TRIG_STATUS__4, data); + if (ret) + return ret; + + data = FIELD_PREP(TRIG_INT_M, BIT(unit)); + ret = ksz_write32(dev, REG_PTP_INT_STATUS__4, data); + if (ret) + return ret; + + /* Clear reset and set GPIO direction */ + return ksz_rmw32(dev, REG_PTP_CTRL_STAT__4, (TRIG_RESET | TRIG_ENABLE), + 0); +} + +static int ksz_ptp_tou_pulse_verify(u64 pulse_ns) +{ + u32 data; + + if (pulse_ns & 0x3) + return -EINVAL; + + data = (pulse_ns / 8); + if (!FIELD_FIT(TRIG_PULSE_WIDTH_M, data)) + return -ERANGE; + + return 0; +} + +static int ksz_ptp_tou_target_time_set(struct ksz_device *dev, + struct timespec64 const *ts) +{ + int ret; + + /* Hardware has only 32 bit */ + if ((ts->tv_sec & 0xffffffff) != ts->tv_sec) + return -EINVAL; + + ret = ksz_write32(dev, REG_TRIG_TARGET_NANOSEC, ts->tv_nsec); + if (ret) + return ret; + + ret = ksz_write32(dev, REG_TRIG_TARGET_SEC, ts->tv_sec); + if (ret) + return ret; + + return 0; +} + +static int ksz_ptp_tou_start(struct ksz_device *dev, u8 unit) +{ + u32 data; + int ret; + + ret = ksz_rmw32(dev, REG_PTP_CTRL_STAT__4, TRIG_ENABLE | GPIO_OUT, + TRIG_ENABLE | GPIO_OUT); + if (ret) + return ret; + + /* Check error flag: + * - the ACTIVE flag is NOT cleared an error! + */ + ret = ksz_read32(dev, REG_PTP_TRIG_STATUS__4, &data); + if (ret) + return ret; + + if (FIELD_GET(TRIG_ERROR_M, data) & (1 << unit)) { + dev_err(dev->dev, "%s: Trigger unit%d error!\n", __func__, + unit); + ret = -EIO; + /* Unit will be reset on next access */ + return ret; + } + + return 0; +} + +static int ksz_ptp_configure_perout(struct ksz_device *dev, + u32 cycle_width_ns, u32 pulse_width_ns, + struct timespec64 const *target_time, + u8 index) +{ + u32 data; + int ret; + + data = FIELD_PREP(TRIG_NOTIFY, 1) | + FIELD_PREP(TRIG_GPO_M, index) | + FIELD_PREP(TRIG_PATTERN_M, TRIG_POS_PERIOD); + ret = ksz_write32(dev, REG_TRIG_CTRL__4, data); + if (ret) + return ret; + + ret = ksz_write32(dev, REG_TRIG_CYCLE_WIDTH, cycle_width_ns); + if (ret) + return ret; + + /* Set cycle count 0 - Infinite */ + ret = ksz_rmw32(dev, REG_TRIG_CYCLE_CNT, TRIG_CYCLE_CNT_M, 0); + if (ret) + return ret; + + data = (pulse_width_ns / 8); + ret = ksz_write32(dev, REG_TRIG_PULSE_WIDTH__4, data); + if (ret) + return ret; + + ret = ksz_ptp_tou_target_time_set(dev, target_time); + if (ret) + return ret; + + return 0; +} + +#define KSZ_PEROUT_VALID_FLAGS ( \ + PTP_PEROUT_DUTY_CYCLE \ + ) + +static int ksz_ptp_enable_perout(struct ksz_device *dev, + struct ptp_perout_request const *request, + int on) +{ + struct ksz_ptp_data *ptp_data = &dev->ptp_data; + u64 cycle_width_ns; + u64 pulse_width_ns; + int pin = 0; + u32 data32; + int ret; + + if (request->flags & ~KSZ_PEROUT_VALID_FLAGS) + return -EINVAL; + + if (ptp_data->tou_mode != KSZ_PTP_TOU_PEROUT && + ptp_data->tou_mode != KSZ_PTP_TOU_IDLE) + return -EBUSY; + + data32 = FIELD_PREP(PTP_GPIO_INDEX, pin) | + FIELD_PREP(PTP_TOU_INDEX, request->index); + ret = ksz_rmw32(dev, REG_PTP_UNIT_INDEX__4, + PTP_GPIO_INDEX | PTP_TOU_INDEX, data32); + if (ret) + return ret; + + ret = ksz_ptp_tou_reset(dev, request->index); + if (ret) + return ret; + + if (!on) { + ptp_data->tou_mode = KSZ_PTP_TOU_IDLE; + return 0; + } + + ptp_data->perout_target_time_first.tv_sec = request->start.sec; + ptp_data->perout_target_time_first.tv_nsec = request->start.nsec; + + ptp_data->perout_period.tv_sec = request->period.sec; + ptp_data->perout_period.tv_nsec = request->period.nsec; + + cycle_width_ns = timespec64_to_ns(&ptp_data->perout_period); + if ((cycle_width_ns & TRIG_CYCLE_WIDTH_M) != cycle_width_ns) + return -EINVAL; + + if (request->flags & PTP_PEROUT_DUTY_CYCLE) { + pulse_width_ns = request->on.sec * NSEC_PER_SEC + + request->on.nsec; + } else { + /* Use a duty cycle of 50%. Maximum pulse width supported by the + * hardware is a little bit more than 125 ms. + */ + pulse_width_ns = min_t(u64, + (request->period.sec * NSEC_PER_SEC + + request->period.nsec) / 2 + / 8 * 8, + 125000000LL); + } + + ret = ksz_ptp_tou_pulse_verify(pulse_width_ns); + if (ret) + return ret; + + ret = ksz_ptp_configure_perout(dev, cycle_width_ns, pulse_width_ns, + &ptp_data->perout_target_time_first, + pin); + if (ret) + return ret; + + ret = ksz_ptp_tou_gpio(dev); + if (ret) + return ret; + + ret = ksz_ptp_tou_start(dev, request->index); + if (ret) + return ret; + + ptp_data->tou_mode = KSZ_PTP_TOU_PEROUT; + + return 0; +} + +static int ksz_ptp_restart_perout(struct ksz_device *dev) +{ + struct ksz_ptp_data *ptp_data = &dev->ptp_data; + s64 now_ns, first_ns, period_ns, next_ns; + struct ptp_perout_request request; + struct timespec64 next; + struct timespec64 now; + unsigned int count; + int ret; + + ret = _ksz_ptp_gettime(dev, &now); + if (ret) + return ret; + + now_ns = timespec64_to_ns(&now); + first_ns = timespec64_to_ns(&ptp_data->perout_target_time_first); + + /* Calculate next perout event based on start time and period */ + period_ns = timespec64_to_ns(&ptp_data->perout_period); + + if (first_ns < now_ns) { + count = div_u64(now_ns - first_ns, period_ns); + next_ns = first_ns + count * period_ns; + } else { + next_ns = first_ns; + } + + /* Ensure 100 ms guard time prior next event */ + while (next_ns < now_ns + 100000000) + next_ns += period_ns; + + /* Restart periodic output signal */ + next = ns_to_timespec64(next_ns); + request.start.sec = next.tv_sec; + request.start.nsec = next.tv_nsec; + request.period.sec = ptp_data->perout_period.tv_sec; + request.period.nsec = ptp_data->perout_period.tv_nsec; + request.index = 0; + request.flags = 0; + + return ksz_ptp_enable_perout(dev, &request, 1); +} + static int ksz_ptp_enable_mode(struct ksz_device *dev, bool enable) { struct ksz_ptp_data *ptp_data = &dev->ptp_data; @@ -291,6 +554,20 @@ static int ksz_ptp_settime(struct ptp_clock_info *ptp, if (ret) goto error_return; + switch (ptp_data->tou_mode) { + case KSZ_PTP_TOU_IDLE: + break; + + case KSZ_PTP_TOU_PEROUT: + dev_info(dev->dev, "Restarting periodic output signal\n"); + + ret = ksz_ptp_restart_perout(dev); + if (ret) + goto error_return; + + break; + } + spin_lock_bh(&ptp_data->clock_lock); ptp_data->clock_time = *ts; spin_unlock_bh(&ptp_data->clock_lock); @@ -384,6 +661,20 @@ static int ksz_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) if (ret) goto error_return; + switch (ptp_data->tou_mode) { + case KSZ_PTP_TOU_IDLE: + break; + + case KSZ_PTP_TOU_PEROUT: + dev_info(dev->dev, "Restarting periodic output signal\n"); + + ret = ksz_ptp_restart_perout(dev); + if (ret) + goto error_return; + + break; + } + spin_lock_bh(&ptp_data->clock_lock); ptp_data->clock_time = timespec64_add(ptp_data->clock_time, delta64); spin_unlock_bh(&ptp_data->clock_lock); @@ -393,6 +684,30 @@ static int ksz_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) return ret; } +static int ksz_ptp_enable(struct ptp_clock_info *ptp, + struct ptp_clock_request *req, int on) +{ + struct ksz_ptp_data *ptp_data = ptp_caps_to_data(ptp); + struct ksz_device *dev = ptp_data_to_ksz_dev(ptp_data); + struct ptp_perout_request *request = &req->perout; + int ret; + + switch (req->type) { + case PTP_CLK_REQ_PEROUT: + if (request->index > ptp->n_per_out) + return -EINVAL; + + mutex_lock(&ptp_data->lock); + ret = ksz_ptp_enable_perout(dev, request, on); + mutex_unlock(&ptp_data->lock); + break; + default: + return -EINVAL; + } + + return ret; +} + /* Function is pointer to the do_aux_work in the ptp_clock capability */ static long ksz_ptp_do_aux_work(struct ptp_clock_info *ptp) { @@ -508,6 +823,8 @@ static const struct ptp_clock_info ksz_ptp_caps = { .adjfine = ksz_ptp_adjfine, .adjtime = ksz_ptp_adjtime, .do_aux_work = ksz_ptp_do_aux_work, + .enable = ksz_ptp_enable, + .n_per_out = 3, }; int ksz_ptp_clock_register(struct dsa_switch *ds) diff --git a/drivers/net/dsa/microchip/ksz_ptp.h b/drivers/net/dsa/microchip/ksz_ptp.h index ff169d119169..94ffd8bc0603 100644 --- a/drivers/net/dsa/microchip/ksz_ptp.h +++ b/drivers/net/dsa/microchip/ksz_ptp.h @@ -10,6 +10,11 @@ #include +enum ksz_ptp_tou_mode { + KSZ_PTP_TOU_IDLE, + KSZ_PTP_TOU_PEROUT, +}; + struct ksz_ptp_data { struct ptp_clock_info caps; struct ptp_clock *clock; @@ -18,6 +23,9 @@ struct ksz_ptp_data { /* lock for accessing the clock_time */ spinlock_t clock_lock; struct timespec64 clock_time; + enum ksz_ptp_tou_mode tou_mode; + struct timespec64 perout_target_time_first; /* start of first perout pulse */ + struct timespec64 perout_period; }; int ksz_ptp_clock_register(struct dsa_switch *ds); diff --git a/drivers/net/dsa/microchip/ksz_ptp_reg.h b/drivers/net/dsa/microchip/ksz_ptp_reg.h index 0c5a1193e1a1..f714deb55681 100644 --- a/drivers/net/dsa/microchip/ksz_ptp_reg.h +++ b/drivers/net/dsa/microchip/ksz_ptp_reg.h @@ -6,6 +6,14 @@ #ifndef __KSZ_PTP_REGS_H #define __KSZ_PTP_REGS_H +#define REG_SW_GLOBAL_LED_OVR__4 0x0120 +#define LED_OVR_2 BIT(1) +#define LED_OVR_1 BIT(0) + +#define REG_SW_GLOBAL_LED_SRC__4 0x0128 +#define LED_SRC_PTP_GPIO_1 BIT(3) +#define LED_SRC_PTP_GPIO_2 BIT(2) + /* 5 - PTP Clock */ #define REG_PTP_CLK_CTRL 0x0500 @@ -54,6 +62,69 @@ #define PTP_MASTER BIT(1) #define PTP_1STEP BIT(0) +#define REG_PTP_UNIT_INDEX__4 0x0520 + +#define PTP_GPIO_INDEX GENMASK(19, 16) +#define PTP_TSI_INDEX BIT(8) +#define PTP_TOU_INDEX GENMASK(1, 0) + +#define REG_PTP_TRIG_STATUS__4 0x0524 + +#define TRIG_ERROR_M GENMASK(18, 16) +#define TRIG_DONE_M GENMASK(2, 0) + +#define REG_PTP_INT_STATUS__4 0x0528 + +#define TRIG_INT_M GENMASK(18, 16) +#define TS_INT_M GENMASK(1, 0) + +#define REG_PTP_CTRL_STAT__4 0x052C + +#define GPIO_IN BIT(7) +#define GPIO_OUT BIT(6) +#define TS_INT_ENABLE BIT(5) +#define TRIG_ACTIVE BIT(4) +#define TRIG_ENABLE BIT(3) +#define TRIG_RESET BIT(2) +#define TS_ENABLE BIT(1) +#define TS_RESET BIT(0) + +#define REG_TRIG_TARGET_NANOSEC 0x0530 +#define REG_TRIG_TARGET_SEC 0x0534 + +#define REG_TRIG_CTRL__4 0x0538 + +#define TRIG_CASCADE_ENABLE BIT(31) +#define TRIG_CASCADE_TAIL BIT(30) +#define TRIG_CASCADE_UPS_M GENMASK(29, 26) +#define TRIG_NOW BIT(25) +#define TRIG_NOTIFY BIT(24) +#define TRIG_EDGE BIT(23) +#define TRIG_PATTERN_M GENMASK(22, 20) +#define TRIG_NEG_EDGE 0 +#define TRIG_POS_EDGE 1 +#define TRIG_NEG_PULSE 2 +#define TRIG_POS_PULSE 3 +#define TRIG_NEG_PERIOD 4 +#define TRIG_POS_PERIOD 5 +#define TRIG_REG_OUTPUT 6 +#define TRIG_GPO_M GENMASK(19, 16) +#define TRIG_CASCADE_ITERATE_CNT_M GENMASK(15, 0) + +#define REG_TRIG_CYCLE_WIDTH 0x053C +#define TRIG_CYCLE_WIDTH_M GENMASK(31, 0) + +#define REG_TRIG_CYCLE_CNT 0x0540 + +#define TRIG_CYCLE_CNT_M GENMASK(31, 16) +#define TRIG_BIT_PATTERN_M GENMASK(15, 0) + +#define REG_TRIG_ITERATE_TIME 0x0544 + +#define REG_TRIG_PULSE_WIDTH__4 0x0548 + +#define TRIG_PULSE_WIDTH_M GENMASK(23, 0) + /* Port PTP Register */ #define REG_PTP_PORT_RX_DELAY__2 0x0C00 #define REG_PTP_PORT_TX_DELAY__2 0x0C02 From patchwork Mon Nov 28 10:32:27 2022 Content-Type: text/plain; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id f14-20020a0564021e8e00b0046a91c850a0si10306499edf.78.2022.11.28.02.38.54; Mon, 28 Nov 2022 02:39:18 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=vx0BZgsb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230266AbiK1KgA (ORCPT + 99 others); Mon, 28 Nov 2022 05:36:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35536 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230352AbiK1Kff (ORCPT ); Mon, 28 Nov 2022 05:35:35 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F5C11ADA5; Mon, 28 Nov 2022 02:34:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1669631682; x=1701167682; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MDmZQEsgcRyI7TsiycO+2Jxh12HbRA1PQvHyL4JSUWE=; b=vx0BZgsbfEbUPfW+Yofw2VrPX+dwn8zHqAInmr7lHQPLOvCZ8VWWZgj3 RvVhvkhnAlJ8tnbgu4OC6AVHbJH6htDhI2GYr2pfxJoA29jmYzWuPTQ/B zBL6Hjzr19r9/24+1049hPs6DA5U2R901QMB3hM8SwDE1szBFuQtNOpB5 YLtPriFNXw2qCY/spsQatxey5QNZIut4rMN0aBq3S3YJ9AK/CD13TUqrS mPduBAOhyVLoE3VuQbjFaNQMN8zaLb9dYGeB8t7oMyvbBiZqk24WthrcC 9hXl131YjjnIRCZ9cZs+TuURHjZ2H5AlmtDF+F5bH0iTUaDFKoFfRuFwJ A==; X-IronPort-AV: E=Sophos;i="5.96,200,1665471600"; d="scan'208";a="185454052" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Nov 2022 03:34:41 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 28 Nov 2022 03:34:39 -0700 Received: from CHE-LT-I17769U.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 28 Nov 2022 03:34:33 -0700 From: Arun Ramadoss To: , CC: , , , , , , , , , , , , , Subject: [Patch net-next v1 12/12] net: dsa: microchip: ptp: add support for perout programmable pins Date: Mon, 28 Nov 2022 16:02:27 +0530 Message-ID: <20221128103227.23171-13-arun.ramadoss@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221128103227.23171-1-arun.ramadoss@microchip.com> References: <20221128103227.23171-1-arun.ramadoss@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750736000305398893?= X-GMAIL-MSGID: =?utf-8?q?1750736000305398893?= There are two programmable pins available for Trigger output unit to generate periodic pulses. This patch add verify_pin for the available 2 pins and configure it with respect to GPIO index for the TOU unit. Signed-off-by: Arun Ramadoss --- Patch v1 - patch is new --- drivers/net/dsa/microchip/ksz_ptp.c | 41 +++++++++++++++++++++++++++-- drivers/net/dsa/microchip/ksz_ptp.h | 3 +++ 2 files changed, 42 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/microchip/ksz_ptp.c b/drivers/net/dsa/microchip/ksz_ptp.c index 15b863c85cb1..445d220f1a1b 100644 --- a/drivers/net/dsa/microchip/ksz_ptp.c +++ b/drivers/net/dsa/microchip/ksz_ptp.c @@ -30,12 +30,14 @@ static int ksz_ptp_tou_gpio(struct ksz_device *dev) { int ret; - ret = ksz_rmw32(dev, REG_SW_GLOBAL_LED_OVR__4, LED_OVR_1, LED_OVR_1); + ret = ksz_rmw32(dev, REG_SW_GLOBAL_LED_OVR__4, LED_OVR_1 | LED_OVR_2, + LED_OVR_1 | LED_OVR_2); if (ret) return ret; return ksz_rmw32(dev, REG_SW_GLOBAL_LED_SRC__4, - LED_SRC_PTP_GPIO_1, LED_SRC_PTP_GPIO_1); + LED_SRC_PTP_GPIO_1 | LED_SRC_PTP_GPIO_2, + LED_SRC_PTP_GPIO_1 | LED_SRC_PTP_GPIO_2); } static int ksz_ptp_tou_reset(struct ksz_device *dev, u8 unit) @@ -181,6 +183,10 @@ static int ksz_ptp_enable_perout(struct ksz_device *dev, ptp_data->tou_mode != KSZ_PTP_TOU_IDLE) return -EBUSY; + pin = ptp_find_pin(ptp_data->clock, PTP_PF_PEROUT, request->index); + if (pin < 0) + return -EINVAL; + data32 = FIELD_PREP(PTP_GPIO_INDEX, pin) | FIELD_PREP(PTP_TOU_INDEX, request->index); ret = ksz_rmw32(dev, REG_PTP_UNIT_INDEX__4, @@ -708,6 +714,23 @@ static int ksz_ptp_enable(struct ptp_clock_info *ptp, return ret; } +static int ksz_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin, + enum ptp_pin_function func, unsigned int chan) +{ + int ret = 0; + + switch (func) { + case PTP_PF_NONE: + case PTP_PF_PEROUT: + break; + default: + ret = -1; + break; + } + + return ret; +} + /* Function is pointer to the do_aux_work in the ptp_clock capability */ static long ksz_ptp_do_aux_work(struct ptp_clock_info *ptp) { @@ -824,6 +847,8 @@ static const struct ptp_clock_info ksz_ptp_caps = { .adjtime = ksz_ptp_adjtime, .do_aux_work = ksz_ptp_do_aux_work, .enable = ksz_ptp_enable, + .verify = ksz_ptp_verify_pin, + .n_pins = KSZ_PTP_N_GPIO, .n_per_out = 3, }; @@ -832,6 +857,7 @@ int ksz_ptp_clock_register(struct dsa_switch *ds) struct ksz_device *dev = ds->priv; struct ksz_ptp_data *ptp_data; int ret; + u8 i; ptp_data = &dev->ptp_data; mutex_init(&ptp_data->lock); @@ -843,6 +869,17 @@ int ksz_ptp_clock_register(struct dsa_switch *ds) if (ret) return ret; + for (i = 0; i < KSZ_PTP_N_GPIO; i++) { + struct ptp_pin_desc *ptp_pin = &ptp_data->pin_config[i]; + + snprintf(ptp_pin->name, + sizeof(ptp_pin->name), "ksz_ptp_pin_%02d", i); + ptp_pin->index = i; + ptp_pin->func = PTP_PF_NONE; + } + + ptp_data->caps.pin_config = ptp_data->pin_config; + ptp_data->clock = ptp_clock_register(&ptp_data->caps, dev->dev); if (IS_ERR_OR_NULL(ptp_data->clock)) return PTR_ERR(ptp_data->clock); diff --git a/drivers/net/dsa/microchip/ksz_ptp.h b/drivers/net/dsa/microchip/ksz_ptp.h index 94ffd8bc0603..390364a177ea 100644 --- a/drivers/net/dsa/microchip/ksz_ptp.h +++ b/drivers/net/dsa/microchip/ksz_ptp.h @@ -10,6 +10,8 @@ #include +#define KSZ_PTP_N_GPIO 2 + enum ksz_ptp_tou_mode { KSZ_PTP_TOU_IDLE, KSZ_PTP_TOU_PEROUT, @@ -18,6 +20,7 @@ enum ksz_ptp_tou_mode { struct ksz_ptp_data { struct ptp_clock_info caps; struct ptp_clock *clock; + struct ptp_pin_desc pin_config[KSZ_PTP_N_GPIO]; /* Serializes all operations on the PTP hardware clock */ struct mutex lock; /* lock for accessing the clock_time */