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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id y2-20020a50eb02000000b00461cdda451dsi9089193edp.435.2022.11.27.22.40.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Nov 2022 22:40:08 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=PxTzdCJz; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9FEB0385B1B8 for ; Mon, 28 Nov 2022 06:40:07 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9FEB0385B1B8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1669617607; bh=bvtNUsFtEFTBFs/5gmeoFYvkpl5ywOr71uihtYi0LU0=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=PxTzdCJzGe5CzJeLEQzmvd2JBndF4CH0eALcD1lhRJklxrfNDqjalEBgBU4hdOD6r ZhuDz4GCLUcIibXuQqqGWqp3pIflmQoLS0fSbNsE8dMyC5qzOqi7j7fkYBFPU/YAeR FjaYWRCiTaW0Ug5dyNYDEGi3FeRsb6pOGNkd1w8s= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 389E63858C2C for ; Mon, 28 Nov 2022 06:39:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 389E63858C2C Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 46562300089; Mon, 28 Nov 2022 06:39:56 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH 1/3] RISC-V: Allocate "various" operand type Date: Mon, 28 Nov 2022 06:39:32 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750720954016131158?= X-GMAIL-MSGID: =?utf-8?q?1750720954016131158?= From: Tsukasa OI This commit intends to move operands that require very special handling or operand types that are so minor (e.g. only useful on a few instructions) under "W". I also intend this "W" to be "temporary" operand storage until we can find good two character (or less) operand type. In this commit, prefetch offset operand "f" for 'Zicbop' extension is moved to "Wif" because of its special handling (and allocating single character "f" for this operand type seemed too much). Current expected allocation guideline is as follows: 1. 'W' 2. The most closely related single-letter extension in lowercase (strongly recommended but not mandatory) 3. Identify operand type The author currently plans to allocate following three-character operand types (for operands including instructions from unratified extensions). 1. "Wif" ('Zicbop': fetch offset) 2. "Wfv" (unratified 'Zfa': value operand from FLI.[HSDQ] instructions) 3. "Wfm" / "WfM" 'Zfh', 'F', 'D', 'Q': rounding modes "m" with special handling solely for widening conversion instructions. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn, riscv_ip): Move from "f" to "Wif". opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Move from "f" to "Wif". * riscv-opc.c (riscv_opcodes): Reflect new operand type. --- gas/config/tc-riscv.c | 64 +++++++++++++++++++++++++++++++------------ opcodes/riscv-dis.c | 26 ++++++++++++++---- opcodes/riscv-opc.c | 6 ++-- 3 files changed, 71 insertions(+), 25 deletions(-) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 0682eb355241..bb0e18ac8d52 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1359,7 +1359,6 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break; case 'a': used_bits |= ENCODE_JTYPE_IMM (-1U); break; case 'p': used_bits |= ENCODE_BTYPE_IMM (-1U); break; - case 'f': /* Fall through. */ case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break; case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break; case 'z': break; /* Zero immediate. */ @@ -1386,6 +1385,21 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) goto unknown_validate_operand; } break; + case 'W': /* Various operands. */ + switch (*++oparg) + { + case 'i': + switch (*++oparg) + { + case 'f': used_bits |= ENCODE_STYPE_IMM (-1U); break; + default: + goto unknown_validate_operand; + } + break; + default: + goto unknown_validate_operand; + } + break; case 'X': /* Integer immediate. */ { size_t n; @@ -3401,22 +3415,37 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, imm_expr->X_op = O_absent; continue; - case 'f': /* Prefetch offset, pseudo S-type but lower 5-bits zero. */ - if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) - continue; - my_getExpression (imm_expr, asarg); - check_absolute_expr (ip, imm_expr, false); - if (((unsigned) (imm_expr->X_add_number) & 0x1fU) - || imm_expr->X_add_number >= (signed) RISCV_IMM_REACH / 2 - || imm_expr->X_add_number < -(signed) RISCV_IMM_REACH / 2) - as_bad (_("improper prefetch offset (%ld)"), - (long) imm_expr->X_add_number); - ip->insn_opcode |= - ENCODE_STYPE_IMM ((unsigned) (imm_expr->X_add_number) & - ~ 0x1fU); - imm_expr->X_op = O_absent; - asarg = expr_end; - continue; + case 'W': /* Various operands. */ + switch (*++oparg) + { + case 'i': + switch (*++oparg) + { + case 'f': + /* Prefetch offset for 'Zicbop' extension. + pseudo S-type but lower 5-bits zero. */ + if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) + continue; + my_getExpression (imm_expr, asarg); + check_absolute_expr (ip, imm_expr, false); + if (((unsigned) (imm_expr->X_add_number) & 0x1fU) + || imm_expr->X_add_number >= RISCV_IMM_REACH / 2 + || imm_expr->X_add_number < -RISCV_IMM_REACH / 2) + as_bad (_ ("improper prefetch offset (%ld)"), + (long) imm_expr->X_add_number); + ip->insn_opcode |= ENCODE_STYPE_IMM ( + (unsigned) (imm_expr->X_add_number) & ~0x1fU); + imm_expr->X_op = O_absent; + asarg = expr_end; + continue; + default: + goto unknown_riscv_ip_operand; + } + break; + default: + goto unknown_riscv_ip_operand; + } + break; case 'X': /* Integer immediate. */ { @@ -3469,6 +3498,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, } } break; + default: unknown_riscv_ip_operand: as_fatal (_("internal: unknown argument type `%s'"), diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 0e1f3b4610aa..1e6716e8e58c 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -473,11 +473,6 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info (int)EXTRACT_STYPE_IMM (l)); break; - case 'f': - print (info->stream, dis_style_address_offset, "%d", - (int)EXTRACT_STYPE_IMM (l)); - break; - case 'a': info->target = EXTRACT_JTYPE_IMM (l) + pc; (*info->print_address_func) (info->target, info); @@ -582,6 +577,27 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info print (info->stream, dis_style_immediate, "%d", rs1); break; + case 'W': /* Various operands. */ + { + switch (*++oparg) + { + case 'i': + switch (*++oparg) + { + case 'f': + print (info->stream, dis_style_address_offset, "%d", + (int) EXTRACT_STYPE_IMM (l)); + break; + default: + goto undefined_modifier; + } + break; + default: + goto undefined_modifier; + } + } + break; + case 'X': /* Integer immediate. */ { size_t n; diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 0e691544f9bc..653eb60f2a58 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -313,9 +313,9 @@ const struct riscv_opcode riscv_opcodes[] = /* name, xlen, isa, operands, match, mask, match_func, pinfo. */ /* Standard hints. */ -{"prefetch.i", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_I, MASK_PREFETCH_I, match_opcode, 0 }, -{"prefetch.r", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_R, MASK_PREFETCH_R, match_opcode, 0 }, -{"prefetch.w", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_W, MASK_PREFETCH_W, match_opcode, 0 }, +{"prefetch.i", 0, INSN_CLASS_ZICBOP, "Wif(s)", MATCH_PREFETCH_I, MASK_PREFETCH_I, match_opcode, 0 }, +{"prefetch.r", 0, INSN_CLASS_ZICBOP, "Wif(s)", MATCH_PREFETCH_R, MASK_PREFETCH_R, match_opcode, 0 }, +{"prefetch.w", 0, INSN_CLASS_ZICBOP, "Wif(s)", MATCH_PREFETCH_W, MASK_PREFETCH_W, match_opcode, 0 }, {"pause", 0, INSN_CLASS_ZIHINTPAUSE, "", MATCH_PAUSE, MASK_PAUSE, match_opcode, 0 }, /* Basic RVI instructions and aliases. */ From patchwork Mon Nov 28 06:39:33 2022 Content-Type: text/plain; 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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id dr17-20020a170907721100b007a087ccd275si9094366ejc.384.2022.11.27.22.40.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Nov 2022 22:40:23 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=R8pmbzbB; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E7C613854540 for ; Mon, 28 Nov 2022 06:40:17 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E7C613854540 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1669617617; bh=BoGDujGFP3/weGiZHowmW54z8N1ZupNrzkjAUCfLnSA=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=R8pmbzbBdxWPw8V2S7MMIoBhFd8mqDOMaTFgbKjydPEAB0vli0jOgAO/EKtXDU+mK YPVuK9WBcUMp4sKctqQoubJGG6PWLHlGvaeqFXdXG11om8pRmEAaxwMa817k15uLZE 1JagsGHOooD+c/zGphVMZIJ19HlyuVDdaAXY1Vkk= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 773C1385B504 for ; Mon, 28 Nov 2022 06:40:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 773C1385B504 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id CCFF9300089; Mon, 28 Nov 2022 06:40:06 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH 2/3] RISC-V: Reorganize invalid rounding mode test Date: Mon, 28 Nov 2022 06:39:33 +0000 Message-Id: <1a60e4b17f89e7aa94a6a41674f885398e5afd85.1669617534.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750720969560974095?= X-GMAIL-MSGID: =?utf-8?q?1750720969560974095?= From: Tsukasa OI This commit reorganizes and adds testcases to invalid rounding mode operand test. It also fixes a typo in the filename. gas/ChangeLog: * testsuite/gas/riscv/rounding-fail.d: Rename from rouding-fail. Add some testcases. * testsuite/gas/riscv/rounding-fail.s: Likewise. * testsuite/gas/riscv/rounding-fail.l: Likewise. --- gas/testsuite/gas/riscv/rouding-fail.d | 3 --- gas/testsuite/gas/riscv/rouding-fail.s | 3 --- gas/testsuite/gas/riscv/rounding-fail.d | 3 +++ gas/testsuite/gas/riscv/{rouding-fail.l => rounding-fail.l} | 2 ++ gas/testsuite/gas/riscv/rounding-fail.s | 6 ++++++ 5 files changed, 11 insertions(+), 6 deletions(-) delete mode 100644 gas/testsuite/gas/riscv/rouding-fail.d delete mode 100644 gas/testsuite/gas/riscv/rouding-fail.s create mode 100644 gas/testsuite/gas/riscv/rounding-fail.d rename gas/testsuite/gas/riscv/{rouding-fail.l => rounding-fail.l} (52%) create mode 100644 gas/testsuite/gas/riscv/rounding-fail.s diff --git a/gas/testsuite/gas/riscv/rouding-fail.d b/gas/testsuite/gas/riscv/rouding-fail.d deleted file mode 100644 index 9827b11446db..000000000000 --- a/gas/testsuite/gas/riscv/rouding-fail.d +++ /dev/null @@ -1,3 +0,0 @@ -#as: -march=rv32ifd -#source: rouding-fail.s -#error_output: rouding-fail.l diff --git a/gas/testsuite/gas/riscv/rouding-fail.s b/gas/testsuite/gas/riscv/rouding-fail.s deleted file mode 100644 index d18f53efb503..000000000000 --- a/gas/testsuite/gas/riscv/rouding-fail.s +++ /dev/null @@ -1,3 +0,0 @@ -target: - fadd.s fa1,fa1,fa1, - fadd.d fa1,fa1,fa1, diff --git a/gas/testsuite/gas/riscv/rounding-fail.d b/gas/testsuite/gas/riscv/rounding-fail.d new file mode 100644 index 000000000000..0d0a55818caf --- /dev/null +++ b/gas/testsuite/gas/riscv/rounding-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32ifd +#source: rounding-fail.s +#error_output: rounding-fail.l diff --git a/gas/testsuite/gas/riscv/rouding-fail.l b/gas/testsuite/gas/riscv/rounding-fail.l similarity index 52% rename from gas/testsuite/gas/riscv/rouding-fail.l rename to gas/testsuite/gas/riscv/rounding-fail.l index ea46e7c2d5aa..00d4d8e40fa6 100644 --- a/gas/testsuite/gas/riscv/rouding-fail.l +++ b/gas/testsuite/gas/riscv/rounding-fail.l @@ -1,3 +1,5 @@ .*: Assembler messages: .*: Error: illegal operands `fadd.s fa1,fa1,fa1,' .*: Error: illegal operands `fadd.d fa1,fa1,fa1,' +.*: Error: illegal operands `fadd.s fa1,fa1,fa1,unknown' +.*: Error: illegal operands `fadd.d fa1,fa1,fa1,unknown' diff --git a/gas/testsuite/gas/riscv/rounding-fail.s b/gas/testsuite/gas/riscv/rounding-fail.s new file mode 100644 index 000000000000..6e05cbd410c9 --- /dev/null +++ b/gas/testsuite/gas/riscv/rounding-fail.s @@ -0,0 +1,6 @@ +target: + # Invalid rounding modes + fadd.s fa1,fa1,fa1, + fadd.d fa1,fa1,fa1, + fadd.s fa1,fa1,fa1,unknown + fadd.d fa1,fa1,fa1,unknown From patchwork Mon Nov 28 06:39:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 26534 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5469789wrr; Sun, 27 Nov 2022 22:41:53 -0800 (PST) X-Google-Smtp-Source: AA0mqf6fUn4tnHju4+L3moRGhTfUqNCDyHHybr1zZ7i6efkyacPj7ZDBECyhTM4cQEy1kNFuhQJw X-Received: by 2002:a17:907:7782:b0:7b6:dd6d:b829 with SMTP id ky2-20020a170907778200b007b6dd6db829mr29255215ejc.602.1669617713568; Sun, 27 Nov 2022 22:41:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669617713; cv=none; d=google.com; s=arc-20160816; b=LfeF/z9kJB3jnK/DRP8CyYirHkW6rfPwfSgtH/unxOsDQfSjKJ7ZpWYpGNJ7SC45d+ bHPlg3WB+YQuo+kE8W+bIrcfidxiIDnZqKPV8kx/vrOX056LgFje6Aw1kDPiNa4p4xp1 qerPuGtg+A7Khhir19jx7S6wCaMUko67MgRgYcFC43ipsRrjCCujDth9IXHDhhnRaPAj yNnoLVKxc2xuZ2+EL8KC+bKlRJmxUHn8sWoYN9LXTsg08Ln/axDYxeAoMNfxJdvv3Vfo M0jmnYS8tG1WnaSc5xVh0+Rdo3vkGJpigh6lMP4nd1UnhpDQ6FmFqg5X6TVepK/PYPzU 1AyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=J8VfoDknzQPZIKJW9DIHrT2frZ4NK3wgS3IkTUMF0NI=; b=KgYFoe8uGwQmJ8iXNVUxbxBaITRuVjlt1YU9KsOjVXJD+ovtHfkGfo4cMClKRESQJi 1SSqG6ORi077O+pKMoPAHzZ3TPzOhGEsRI8pKBjSVpFtXvWmslI+W2iZ+A3rcY+5Qklj rZGH/soIWaniIlzb5wc8/BSKxWttfm99Ms2gz7QZWCcEiwE97FooIsiJQ0VIr8ZmiVEV yqmHHFPZb8aRaF2VTQgI2V6GwaGk+jr6ncJ5LyXflu1sB1Di5gs/zer8VkwwymMYTSEY xsfSFrVzG+gFZ3v+r578fwZzg5Jf+/umtoA9+XTT4vgVyHi8v9M2g6CGfwFCpKhNDPS7 v3dw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=OJ367bWF; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id wz5-20020a170906fe4500b00732fcbcfedesi9937924ejb.623.2022.11.27.22.41.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Nov 2022 22:41:53 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=OJ367bWF; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0CDD13853D78 for ; Mon, 28 Nov 2022 06:41:18 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0CDD13853D78 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1669617678; bh=J8VfoDknzQPZIKJW9DIHrT2frZ4NK3wgS3IkTUMF0NI=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=OJ367bWFFB6JfLjIlL27F4smsEbYKoaLWHLpQ/iUI9zvjS6ZuTBLiALOfFymjztLI GSp5FBcvXz7EfTFItK5VFp4IKUlQTBe5FNSV5XlBq3NEa4D9VxGPEBdycYZLTHgMaE NwgQ3AVrkDKGiGMCDkaxBp90TfKmzGYWKqKGAoG8= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 0D8343858298 for ; Mon, 28 Nov 2022 06:40:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0D8343858298 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 5BA1A300089; Mon, 28 Nov 2022 06:40:17 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org, S Pawan Kumar Subject: [PATCH 3/3] RISC-V: Rounding mode on widening instructions Date: Mon, 28 Nov 2022 06:39:34 +0000 Message-Id: <354029278ac02efee0bf1f1dbc3514647f057424.1669617534.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750721063540302495?= X-GMAIL-MSGID: =?utf-8?q?1750721063540302495?= From: Tsukasa OI This commit adds support for rounding modes on widening instructions to the assembler/disassembler. On the disassembler, non-default rounding mode is displayed when "no-aliases" option is given or the rounding mode itself is invalid. On the assembler, specifying such rounding modes is prohibited unless we have supported in the past. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add rounding mode support to widening instructions. (riscv_ip): Likewise. * testsuite/gas/riscv/rounding-dis-widening.d: New disasm test. * testsuite/gas/riscv/rounding-dis-widening.s: Likewise. * testsuite/gas/riscv/rounding-dis-widening-noalias.d: Likewise. * testsuite/gas/riscv/rounding-fail.d: Add testcases for widening instructions. * testsuite/gas/riscv/rounding-fail.l: Likewise. * testsuite/gas/riscv/rounding-fail.s: Likewise. * testsuite/gas/riscv/rounding-fcvt.q.l.d: New test. * testsuite/gas/riscv/rounding-fcvt.q.l.l: Likewise. * testsuite/gas/riscv/rounding-fcvt.q.l.s: Likewise. * testsuite/gas/riscv/rounding-fcvt.q.l-noalias.d: Likewise. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add rounding mode support to widening instructions. * riscv-opc.c (riscv_opcodes): Use new operand types. Idea-by: Tsukasa OI Idea-by: S Pawan Kumar --- gas/config/tc-riscv.c | 43 +++++++++++++++++++ .../gas/riscv/rounding-dis-widening-noalias.d | 13 ++++++ .../gas/riscv/rounding-dis-widening.d | 13 ++++++ .../gas/riscv/rounding-dis-widening.s | 8 ++++ gas/testsuite/gas/riscv/rounding-fail.d | 2 +- gas/testsuite/gas/riscv/rounding-fail.l | 11 +++++ gas/testsuite/gas/riscv/rounding-fail.s | 16 +++++++ .../gas/riscv/rounding-fcvt.q.l-noalias.d | 15 +++++++ gas/testsuite/gas/riscv/rounding-fcvt.q.l.d | 15 +++++++ gas/testsuite/gas/riscv/rounding-fcvt.q.l.l | 3 ++ gas/testsuite/gas/riscv/rounding-fcvt.q.l.s | 5 +++ opcodes/riscv-dis.c | 22 ++++++++++ opcodes/riscv-opc.c | 26 ++++++----- 13 files changed, 177 insertions(+), 15 deletions(-) create mode 100644 gas/testsuite/gas/riscv/rounding-dis-widening-noalias.d create mode 100644 gas/testsuite/gas/riscv/rounding-dis-widening.d create mode 100644 gas/testsuite/gas/riscv/rounding-dis-widening.s create mode 100644 gas/testsuite/gas/riscv/rounding-fcvt.q.l-noalias.d create mode 100644 gas/testsuite/gas/riscv/rounding-fcvt.q.l.d create mode 100644 gas/testsuite/gas/riscv/rounding-fcvt.q.l.l create mode 100644 gas/testsuite/gas/riscv/rounding-fcvt.q.l.s diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index bb0e18ac8d52..f0f531039415 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1396,6 +1396,15 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) goto unknown_validate_operand; } break; + case 'f': + switch (*++oparg) + { + case 'M': /* Fall through. */ + case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break; + default: + goto unknown_validate_operand; + } + break; default: goto unknown_validate_operand; } @@ -3442,6 +3451,40 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, goto unknown_riscv_ip_operand; } break; + case 'f': + switch (*++oparg) + { + case 'M': + case 'm': + /* Optional rounding mode (widening conversion) + 'M': operand either disallowed or not recommended + (considered to be non-useful to normal software). + 'm': operand allowed for compatibility reasons + (display a warning instead). */ + if (*asarg == '\0') + { + INSERT_OPERAND (RM, *ip, 0); + continue; + } + else if (*asarg == ',' && asarg++ + && arg_lookup (&asarg, riscv_rm, + ARRAY_SIZE (riscv_rm), ®no)) + { + INSERT_OPERAND (RM, *ip, regno); + if (*oparg == 'M') + as_bad (_ ("rounding mode cannot be specified " + "on widening conversion")); + else + as_warn ( + _ ("specifying a rounding mode is strongly " + "discourged on widening conversion")); + continue; + } + break; + default: + goto unknown_riscv_ip_operand; + } + break; default: goto unknown_riscv_ip_operand; } diff --git a/gas/testsuite/gas/riscv/rounding-dis-widening-noalias.d b/gas/testsuite/gas/riscv/rounding-dis-widening-noalias.d new file mode 100644 index 000000000000..3330b1db83db --- /dev/null +++ b/gas/testsuite/gas/riscv/rounding-dis-widening-noalias.d @@ -0,0 +1,13 @@ +#as: -march=rv32ifd +#source: rounding-dis-widening.s +#objdump: -d -M no-aliases + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+420100d3[ ]+fcvt\.d\.s[ ]+ft1,ft2 +[ ]+[0-9a-f]+:[ ]+420100d3[ ]+fcvt\.d\.s[ ]+ft1,ft2 +[ ]+[0-9a-f]+:[ ]+420170d3[ ]+fcvt\.d\.s[ ]+ft1,ft2,dyn diff --git a/gas/testsuite/gas/riscv/rounding-dis-widening.d b/gas/testsuite/gas/riscv/rounding-dis-widening.d new file mode 100644 index 000000000000..8fb31ab39efa --- /dev/null +++ b/gas/testsuite/gas/riscv/rounding-dis-widening.d @@ -0,0 +1,13 @@ +#as: -march=rv32ifd +#source: rounding-dis-widening.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+420100d3[ ]+fcvt\.d\.s[ ]+ft1,ft2 +[ ]+[0-9a-f]+:[ ]+420100d3[ ]+fcvt\.d\.s[ ]+ft1,ft2 +[ ]+[0-9a-f]+:[ ]+420170d3[ ]+fcvt\.d\.s[ ]+ft1,ft2 diff --git a/gas/testsuite/gas/riscv/rounding-dis-widening.s b/gas/testsuite/gas/riscv/rounding-dis-widening.s new file mode 100644 index 000000000000..17443b0a0343 --- /dev/null +++ b/gas/testsuite/gas/riscv/rounding-dis-widening.s @@ -0,0 +1,8 @@ +target: + fcvt.d.s ft1, ft2 + # Standard encoding: + # - 2nd operand is the rounding mode (RNE [0b000] is preferred). + # - 6th operand (additional function) is zero for FCVT.D.S. + .insn r OP_FP, 0x0, 0x21, ft1, ft2, f0 + # Non-standard encoding + .insn r OP_FP, 0x7, 0x21, ft1, ft2, f0 diff --git a/gas/testsuite/gas/riscv/rounding-fail.d b/gas/testsuite/gas/riscv/rounding-fail.d index 0d0a55818caf..7857ab75145c 100644 --- a/gas/testsuite/gas/riscv/rounding-fail.d +++ b/gas/testsuite/gas/riscv/rounding-fail.d @@ -1,3 +1,3 @@ -#as: -march=rv32ifd +#as: -march=rv32ifdq_zfh #source: rounding-fail.s #error_output: rounding-fail.l diff --git a/gas/testsuite/gas/riscv/rounding-fail.l b/gas/testsuite/gas/riscv/rounding-fail.l index 00d4d8e40fa6..69d359a0eba4 100644 --- a/gas/testsuite/gas/riscv/rounding-fail.l +++ b/gas/testsuite/gas/riscv/rounding-fail.l @@ -3,3 +3,14 @@ .*: Error: illegal operands `fadd.d fa1,fa1,fa1,' .*: Error: illegal operands `fadd.s fa1,fa1,fa1,unknown' .*: Error: illegal operands `fadd.d fa1,fa1,fa1,unknown' +.*: Error: rounding mode cannot be specified on widening conversion +.*: Error: rounding mode cannot be specified on widening conversion +.*: Error: rounding mode cannot be specified on widening conversion +.*: Error: rounding mode cannot be specified on widening conversion +.*: Error: rounding mode cannot be specified on widening conversion +.*: Error: rounding mode cannot be specified on widening conversion +.*: Error: rounding mode cannot be specified on widening conversion +.*: Error: rounding mode cannot be specified on widening conversion +.*: Error: rounding mode cannot be specified on widening conversion +.*: Error: rounding mode cannot be specified on widening conversion +.*: Error: illegal operands `fcvt\.q\.wu ft1,t0,unknown' diff --git a/gas/testsuite/gas/riscv/rounding-fail.s b/gas/testsuite/gas/riscv/rounding-fail.s index 6e05cbd410c9..75f9fe1965d1 100644 --- a/gas/testsuite/gas/riscv/rounding-fail.s +++ b/gas/testsuite/gas/riscv/rounding-fail.s @@ -4,3 +4,19 @@ target: fadd.d fa1,fa1,fa1, fadd.s fa1,fa1,fa1,unknown fadd.d fa1,fa1,fa1,unknown + + # Rounding mode cannot be specified on widening conversion + # unless we have supported in the past. + fcvt.s.h ft1,ft2,dyn + fcvt.d.h ft1,ft2,dyn + fcvt.q.h ft1,ft2,dyn + fcvt.d.s ft1,ft2,dyn + fcvt.q.s ft1,ft2,dyn + fcvt.q.d ft1,ft2,dyn + fcvt.d.w ft1,t0,dyn + fcvt.d.wu ft1,t0,dyn + fcvt.q.w ft1,t0,dyn + fcvt.q.wu ft1,t0,dyn + + # Different error message because of an invalid rounding mode + fcvt.q.wu ft1,t0,unknown diff --git a/gas/testsuite/gas/riscv/rounding-fcvt.q.l-noalias.d b/gas/testsuite/gas/riscv/rounding-fcvt.q.l-noalias.d new file mode 100644 index 000000000000..6f7a10f6c755 --- /dev/null +++ b/gas/testsuite/gas/riscv/rounding-fcvt.q.l-noalias.d @@ -0,0 +1,15 @@ +#as: -march=rv64ifdq +#source: rounding-fcvt.q.l.s +#warning_output: rounding-fcvt.q.l.l +#objdump: -d -M no-aliases + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+d62280d3[ ]+fcvt\.q\.l[ ]+ft1,t0 +[ ]+[0-9a-f]+:[ ]+d622f0d3[ ]+fcvt\.q\.l[ ]+ft1,t0,dyn +[ ]+[0-9a-f]+:[ ]+d63280d3[ ]+fcvt\.q\.lu[ ]+ft1,t0 +[ ]+[0-9a-f]+:[ ]+d632f0d3[ ]+fcvt\.q\.lu[ ]+ft1,t0,dyn diff --git a/gas/testsuite/gas/riscv/rounding-fcvt.q.l.d b/gas/testsuite/gas/riscv/rounding-fcvt.q.l.d new file mode 100644 index 000000000000..80b6320e873f --- /dev/null +++ b/gas/testsuite/gas/riscv/rounding-fcvt.q.l.d @@ -0,0 +1,15 @@ +#as: -march=rv64ifdq +#source: rounding-fcvt.q.l.s +#warning_output: rounding-fcvt.q.l.l +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+d62280d3[ ]+fcvt\.q\.l[ ]+ft1,t0 +[ ]+[0-9a-f]+:[ ]+d622f0d3[ ]+fcvt\.q\.l[ ]+ft1,t0 +[ ]+[0-9a-f]+:[ ]+d63280d3[ ]+fcvt\.q\.lu[ ]+ft1,t0 +[ ]+[0-9a-f]+:[ ]+d632f0d3[ ]+fcvt\.q\.lu[ ]+ft1,t0 diff --git a/gas/testsuite/gas/riscv/rounding-fcvt.q.l.l b/gas/testsuite/gas/riscv/rounding-fcvt.q.l.l new file mode 100644 index 000000000000..22df262891e8 --- /dev/null +++ b/gas/testsuite/gas/riscv/rounding-fcvt.q.l.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Warning: specifying a rounding mode is strongly discourged on widening conversion +.*: Warning: specifying a rounding mode is strongly discourged on widening conversion diff --git a/gas/testsuite/gas/riscv/rounding-fcvt.q.l.s b/gas/testsuite/gas/riscv/rounding-fcvt.q.l.s new file mode 100644 index 000000000000..ec60e53f7ad1 --- /dev/null +++ b/gas/testsuite/gas/riscv/rounding-fcvt.q.l.s @@ -0,0 +1,5 @@ +target: + fcvt.q.l ft1,t0 + fcvt.q.l ft1,t0,dyn + fcvt.q.lu ft1,t0 + fcvt.q.lu ft1,t0,dyn diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 1e6716e8e58c..e4d966a118df 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -592,6 +592,27 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info goto undefined_modifier; } break; + case 'f': + switch (*++oparg) + { + case 'M': /* Fall through. */ + case 'm': + /* Optional rounding mode (widening conversion) + which defaults to RNE (0b000). + Display non-default rounding mode if: + 1. rounding mode is invalid or + 2. 'no-aliases' option is specified. */ + if (EXTRACT_OPERAND (RM, l) == 0 + || (!no_aliases && riscv_rm[EXTRACT_OPERAND (RM, l)])) + break; + print (info->stream, dis_style_text, ","); + arg_print (info, EXTRACT_OPERAND (RM, l), riscv_rm, + ARRAY_SIZE (riscv_rm)); + break; + default: + goto undefined_modifier; + } + break; default: goto undefined_modifier; } @@ -640,6 +661,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info } } break; + default: undefined_modifier: /* xgettext:c-format */ diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 653eb60f2a58..dbfb4f3918b2 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -659,9 +659,9 @@ const struct riscv_opcode riscv_opcodes[] = {"fcvt.h.w", 0, INSN_CLASS_ZFH_INX, "D,s,m", MATCH_FCVT_H_W, MASK_FCVT_H_W, match_opcode, 0 }, {"fcvt.h.wu", 0, INSN_CLASS_ZFH_INX, "D,s", MATCH_FCVT_H_WU|MASK_RM, MASK_FCVT_H_WU|MASK_RM, match_opcode, 0 }, {"fcvt.h.wu", 0, INSN_CLASS_ZFH_INX, "D,s,m", MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 }, -{"fcvt.s.h", 0, INSN_CLASS_ZFHMIN_INX, "D,S", MATCH_FCVT_S_H, MASK_FCVT_S_H|MASK_RM, match_opcode, 0 }, -{"fcvt.d.h", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,S", MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, 0 }, -{"fcvt.q.h", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,S", MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 }, +{"fcvt.s.h", 0, INSN_CLASS_ZFHMIN_INX, "D,SWfM", MATCH_FCVT_S_H, MASK_FCVT_S_H, match_opcode, 0 }, +{"fcvt.d.h", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,SWfM", MATCH_FCVT_D_H, MASK_FCVT_D_H, match_opcode, 0 }, +{"fcvt.q.h", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,SWfM", MATCH_FCVT_Q_H, MASK_FCVT_Q_H, match_opcode, 0 }, {"fcvt.h.s", 0, INSN_CLASS_ZFHMIN_INX, "D,S", MATCH_FCVT_H_S|MASK_RM, MASK_FCVT_H_S|MASK_RM, match_opcode, 0 }, {"fcvt.h.s", 0, INSN_CLASS_ZFHMIN_INX, "D,S,m", MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 }, {"fcvt.h.d", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,S", MATCH_FCVT_H_D|MASK_RM, MASK_FCVT_H_D|MASK_RM, match_opcode, 0 }, @@ -800,9 +800,9 @@ const struct riscv_opcode riscv_opcodes[] = {"fcvt.w.d", 0, INSN_CLASS_D_INX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 }, {"fcvt.wu.d", 0, INSN_CLASS_D_INX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, 0 }, {"fcvt.wu.d", 0, INSN_CLASS_D_INX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 }, -{"fcvt.d.w", 0, INSN_CLASS_D_INX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 }, -{"fcvt.d.wu", 0, INSN_CLASS_D_INX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.d.s", 0, INSN_CLASS_D_INX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 }, +{"fcvt.d.w", 0, INSN_CLASS_D_INX, "D,sWfM", MATCH_FCVT_D_W, MASK_FCVT_D_W, match_opcode, 0 }, +{"fcvt.d.wu", 0, INSN_CLASS_D_INX, "D,sWfM", MATCH_FCVT_D_WU, MASK_FCVT_D_WU, match_opcode, 0 }, +{"fcvt.d.s", 0, INSN_CLASS_D_INX, "D,SWfM", MATCH_FCVT_D_S, MASK_FCVT_D_S, match_opcode, 0 }, {"fcvt.s.d", 0, INSN_CLASS_D_INX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, 0 }, {"fcvt.s.d", 0, INSN_CLASS_D_INX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 }, {"fclass.d", 0, INSN_CLASS_D_INX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 }, @@ -857,10 +857,10 @@ const struct riscv_opcode riscv_opcodes[] = {"fcvt.w.q", 0, INSN_CLASS_Q_INX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 }, {"fcvt.wu.q", 0, INSN_CLASS_Q_INX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 }, {"fcvt.wu.q", 0, INSN_CLASS_Q_INX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 }, -{"fcvt.q.w", 0, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 }, -{"fcvt.q.wu", 0, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.q.s", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 }, -{"fcvt.q.d", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 }, +{"fcvt.q.w", 0, INSN_CLASS_Q_INX, "D,sWfM", MATCH_FCVT_Q_W, MASK_FCVT_Q_W, match_opcode, 0 }, +{"fcvt.q.wu", 0, INSN_CLASS_Q_INX, "D,sWfM", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU, match_opcode, 0 }, +{"fcvt.q.s", 0, INSN_CLASS_Q_INX, "D,SWfM", MATCH_FCVT_Q_S, MASK_FCVT_Q_S, match_opcode, 0 }, +{"fcvt.q.d", 0, INSN_CLASS_Q_INX, "D,SWfM", MATCH_FCVT_Q_D, MASK_FCVT_Q_D, match_opcode, 0 }, {"fcvt.s.q", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 }, {"fcvt.s.q", 0, INSN_CLASS_Q_INX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 }, {"fcvt.d.q", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 }, @@ -875,10 +875,8 @@ const struct riscv_opcode riscv_opcodes[] = {"fcvt.l.q", 64, INSN_CLASS_Q_INX, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 }, {"fcvt.lu.q", 64, INSN_CLASS_Q_INX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 }, {"fcvt.lu.q", 64, INSN_CLASS_Q_INX, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 }, -{"fcvt.q.l", 64, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, -{"fcvt.q.l", 64, INSN_CLASS_Q_INX, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 }, -{"fcvt.q.lu", 64, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 }, -{"fcvt.q.lu", 64, INSN_CLASS_Q_INX, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 }, +{"fcvt.q.l", 64, INSN_CLASS_Q_INX, "D,sWfm", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 }, +{"fcvt.q.lu", 64, INSN_CLASS_Q_INX, "D,sWfm", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 }, /* Compressed instructions. */ {"c.unimp", 0, INSN_CLASS_C, "", 0, 0xffffU, match_opcode, 0 },