From patchwork Mon Nov 28 04:43:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 26493 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5432319wrr; Sun, 27 Nov 2022 20:44:29 -0800 (PST) X-Google-Smtp-Source: AA0mqf652RwZp4RaKi+V4qF3PeRr6HyZY89BuIl6rDi18C8PUQnfH2QZ8v8Uv7Xl/F9IsTkgmevt X-Received: by 2002:a17:906:1695:b0:7aa:493b:679 with SMTP id s21-20020a170906169500b007aa493b0679mr25788461ejd.320.1669610669837; Sun, 27 Nov 2022 20:44:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669610669; cv=none; d=google.com; s=arc-20160816; b=PhxQvQaF/glUTLmBvYpcNZDskUKgt1rwGG6OEeNghKVD6Dvo9x/W3Cb7xLnRC1N6Vy agLIZcZk7lYK/cE4rk6W2yBEyLq8vFgd1dlUOKhp2PTN4WE8F8rHisTvGViwUjDUKlf+ LsOVDShqDaUfSEfjcvTzjcrhzKgvc6u5hjUm/ZZCqKNUybgbwRd1wKR19gRu3HSrGoq9 RtRUulKctCNO0S7fdhL/WfJ+ev8hFIxwtvgJqsqji701inu72rIXqqWBSzNjOWg+U4DN NjfbHATQ0Wo6CDaU7dggpXKY7/k+ps1kLVcae+8iDFky6jpH2nNrj1PsdhALj2nfUKQB 3v5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=qJef31EYBv3kk2BeFCjhXOpP9jMnQ3/rB8hh0u3Iupc=; b=duYlvX6Gl5F5QSDTsN20NeU46FzFkh/2xQEjrXtpcZbUen5+bKQNYSTqxXBm/fkVSX wYfVnEdQnJur4XuDu9iufRQV30bsJFOYc7csYsoGMCkB1ZhkZCJtsMU5mqkJ28spXHKg LGSzR2LJZYTSVdBusTOHNPgwdn0k72+EtXsorflDaCa3mtBYRedYAs9Ob7AgjKX4Lhkf 1ipnpYUIM9Kiw5zQX3M3IMw9aYrQ2CaFcb9AYB7q5QOTKKWRNqqBtgUAOSVjjFQOA4gx hvI+fOf+2/M4KhJ7gKC2uXnUnzagT8Dm7ot781clW4wzobI+issgjT2Gtc3UNb3dYBac 970Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=UxrxB8pA; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id hg4-20020a1709072cc400b007ae0e8f697fsi9493014ejc.652.2022.11.27.20.44.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Nov 2022 20:44:29 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=UxrxB8pA; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B861F385842B for ; Mon, 28 Nov 2022 04:44:27 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B861F385842B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1669610667; bh=qJef31EYBv3kk2BeFCjhXOpP9jMnQ3/rB8hh0u3Iupc=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=UxrxB8pALRsYGnAUa72CTnfQjeAIVSwJ5mKxRRHTo2xQpQ5WDXZ09HDUCnDc3h5vl F65ReaXJzuTK+knP7yBZpfnj9xP2qSPsdm1AL61XV8pE+Nq3UGpoVe2+xjPtGnJG2K 7QsfvfX3yTT8enjzhye+aj2k9BJsA7gcReMFBsFM= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id D6213385802F for ; Mon, 28 Nov 2022 04:44:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D6213385802F Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 5FA66300089; Mon, 28 Nov 2022 04:44:15 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH v2 01/11] opcodes/riscv-dis.c: More tidying Date: Mon, 28 Nov 2022 04:43:36 +0000 Message-Id: <5965a4d1d20a33accd4a9872f87da9e0fd6c1747.1669610611.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749536766377404391?= X-GMAIL-MSGID: =?utf-8?q?1750713677771316030?= From: Tsukasa OI This is a general tidying commit. opcodes/ChangeLog: * riscv-dis.c (struct riscv_private_data) Add summary. Make length of hi_addr more meaningful. --- opcodes/riscv-dis.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 0e1f3b4610aa..768b44ee6003 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -52,11 +52,12 @@ static riscv_parse_subset_t riscv_rps_dis = false, /* check_unknown_prefixed_ext. */ }; +/* Private data structure for the RISC-V disassembler. */ struct riscv_private_data { bfd_vma gp; bfd_vma print_addr; - bfd_vma hi_addr[OP_MASK_RD + 1]; + bfd_vma hi_addr[NGPR]; bool to_print_addr; bool has_gp; }; From patchwork Mon Nov 28 04:43:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 26494 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5432394wrr; Sun, 27 Nov 2022 20:44:43 -0800 (PST) X-Google-Smtp-Source: AA0mqf6lYpQEjF/emiTG21Lc6eJh/FQU6tsikdYpmgHT8fPdYE91k6wwxI37AorOMLkZ74wN+MCp X-Received: by 2002:a17:907:d40e:b0:7bb:f10c:9282 with SMTP id vi14-20020a170907d40e00b007bbf10c9282mr14373470ejc.325.1669610683881; Sun, 27 Nov 2022 20:44:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669610683; cv=none; d=google.com; s=arc-20160816; b=IBsMHfUqWFIRThl6Y6lmSTo0vvLXXmpnGk0xiQgNLTjoZNUJMmtgeaHiOL2YDBr6VC VVOHOl5JeNgnRKZoDh0+hGU7MhzmO+6MQa2O9F+ZKWg8oTumeMDD6jF6sxQ6hZt13+lM cJnvLZ6omWvgbFdgfDy88bZpBObjVLM8BxTbj1SAYuCo5nIRXxQJHbdK5SBqB+uWHlyZ IEpefmMBDv0l0PDsufK2j2JR3eF5lYF8911EI7MBhed/5NEZPdYCJ3Emc6Jhoko3g1Yv lq/PtBgu4pE6BecCTqevtOHFOOxB785rPO6ycuwYNNqXtJ2JouXOYLmjeyUBhopowxzN sW8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=+PMiStZLbu0tI3NfhVKkbOIv25tSm15twhC6XZyPUrg=; b=KuJicWD3tCjVKDQ0pBmGdKTOjyCq3ed8nr+Y/YX0Blwcn4hnxTBrYfBCeuUTAETZZG BKZNNNzySIEGrOc1LEgSAuPO5eyYXe9IaoOhIvSp/KIVsMiSz6upAQ8LjQ+FtkdkcrZM auMrtQM/57Es236ra474ul6MmcfS0t9PkD+KrNFklYE2KgQypOYXGmfnLakY4YzPJy6X 44dNRXuOUuzutlPJseJuHVaHn7IkiyfaxmNWriBJzNxjp0TCtE3XQwpwIrXvZYYQZFzp NTqW5OynYP3qnzGv0dyNgk4hzX+9tPyWSZOW0PDSLYA/+GmyXOMGsjz+tHOfhZdCagJi J2rQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=BHFKXxKZ; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id cr16-20020a170906d55000b00791a41d1b39si9563498ejc.656.2022.11.27.20.44.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Nov 2022 20:44:43 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=BHFKXxKZ; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 314B83855158 for ; Mon, 28 Nov 2022 04:44:36 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 314B83855158 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1669610676; bh=+PMiStZLbu0tI3NfhVKkbOIv25tSm15twhC6XZyPUrg=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=BHFKXxKZNdi1Of+T/zQ139Cnll14+JM0S5hBj/HySToPaF8urG2t9aYARWEDzm32Q sz9Y0tH6zmIUofp0b9+pDPZNZSmS6DWiDFqVWcqjvo5mQ5y1xw7Z0fnHpRaWoAjtM0 bEb/afMgbmQfmsYAlkiqSFaViw9Q8L9gu+u7tib4= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id A0EE0385B505 for ; Mon, 28 Nov 2022 04:44:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A0EE0385B505 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id DDED2300089; Mon, 28 Nov 2022 04:44:25 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH v2 02/11] RISC-V: Add test for 'Zfinx' register switching Date: Mon, 28 Nov 2022 04:43:37 +0000 Message-Id: <761a39a87ef882c6d99d135988d251d18c2bf096.1669610611.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749536910956208674?= X-GMAIL-MSGID: =?utf-8?q?1750713692052261604?= From: Tsukasa OI Because the author is going to reorganize core RISC-V disassembler, we have to make sure that nothing is broken when disassembling with mapping symbols with ISA string. This commit adds a testcase for 'F' and 'Zfinx' instructions to make sure that "FPR" register names are correctly switched when necessary. gas/ChangeLog: * testsuite/gas/riscv/mapping.s: Add 'F' and 'Zfinx' testcase. * testsuite/gas/riscv/mapping-dis.d: Likewise. * testsuite/gas/riscv/mapping-symbols.d: Likewise. --- gas/testsuite/gas/riscv/mapping-dis.d | 7 +++++++ gas/testsuite/gas/riscv/mapping-symbols.d | 4 ++++ gas/testsuite/gas/riscv/mapping.s | 10 ++++++++++ 3 files changed, 21 insertions(+) diff --git a/gas/testsuite/gas/riscv/mapping-dis.d b/gas/testsuite/gas/riscv/mapping-dis.d index b1a26fbd151b..f0508499b726 100644 --- a/gas/testsuite/gas/riscv/mapping-dis.d +++ b/gas/testsuite/gas/riscv/mapping-dis.d @@ -91,3 +91,10 @@ Disassembly of section .text.relax.align: [ ]+[0-9a-f]+:[ ]+00000013[ ]+nop [ ]+[0-9a-f]+:[ ]+00200513[ ]+li[ ]+a0,2 [ ]+[0-9a-f]+:[ ]+00000013[ ]+nop + +Disassembly of section .text.dis.zfinx: + +0+000 <.text.dis.zfinx>: +[ ]+[0-9a-f]+:[ ]+00c5f553[ ]+fadd\.s[ ]+fa0,fa1,fa2 +[ ]+[0-9a-f]+:[ ]+00c5f553[ ]+fadd\.s[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+00c5f553[ ]+fadd\.s[ ]+fa0,fa1,fa2 diff --git a/gas/testsuite/gas/riscv/mapping-symbols.d b/gas/testsuite/gas/riscv/mapping-symbols.d index 40df34097369..b28e3306b1b4 100644 --- a/gas/testsuite/gas/riscv/mapping-symbols.d +++ b/gas/testsuite/gas/riscv/mapping-symbols.d @@ -42,6 +42,10 @@ SYMBOL TABLE: 0+00 l d .text.relax.align 0+00 .text.relax.align 0+00 l .text.relax.align 0+00 \$xrv32i2p1_c2p0 0+08 l .text.relax.align 0+00 \$xrv32i2p1 +0+00 l d .text.dis.zfinx 0+00 .text.dis.zfinx +0+00 l .text.dis.zfinx 0+00 \$xrv32i2p1_f2p2_zicsr2p0 +0+04 l .text.dis.zfinx 0+00 \$xrv32i2p1_zicsr2p0_zfinx1p0 +0+08 l .text.dis.zfinx 0+00 \$xrv32i2p1_f2p2_zicsr2p0 0+0a l .text.section.padding 0+00 \$x 0+03 l .text.odd.align.start.insn 0+00 \$d 0+04 l .text.odd.align.start.insn 0+00 \$x diff --git a/gas/testsuite/gas/riscv/mapping.s b/gas/testsuite/gas/riscv/mapping.s index 3014a69e7920..4fee2b420f0c 100644 --- a/gas/testsuite/gas/riscv/mapping.s +++ b/gas/testsuite/gas/riscv/mapping.s @@ -119,3 +119,13 @@ addi a0, zero, 1 # $x, won't added .align 3 # $x, won't added addi a0, zero, 2 # $xrv32i .option pop + +.section .text.dis.zfinx, "ax" +.option push +.option arch, rv32if +fadd.s fa0, fa1, fa2 # $xrv32if +.option arch, rv32i_zfinx +fadd.s a0, a1, a2 # $xrv32i_zfinx +.option arch, rv32if +fadd.s fa0, fa1, fa2 # $xrv32if +.option pop From patchwork Mon Nov 28 04:43:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 26495 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5432491wrr; Sun, 27 Nov 2022 20:45:04 -0800 (PST) X-Google-Smtp-Source: AA0mqf7eolVbpBmd4C8grPt0qHzv2bsvIovnUqLWHYZcfsdkMCyXlvlzrnZynmYS5d3wK4uuNPb7 X-Received: by 2002:a05:6402:3810:b0:467:42a9:3568 with SMTP id es16-20020a056402381000b0046742a93568mr44790073edb.70.1669610704646; Sun, 27 Nov 2022 20:45:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669610704; cv=none; d=google.com; s=arc-20160816; b=oLKlaoGk2pwJlcfsjgApxA/EjtntJA0O84zvQPydE9z2RdyRkryQxbR29M8XfP4EYl WD8ls+vUHQsTqr9CKtFiDYTDVRR4UuQyGVF2NdUFtN9bo2uODtyZSFQrlnNuq58O9n1M VfEA3pvSXc6ks+Mby78fBJYsyXcac+BpOMm5iqUY0z8m3ZY7ANVgYEDJVlX4Dhnh5bnL QPBWbzR7o/7ow6Qf6M7GTQ54UEFm/gKRypg+9Kqt5tLn3NMhIhmeqDDIYNxcbA5Xcll2 Fv6IQV7fSePeS3y/tG83wUP0pHI78mRy41tF+Qo/9JfErpSIrJ5tN+4Y6VP04aj71sDG b5dw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=d8lDrteGVAiw88iusvV4T7cQPmz8kTOtl3cj1KFivLk=; b=AhgCvPyD19ybrCmIrFeGMk+jRKhw8tDpTY3A0PrjIHsRdLfin9VV+wKB+LKul/vzRn Zor7wY2O3OtR34yzRnTKLAHEXSaYahxCk33wnrCDo/mETvXy2X86/etYqXATu1r9HMp4 dhfuu+bv4Ds6lFeE6yEyw5SiO72VfpWAJPxNl84XSAussQXH4DpuXHB5NgMT5MNmz8x5 wzd0VAE2AicsNsf/NBjfKTDywAM7COffOSvb8QeJp80Cb+LhXB9WC4y7hZ1r8bGSjDfX H3NaOj0eIRmH5Rrd05nrPFRPA31Z5VSlrF/afQuXmrH8/3mHXoKZskCqk77l6FPCPizk mjbQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=DSnvLYVs; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id ht14-20020a170907608e00b007ad7e81a30csi8912017ejc.167.2022.11.27.20.45.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Nov 2022 20:45:04 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=DSnvLYVs; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8AEC1385514B for ; Mon, 28 Nov 2022 04:44:45 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8AEC1385514B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1669610685; bh=d8lDrteGVAiw88iusvV4T7cQPmz8kTOtl3cj1KFivLk=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=DSnvLYVss0TusEhzdIH/uiaKadPor9ij6LhrCdd3hwXqL6yJb+n2e7m5FFuZ8Xca8 IIq3iXratN8wSE9rXX7XUcevCuUPcl6ELC3JhjVihKASWWOOVsv4fHE9ykBIvY2X6t qv4orm3svCXRA3V45eBz1b7XvZHoWYM8R9pPVISk= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 2058A3854546 for ; Mon, 28 Nov 2022 04:44:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 2058A3854546 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 6DCC0300089; Mon, 28 Nov 2022 04:44:36 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH v2 03/11] RISC-V: Make mapping symbol checking consistent Date: Mon, 28 Nov 2022 04:43:38 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749536802991755025?= X-GMAIL-MSGID: =?utf-8?q?1750713714087179418?= From: Tsukasa OI There were two places where the mapping symbols are checked but had different conditions. - riscv_get_map_state: "$d" or starts with "$x" - riscv_elf_is_mapping_symbols: Starts with either "$x" or "$d" Considering recent mapping symbol proposal, it's better to make symbol checking consistent (whether the symbol _starts_ with "$[xd]"). It only checks prefix "$xrv" (mapping symbol with ISA string) only when the prefix "$x" is matched. opcodes/ChangeLog: * riscv-dis.c (riscv_get_map_state): Change the condition for consistency. --- opcodes/riscv-dis.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 768b44ee6003..f6fdd5badfe6 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -834,16 +834,17 @@ riscv_get_map_state (int n, return false; name = bfd_asymbol_name(info->symtab[n]); - if (strcmp (name, "$x") == 0) - *state = MAP_INSN; - else if (strcmp (name, "$d") == 0) - *state = MAP_DATA; - else if (strncmp (name, "$xrv", 4) == 0) + if (startswith (name, "$x")) { + if (startswith (name + 2, "rv")) + { + riscv_release_subset_list (&riscv_subsets); + riscv_parse_subset (&riscv_rps_dis, name + 2); + } *state = MAP_INSN; - riscv_release_subset_list (&riscv_subsets); - riscv_parse_subset (&riscv_rps_dis, name + 2); } + else if (startswith (name, "$d")) + *state = MAP_DATA; else return false; From patchwork Mon Nov 28 04:43:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 26497 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5433036wrr; Sun, 27 Nov 2022 20:46:59 -0800 (PST) X-Google-Smtp-Source: AA0mqf4+6LgDII1BKmRj9KxUVQ62zoLYbyyn4JAFMtjKJJLgvM5cD38vm/UBL0rBhu99u65sCbDU X-Received: by 2002:a17:907:a709:b0:79f:cd7c:e861 with SMTP id vw9-20020a170907a70900b0079fcd7ce861mr40670512ejc.339.1669610819866; Sun, 27 Nov 2022 20:46:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669610819; cv=none; d=google.com; s=arc-20160816; b=qqUQeF3ute6jSID/2gG4tYjynmOz5+wP0SxWgUcsNqoqBpUoqYzTqzi5f/z1ywvGT/ LInsV8kcmZBPN9BSU2AqGRuh6mkGinRDUVYknYB4KV8sYR8WlHE6sXiJLrRQBaenpBaa SylNVxBANlRXAVc2fwT79DpAIF8/sBH1mD0siNKy3zoysjJXjMM/PKG8L24FYDkmxNY9 m+tNvQcj0fKDK4/EVSYk2P4qhPOemasdGSZ3D5w+KeNBqk+0OjLxYhlBk1hBBAF26xdE xB+yIGaMyWmKTI27f9fz1/rjfFeJlaOlwXSK31KdUEMfv3tW13u7WzKC8HajVnqeEuBs ir9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=aYMPmris9xEH07eV+RcaAF8Nyhc+DvwAZYRNQFL1Hpo=; b=1BQzIGJNDRZp3bAbhrWXb4yqejMvk/AApqNbfZ1Gxst+c/rvO1V91oV5nbB2l2Th02 T2F6lAIb5J9y6Nom6VSP/CrUyAzAHfAGbftLqFfp+3JvzJmz4qtTRaATbXDyfdoc8HzC hK+1J62dvCNjGYM+VL1mNsJwE3KpZa/81ywmgwqcOnf6KF2NxuKB6ng14aR5UvpGwJ90 Ng02X0G8Tfewjr+OkciwadeMOqYoQjHIr5BhPbJL2+svT50EDM9QyF0XDHY+MGq2xkAP OHUv0+EU+iOLkY1wTmD/dGPQll1/tZ7qgxUJn3DqMr6rxnM/+qBW23yzuEIb8+f8XOg9 kVww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=x78yyj6E; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id xe14-20020a170907318e00b007ae85c3b7b3si9568153ejb.362.2022.11.27.20.46.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Nov 2022 20:46:59 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=x78yyj6E; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 67661384EF40 for ; Mon, 28 Nov 2022 04:45:37 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 67661384EF40 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1669610737; bh=aYMPmris9xEH07eV+RcaAF8Nyhc+DvwAZYRNQFL1Hpo=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=x78yyj6EGWyfRY8QBG/9NLF5F0upkdnHAmEwPuaZj6BwtwO4s36qqVYyvoeSVUWx9 rvMa7SJwBXELCNfIko+xLXLCuLHHaTdbxKbZYr/tm3dDhrdd3Inu1Gedm97nxl5y2P icCxBt2QsXxguCjM2TgWkFNmWt4N0JiN9OFo0Urg= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 9BC29385B53D for ; Mon, 28 Nov 2022 04:44:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 9BC29385B53D Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id EF94D300089; Mon, 28 Nov 2022 04:44:46 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH v2 04/11] RISC-V: Split riscv_get_map_state into two steps Date: Mon, 28 Nov 2022 04:43:39 +0000 Message-Id: <395973f56b805a000b0e2929c6b2ba6cd8fd140b.1669610611.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749536825560433114?= X-GMAIL-MSGID: =?utf-8?q?1750713834970964958?= From: Tsukasa OI Because mapping symbol optimization would remove riscv_get_map_state function, this commit splits symbol name checking step into a separate function riscv_get_map_state_by_name. Let alone the optimization, splitting the code improves readability. opcodes/ChangeLog: * riscv-dis.c (riscv_get_map_state): Split symbol name checking into a separate function. (riscv_get_map_state_by_name): New. --- opcodes/riscv-dis.c | 41 +++++++++++++++++++++++++++-------------- 1 file changed, 27 insertions(+), 14 deletions(-) diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index f6fdd5badfe6..38eb91349d9a 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -818,6 +818,24 @@ riscv_disassemble_insn (bfd_vma memaddr, return insnlen; } +/* Return new mapping state if a given symbol name is of mapping symbols', + MAP_NONE otherwise. If arch is not NULL and name denotes a mapping symbol + with ISA string, *arch is updated to the ISA string. */ + +static enum riscv_seg_mstate +riscv_get_map_state_by_name (const char *name, const char** arch) +{ + if (startswith (name, "$x")) + { + if (arch && startswith (name + 2, "rv")) + *arch = name + 2; + return MAP_INSN; + } + else if (startswith (name, "$d")) + return MAP_DATA; + return MAP_NONE; +} + /* Return true if we find the suitable mapping symbol, and also update the STATE. Otherwise, return false. */ @@ -826,28 +844,23 @@ riscv_get_map_state (int n, enum riscv_seg_mstate *state, struct disassemble_info *info) { - const char *name; + const char *name, *arch = NULL; /* If the symbol is in a different section, ignore it. */ if (info->section != NULL && info->section != info->symtab[n]->section) return false; - name = bfd_asymbol_name(info->symtab[n]); - if (startswith (name, "$x")) + name = bfd_asymbol_name (info->symtab[n]); + enum riscv_seg_mstate newstate = riscv_get_map_state_by_name (name, &arch); + if (newstate == MAP_NONE) + return false; + *state = newstate; + if (arch) { - if (startswith (name + 2, "rv")) - { - riscv_release_subset_list (&riscv_subsets); - riscv_parse_subset (&riscv_rps_dis, name + 2); - } - *state = MAP_INSN; + riscv_release_subset_list (&riscv_subsets); + riscv_parse_subset (&riscv_rps_dis, arch); } - else if (startswith (name, "$d")) - *state = MAP_DATA; - else - return false; - return true; } From patchwork Mon Nov 28 04:43:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 26496 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5432973wrr; Sun, 27 Nov 2022 20:46:46 -0800 (PST) X-Google-Smtp-Source: AA0mqf7JYIz1+gNCV64pjUKGep/qcWGRRWtJ3C1+mKrKMNbaUPGAoNX53xqRJ5HVfab0cClO7Un1 X-Received: by 2002:a05:6402:360b:b0:468:f365:dca with SMTP id el11-20020a056402360b00b00468f3650dcamr9307366edb.41.1669610806819; Sun, 27 Nov 2022 20:46:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669610806; cv=none; d=google.com; s=arc-20160816; b=My/efEzYdKXuY8lPM+kJPWyE/JbT4qnhLaq7Q69V17a+4hLH/qMR1F8dqViTwslIfd w/6o2TDjVbZqWq4W93fCyJAr+v1xxH6lAR1QfGdDPxWmwPJARKqa2x6ArxUSJgv9UZiq VopAlHvuL6+pntlTketKL/Xe2+Ife3gYNCf/83VLsRWclzmTyNR+QjncSxCzRqCqIvYj P5nE9Hune/4BewnGiC8/Apl0qy72SbIq+cMu0chgZOrkyjSoP5b2kU+FwHLHuAKpHmLh qR0JFwKt5Y/1WjMiwF2/nAfqSUHi8VU3ob700NWP95WJeyqd85LPA8pds0vE7IX63h14 mPNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=zxufoScZ45JUF/v53XFfZpJIolVsqNg1wUdR4KqVktQ=; b=SZSQgpX8Hwg/Eu4xOuME/kjblIN4KN5mypp3rYLMWxsZhRcN1M11uENw4nvs2eby69 lx5Lxtyz45iw+eG19kOz378k2Z1FbaI1lLsTkWCkTMB3+EGNDkibfgyoQRzfKKDWSMbJ EA4N0i0rEhqFOckpfRhUyvOHTZveys2al4NLnpKTV0yDa91srJZrC5xwqGfHbidTk9EH JM0hctQ2WeiC/ww8ulzgiQUlXj52dT1Yt5KZm9uF9ZcjuyUrNEqf0DxPz/dfH+ySBhAY kZ4+kB5Flclco4Uvq3ocqVfZ+1Osfu6c6biD8MvE9eyqxVGHP+Kcm60ZGPORhPYRRda1 R7RQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=xil6NfGg; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id nb24-20020a1709071c9800b007bfacfbd8b6si1628544ejc.155.2022.11.27.20.46.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Nov 2022 20:46:46 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=xil6NfGg; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C6B2B38362F2 for ; Mon, 28 Nov 2022 04:45:30 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C6B2B38362F2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1669610730; bh=zxufoScZ45JUF/v53XFfZpJIolVsqNg1wUdR4KqVktQ=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=xil6NfGgrEP9yg6NouTfLfjHjb1tzC8RgxQGOcklYj8oUe4qoEysHyHLd28T+bp9J HesRFqsV5YUPdfieyEeEL3ZMglVMTgTYYsAbXAO2lyP3//K9+pZc0bGJuNenEjY7uc Wm5wsg9ATTCO2SkebO6AZYniW4Wcb5NizeA5X6N0= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 2F1563854572 for ; Mon, 28 Nov 2022 04:44:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 2F1563854572 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 7C2DC300089; Mon, 28 Nov 2022 04:44:57 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH v2 05/11] RISC-V: One time CSR hash table initialization Date: Mon, 28 Nov 2022 04:43:40 +0000 Message-Id: <72c8e56861fccff6720a9b6ccefcecfd80e1adba.1669610611.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749537067859008886?= X-GMAIL-MSGID: =?utf-8?q?1750713821334506215?= From: Tsukasa OI The current disassembler intends to initialize the CSR hash table when CSR name parsing is required at the first time. This is managed by a function- scope static variable init_csr but... there's a problem. It's never set to true. Because of this issue, current disassembler actually initializes the CSR hash table every time when CSR name parsing is required. This commit sets init_csr to true once the CSR hash table is initialized. It is expected to have about 30% performance improvements alone when thousands of only CSR instructions are disassembled (CSR instructions are rare in general so real world performance improvement is not that high). This commit alone will not affect real world performance that much but after the efficient opcode hash is implemented, it will be much effective (sometimes >x10 effect than this commit alone) so that even some regular programs can benefit from it. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Make sure that CSR hash table initialization occurs only once. --- opcodes/riscv-dis.c | 1 + 1 file changed, 1 insertion(+) diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 38eb91349d9a..51a08d847b10 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -564,6 +564,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info DECLARE_CSR (name, num, class, define_version, abort_version) #include "opcode/riscv-opc.h" #undef DECLARE_CSR + init_csr = true; } if (riscv_csr_hash[csr] != NULL) From patchwork Mon Nov 28 04:43:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 26499 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5433492wrr; Sun, 27 Nov 2022 20:48:48 -0800 (PST) X-Google-Smtp-Source: AA0mqf49g6120rbKwSI0NiaNNr0pk3dJuga3/cAWhp/ea4+bt8WSl0cFZxgyolAfwils1Us0rgiQ X-Received: by 2002:a17:906:b809:b0:7be:71f5:3183 with SMTP id dv9-20020a170906b80900b007be71f53183mr6075678ejb.547.1669610928289; Sun, 27 Nov 2022 20:48:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669610928; cv=none; d=google.com; s=arc-20160816; b=hle1HQrFF0os/AWl9LlP3tlus1awe8cjkhL3iz8SkjOTsC/RhF+XKQOOVMgjaOfSiy SIvtEenaWAsbmN2WOuKNHfZDycaqua2c5Xb8iXusIvtnrQa5W920dPHY1c4owbMA53hi nVSG1s+ryKJ538bmGvT6+v9zSG9zuhl+DmUuDbbxE6Bi5Y/bJaI0d5A+EMUXlVPCBOBV ZwkCe/ExnM8mQh7QIpaAJrQNdrpgN7Nw/8hwLbcQK82pb0Coj8oNa+7cY5idepOA89vO 3Y7etEUeKL5ZJDnfLF2gnggBDs6HmpLlncxN9CcO25gWayrG6TIaWlrHcadQD+LOCsKi /KBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=KIqW8yPMFeAwnYpHVCBfAMQwGd4JwRwD5QyvnWMU1e4=; b=Dt18YCG9kxFGpDXema/jlafuwbQ2woihDi5cRzCGBZP1OUa4qIazLQaBIBBCke8442 evfZtEWz9SiP0nDFJJOFXbixRocgigxIejsxBuRXshD5npem36oJdE/+Nz5Fz/OEiJME Dk/pK6veUitbgpx8wag2Ppl6/UcFtKZevjv+5rRwjmIqHhCjT0FdUt6jCxERRnW7NyYN uOE9v4KY+Mfxx1XKoQClp1HQxf/rOwEYsQfEwJ2/byFDHweRIAow0CCKApQluxCLLeUj XeAXmQAwssIxAoE3aoDa7yuGeqnEfKW2M6/OO+eW+eLoo2A/t9ymvaDXbJOVu4/KpEAC M7UQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=AVmtnDTo; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id mp9-20020a1709071b0900b007b43ef7c08fsi8622513ejc.501.2022.11.27.20.48.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Nov 2022 20:48:48 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=AVmtnDTo; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AF96338A8157 for ; Mon, 28 Nov 2022 04:46:39 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org AF96338A8157 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1669610799; bh=KIqW8yPMFeAwnYpHVCBfAMQwGd4JwRwD5QyvnWMU1e4=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=AVmtnDTodDT20Y1GfGqNWKgfvbqZQY0Cc8FZUNVQDmlow8qtqnxXUzY/VMCA92yl8 Ob6qFhdH9MuvJrpGZfMeAEFb1UunvH/YxsgqEL9qQfy9HZtJsNtluoY5bTdqobuMJy ocpRWQmaTx93iqXviJfLPdnnJCSXJcsr6xq7kbtA= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id B0498384F884 for ; Mon, 28 Nov 2022 04:45:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B0498384F884 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 0BB77300089; Mon, 28 Nov 2022 04:45:08 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH v2 06/11] RISC-V: Use static xlen on ADDIW sequence Date: Mon, 28 Nov 2022 04:43:41 +0000 Message-Id: <072cb269b90f85fdfd880a6513080a18ddde015d.1669610611.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749537152408723609?= X-GMAIL-MSGID: =?utf-8?q?1750713948925169487?= From: Tsukasa OI Because XLEN for the disassembler is computed and stored in the xlen variable, this commit replaces uses of info->mach with xlen (when testing for ADDIW / C.ADDIW address sequence). Not just we used two ways to determine current XLEN, info->mach and xlen, xlen is going to be more important in the future commits. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Use xlen variable to determine whether XLEN is larger than 32. --- opcodes/riscv-dis.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 51a08d847b10..4c193624039e 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -261,7 +261,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info case 'j': if (((l & MASK_C_ADDI) == MATCH_C_ADDI) && rd != 0) maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 0); - if (info->mach == bfd_mach_riscv64 + if (xlen > 32 && ((l & MASK_C_ADDIW) == MATCH_C_ADDIW) && rd != 0) maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 1); print (info->stream, dis_style_immediate, "%d", @@ -461,7 +461,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0) || (l & MASK_JALR) == MATCH_JALR) maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0); - if (info->mach == bfd_mach_riscv64 + if (xlen > 32 && ((l & MASK_ADDIW) == MATCH_ADDIW) && rs1 != 0) maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 1); print (info->stream, dis_style_immediate, "%d", From patchwork Mon Nov 28 04:43:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 26503 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5433994wrr; Sun, 27 Nov 2022 20:50:52 -0800 (PST) X-Google-Smtp-Source: AA0mqf508KsAahWdzenP95gcQrM21qEmpB2GmHQj5gGDaygIPUoxQF+FrH9oO9BG53FGwgs966L6 X-Received: by 2002:a17:906:36d2:b0:7ae:9c7b:4d5c with SMTP id b18-20020a17090636d200b007ae9c7b4d5cmr40494570ejc.598.1669611052427; Sun, 27 Nov 2022 20:50:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669611052; cv=none; d=google.com; s=arc-20160816; b=i5IP8X2Gz5Lw8XvMbznmNQkqsrPdXWi2xayFL7o9uWcnUVqNbMuqYzuir9L/3o8hiD Bh4rp5ocf3PbdRkKomSz5gmsSZxqrZxcqA54hLZIWltkSTTlWnKhrn/B5xrp1YrDPH9d ScvYX3mMChRm+Qno5770U25FLLzYcod+MGweJvLx0GrlvAfs7YIO/c6HBLqraIx1LXw/ j+uWH6FqKrIpWmMQXHr1o8fkA3O++1Qzn847uOawFC19xbgC2GPXmx1UAAnKO0gPRfmV JRRqWmDCyiS92/Udvr+Mxd6I9zaQjTeSrOV7dkln+bbuUrxqFHOSMryAOqbhwFMR9L42 +1cw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=3fZOmhoy6r449OgFX9SrJitTz+6NUbxMucfwRdxfrOM=; b=quhedom8xG2oC4tI2Xg5IjMNkmycc7UdTHkL5R9LIDMvOm/bjG5bUVkdg/69OkWHl/ cum0pPG9jUc1X1gBASKmy9MabBKWzHjtBT22o6xMNOrBOB0WvYFmMg807kqz0QCDRdqX AUkgyKCKqT50Q+8z+YtbQfzLX3CJBDyD1TgJJvZ45O+OYoLRc3C2E4LhVk1xtkDZR3VT OXy49NAy8sC1Ny7lsfl42D7H8WseWjRx5tD094I6oJFYfxJ7sEa4y59NWopHI7JKCzQY EujywOVdyehHBr5AK3Ktu1eh0R+yTE4VxqXf3DW8auIkeLD59H1Nw+LqffoMX9E96Vlc K6MA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=XrFxC3do; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id i17-20020a170906265100b0079198b89adbsi7524701ejc.890.2022.11.27.20.50.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Nov 2022 20:50:52 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=XrFxC3do; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 461BE385B189 for ; Mon, 28 Nov 2022 04:47:40 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 461BE385B189 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1669610860; bh=3fZOmhoy6r449OgFX9SrJitTz+6NUbxMucfwRdxfrOM=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=XrFxC3doeAFdiaXVk1nF9wRgw1Kr+uCuFtsU+pjKCB9K+ITR9yZWa/rrwFKTzq9Og q1JxeX51IVznbwWCuhJWvRNh47ujeqmSVBv9+XePLWH31ZYahdKuIBhKuc0/As5uv6 NY9tlhf73p2chQC+lTrl0kfGdkJw/i+CiQ6p5Kbg= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 36B483854550 for ; Mon, 28 Nov 2022 04:45:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 36B483854550 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 90EF5300089; Mon, 28 Nov 2022 04:45:18 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH v2 07/11] opcodes/riscv-dis.c: Add form feed for separation Date: Mon, 28 Nov 2022 04:43:42 +0000 Message-Id: <8f4167371bc52f2c4c7fc6f1a0fc3775e8e8de95.1669610611.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749536982044941449?= X-GMAIL-MSGID: =?utf-8?q?1750714078893629719?= From: Tsukasa OI This is a general tidying commit. opcodes/ChangeLog: * riscv-dis.c: Add lines with form feed to separate functional sections. --- opcodes/riscv-dis.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 4c193624039e..f5dc1907c6ec 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -72,7 +72,7 @@ static const char * const *riscv_fpr_names; /* If set, disassemble as most general instruction. */ static bool no_aliases = false; - + /* Set default RISC-V disassembler options. */ @@ -174,6 +174,7 @@ parse_riscv_dis_options (const char *opts_in) free (opts); } + /* Print one argument from an array. */ From patchwork Mon Nov 28 04:43:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 26498 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5433117wrr; Sun, 27 Nov 2022 20:47:19 -0800 (PST) X-Google-Smtp-Source: AA0mqf66tIlYcrtgWV9S/ZVjyjfotbjvGiYzNQcAXhRwO3WgNWN6vsNsWaOxQ3vvzneFjUStKuO3 X-Received: by 2002:a17:906:3c12:b0:7ad:7e81:1409 with SMTP id h18-20020a1709063c1200b007ad7e811409mr42072245ejg.326.1669610839397; Sun, 27 Nov 2022 20:47:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669610839; cv=none; d=google.com; s=arc-20160816; b=L5K/8qFlwDKNW/7pc7gRyOZ9A6iuJ8hTzfO2QsqZW73Wpq2OSttSInxlbYMMNxe5vx wVHPbLreaiLyfwvi7kNktnodwBcrYFAThl9NdM/iW9tjX9mXfGBh0NWXPSGOLfid1ehw Y82dIWqEqJufWBqAvMyRXp0LDN0iyTxZXtJQTlb1WeM9XE4Nk4uHLQEh3+FKzrHWCW9d CmGZPG/p3EI8UqpNYZEzZ9mfRMImme8FNEpt3x1Wo6ApfhifENZMns5Yi5WkoVLtiODo G/BUM2ZgGdUJCHNkglO923JEjxWZQKV/cjvOhAYavhSOtaVEEXyIszULZNvIWY6STlT5 Nhug== ARC-Message-Signature: i=1; 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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id z3-20020a1709067e4300b0078e1e77f443si7492328ejr.418.2022.11.27.20.47.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Nov 2022 20:47:19 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=Au0LtLRC; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 196103889C9B for ; Mon, 28 Nov 2022 04:45:47 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 196103889C9B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1669610747; bh=yuHfLFlk929sqVLl7ONSiEsUZsFEQhVr1rqulntLglU=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=Au0LtLRCSWgh0zbZ/Xqgdyyqlv2cxD3siwQnp5D5bJH+bzeDo/Ov0W9QLQSNR7MlD uU1o50RFGUfQCuwJaiFV5SPYHdhOjC2R+HyTXkvGrZ6UKC8/QGpPDXAJQPpEqyw//y OQ07tuLnZBRGtYQdjZayK4QIy3AtXKhbX02wzD1c= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id B9502384F6E2 for ; Mon, 28 Nov 2022 04:45:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B9502384F6E2 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 1C129300089; Mon, 28 Nov 2022 04:45:29 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH v2 08/11] RISC-V: Split match/print steps on disassembler Date: Mon, 28 Nov 2022 04:43:43 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749536959919471200?= X-GMAIL-MSGID: =?utf-8?q?1750713855315084137?= From: Tsukasa OI For further optimization and more disassembler features, we may need to change the core RISC-V instruction matching. For this purpose, it is inconvenient to have "match" and "print" steps in the same loop. This commit rewrites riscv_disassemble_insn function so that we store matched_op for matching RISC-V opcode and then print it (if not NULL). Although it looks a bit inefficient, it also lowers the indent of opcode matching loop to clarify the opcode matching changes on the next optimization commit. Unfortunately, this commit alone will impose some performance penalty (<5% on most cases but sometimes about 15% worse) but it can be easily paid back by other optimizations. opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_insn): Split instruction handling to two separate steps - opcode matching and printing. --- opcodes/riscv-dis.c | 151 +++++++++++++++++++++++--------------------- 1 file changed, 79 insertions(+), 72 deletions(-) diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index f5dc1907c6ec..c74827ed19df 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -649,7 +649,7 @@ riscv_disassemble_insn (bfd_vma memaddr, const bfd_byte *packet, disassemble_info *info) { - const struct riscv_opcode *op; + const struct riscv_opcode *op, *matched_op; static bool init = false; static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1]; struct riscv_private_data *pd; @@ -705,85 +705,92 @@ riscv_disassemble_insn (bfd_vma memaddr, info->target = 0; info->target2 = 0; + matched_op = NULL; op = riscv_hash[OP_HASH_IDX (word)]; - if (op != NULL) + + /* If XLEN is not known, get its value from the ELF class. */ + if (info->mach == bfd_mach_riscv64) + xlen = 64; + else if (info->mach == bfd_mach_riscv32) + xlen = 32; + else if (info->section != NULL) { - /* If XLEN is not known, get its value from the ELF class. */ - if (info->mach == bfd_mach_riscv64) - xlen = 64; - else if (info->mach == bfd_mach_riscv32) - xlen = 32; - else if (info->section != NULL) - { - Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner); - xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32; - } + Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner); + xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32; + } - /* If arch has the Zfinx extension, replace FPR with GPR. */ - if (riscv_subset_supports (&riscv_rps_dis, "zfinx")) - riscv_fpr_names = riscv_gpr_names; - else - riscv_fpr_names = riscv_gpr_names == riscv_gpr_names_abi ? - riscv_fpr_names_abi : riscv_fpr_names_numeric; + /* If arch has the Zfinx extension, replace FPR with GPR. */ + if (riscv_subset_supports (&riscv_rps_dis, "zfinx")) + riscv_fpr_names = riscv_gpr_names; + else + riscv_fpr_names = riscv_gpr_names == riscv_gpr_names_abi + ? riscv_fpr_names_abi + : riscv_fpr_names_numeric; - for (; op->name; op++) - { - /* Does the opcode match? */ - if (! (op->match_func) (op, word)) - continue; - /* Is this a pseudo-instruction and may we print it as such? */ - if (no_aliases && (op->pinfo & INSN_ALIAS)) - continue; - /* Is this instruction restricted to a certain value of XLEN? */ - if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen)) - continue; - /* Is this instruction supported by the current architecture? */ - if (!riscv_multi_subset_supports (&riscv_rps_dis, op->insn_class)) - continue; - - /* It's a match. */ - (*info->fprintf_styled_func) (info->stream, dis_style_mnemonic, - "%s", op->name); - print_insn_args (op->args, word, memaddr, info); - - /* Try to disassemble multi-instruction addressing sequences. */ - if (pd->to_print_addr) - { - info->target = pd->print_addr; - (*info->fprintf_styled_func) - (info->stream, dis_style_comment_start, " # "); - (*info->print_address_func) (info->target, info); - pd->to_print_addr = false; - } + for (; op && op->name; op++) + { + /* Does the opcode match? */ + if (!(op->match_func) (op, word)) + continue; + /* Is this a pseudo-instruction and may we print it as such? */ + if (no_aliases && (op->pinfo & INSN_ALIAS)) + continue; + /* Is this instruction restricted to a certain value of XLEN? */ + if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen)) + continue; + /* Is this instruction supported by the current architecture? */ + if (!riscv_multi_subset_supports (&riscv_rps_dis, op->insn_class)) + continue; - /* Finish filling out insn_info fields. */ - switch (op->pinfo & INSN_TYPE) - { - case INSN_BRANCH: - info->insn_type = dis_branch; - break; - case INSN_CONDBRANCH: - info->insn_type = dis_condbranch; - break; - case INSN_JSR: - info->insn_type = dis_jsr; - break; - case INSN_DREF: - info->insn_type = dis_dref; - break; - default: - break; - } + matched_op = op; + break; + } - if (op->pinfo & INSN_DATA_SIZE) - { - int size = ((op->pinfo & INSN_DATA_SIZE) - >> INSN_DATA_SIZE_SHIFT); - info->data_size = 1 << (size - 1); - } + if (matched_op != NULL) + { + /* There is a match. */ + op = matched_op; + + (*info->fprintf_styled_func) (info->stream, dis_style_mnemonic, + "%s", op->name); + print_insn_args (op->args, word, memaddr, info); - return insnlen; + /* Try to disassemble multi-instruction addressing sequences. */ + if (pd->to_print_addr) + { + info->target = pd->print_addr; + (*info->fprintf_styled_func) (info->stream, dis_style_comment_start, + " # "); + (*info->print_address_func) (info->target, info); + pd->to_print_addr = false; } + + /* Finish filling out insn_info fields. */ + switch (op->pinfo & INSN_TYPE) + { + case INSN_BRANCH: + info->insn_type = dis_branch; + break; + case INSN_CONDBRANCH: + info->insn_type = dis_condbranch; + break; + case INSN_JSR: + info->insn_type = dis_jsr; + break; + case INSN_DREF: + info->insn_type = dis_dref; + break; + default: + break; + } + + if (op->pinfo & INSN_DATA_SIZE) + { + int size = ((op->pinfo & INSN_DATA_SIZE) >> INSN_DATA_SIZE_SHIFT); + info->data_size = 1 << (size - 1); + } + + return insnlen; } /* We did not find a match, so just print the instruction bits. */ From patchwork Mon Nov 28 04:43:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 26506 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5434540wrr; Sun, 27 Nov 2022 20:53:13 -0800 (PST) X-Google-Smtp-Source: AA0mqf4Tocy09Bq5QlJ/88jr3dFtrVeaoqITHUDFQ7dBQl1iNFEJSxiSmstwm6u/ip+fNKiH3yig X-Received: by 2002:a17:906:c35a:b0:78d:2af:a818 with SMTP id ci26-20020a170906c35a00b0078d02afa818mr31003465ejb.675.1669611193264; Sun, 27 Nov 2022 20:53:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669611193; cv=none; d=google.com; s=arc-20160816; b=EChlmLaykC01KQRxUTFyNKQxGWKo96QU6hmYCUT32wohinNa/KBTuBdsIB1bs5ci5Q Zh4CgG5LE42/8PpmdiqA8CNM4oaVajf8brz5B2/ux1eLpzylqTsslV0YbhM93GeAcRtn uJqChEgis/QCaA7m2z/+8U0DZ1sEQh5DUzEyoecJPmhLq49JIHGWyVVFADXLD+fb+N5W dgYpMaiib+Uu85HcHllj26C+EwwubxCdKZPFteslRfyvjFFvLWVPc7bC73TkrYJCcJsl oJYjNN/GZjYzeYXIdNk7tWRCK/+zWWhk7IugIFfSPw/VFkFSEHvXQuBxJbVGSZd6O9oI DEKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=eJTBxZJ07t9eLkFU54I2JG47TRjQviaHdqcrHVUVufc=; b=CHLSKLLavl4SGtlOEhx57bOZwASy6X3I/5XI2Krksz3OxAvA5xiYWWwCkH886LMi44 XmsvFvMOz1MKP7zE8pH+d/Yn2pHbY8xnpfyUbycvsca3f2pH4AiG21gtu4P/PsIaG4oD XA6E73YYjskxLeQqsINY1gkAojPd6kUvGlHPc5qewFH3yz/m9M1BYoOnDQ0E97yLII0p 4GB1U6h9Zl4hlcVJ96DmSKA/fafcFSworOZB5QHHRA2av3ETjPl7K+vrBRJUxvYjSuEf JgXx5it9XgXpBsN7QDPaqSdbJDkzSyBapy6Pzub0EKWDOzsgEyHlBP4f0IwouhYG45Ir yTHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=k3JCP9ZB; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id ji9-20020a170907980900b007a46fa50b26si10400365ejc.517.2022.11.27.20.53.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Nov 2022 20:53:13 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=k3JCP9ZB; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 49364395B06F for ; Mon, 28 Nov 2022 04:48:43 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 49364395B06F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1669610923; bh=eJTBxZJ07t9eLkFU54I2JG47TRjQviaHdqcrHVUVufc=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=k3JCP9ZB0fY5BhlJ6o7hts3sdKSg2A3XlfHUab7XyFnCDdVY/icUJAAF2KiTiXHK6 dYD3YwHcNCkHQbPL35HdoUBsH15xRS7SINbDnbfaEvvvdxvyJyVVx8QdTcbIE1lwya 09slZALczFCDR6sbJQlmLPIR7rjOkvnucsbbOwzI= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 4712A3888C45 for ; Mon, 28 Nov 2022 04:45:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 4712A3888C45 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 9A539300089; Mon, 28 Nov 2022 04:45:39 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH v2 09/11] RISC-V: Reorganize disassembler state initialization Date: Mon, 28 Nov 2022 04:43:44 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749536954487615344?= X-GMAIL-MSGID: =?utf-8?q?1750714226563932149?= From: Tsukasa OI The current disassembler repeatedly checks current state per instruction: - Whether riscv_gpr_names is initialized to a non-NULL value - Whether the Zfinx extension is available - Whether the hash table is initialized ... but they are not frequently changed. riscv_gpr_names is initialized to a non-NULL value when - The first disassembler option is specified, or - Not initialized with disassembler options (in the first print_insn_riscv function call). We can safely initialize the default disassembler options prior to the print_insn_riscv function call and this per-instruction checking of riscv_gpr_names can be safely removed. The opcode hash table initialization will be taken care with a later commit. To group disassembler state initialization, this commit utilizes the disassemble_init_for_target function. As a side effect, this will also fix a potential issue when disassembler options is set and then unset on GDB. This idea is based on opcodes/ppc-dis.c and opcodes/wasm32-dis.c. New callback function init_riscv_dis_state_for_arch_and_options is called when either the architecture string or an option is possibly changed. We can now group the disassembler state initialization together. It makes state initialization clearer and makes further changes easier. In performance perspective, this commit has various effects (-5% to 6%). However, this commit makes implementing large optimizations easier as well as "RISC-V: Split match/print steps on disassembler". include/ChangeLog: * dis-asm.h (disassemble_init_riscv): Add declaration of disassemble_init_riscv. opcodes/ChangeLog: * disassemble.c (disassemble_init_for_target): Call disassemble_init_riscv to group state initialization together. * riscv-dis.c (xlen_by_mach, xlen_by_elf): New variables to store environment-inferred XLEN. (is_numeric): New. Instead of directly setting riscv_{gpr,fpr}_names, use this to store an option. (update_riscv_dis_xlen): New function to set actual XLEN from xlen_by_mach and xlen_by_elf variables. (init_riscv_dis_state_for_arch_and_options): New callback function called when either the architecture or an option is changed. Set riscv_{gpr,fpr}_names here. (set_default_riscv_dis_options): Initialize is_numeric instead of riscv_gpr_names and riscv_fpr_names. (parse_riscv_dis_option_without_args): When the "numeric" option is specified, write to is_numeric instead of register names. (parse_riscv_dis_options): Suppress setting the default options here and let disassemble_init_riscv to initialize them. (riscv_disassemble_insn): Move probing Zfinx and setting XLEN portions to init_riscv_dis_state_for_arch_and_options and update_riscv_dis_xlen. (riscv_get_map_state): If a mapping symbol with ISA string is suitable, call init_riscv_dis_state_for_arch_and_options function to update disassembler state. (print_insn_riscv): Update XLEN only if we haven't guessed correct XLEN for the disassembler. Stop checking disassembler options for every instruction and let disassemble_init_riscv to parse options. (riscv_get_disassembler): Call init_riscv_dis_state_for_arch_and_options because the architecture string is updated here. (disassemble_init_riscv): New function to initialize the structure, reset/guess correct XLEN and reset/parse disassembler options. --- include/dis-asm.h | 1 + opcodes/disassemble.c | 2 +- opcodes/riscv-dis.c | 112 +++++++++++++++++++++++++++++------------- 3 files changed, 79 insertions(+), 36 deletions(-) diff --git a/include/dis-asm.h b/include/dis-asm.h index 4921c0407102..11537b432ff0 100644 --- a/include/dis-asm.h +++ b/include/dis-asm.h @@ -393,6 +393,7 @@ extern bool arm_symbol_is_valid (asymbol *, struct disassemble_info *); extern bool csky_symbol_is_valid (asymbol *, struct disassemble_info *); extern bool riscv_symbol_is_valid (asymbol *, struct disassemble_info *); extern void disassemble_init_powerpc (struct disassemble_info *); +extern void disassemble_init_riscv (struct disassemble_info *); extern void disassemble_init_s390 (struct disassemble_info *); extern void disassemble_init_wasm32 (struct disassemble_info *); extern void disassemble_init_nds32 (struct disassemble_info *); diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index 0a8f2da629f3..704fb476ea9f 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -717,7 +717,7 @@ disassemble_init_for_target (struct disassemble_info * info) #endif #ifdef ARCH_riscv case bfd_arch_riscv: - info->symbol_is_valid = riscv_symbol_is_valid; + disassemble_init_riscv (info); info->created_styled_output = true; break; #endif diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index c74827ed19df..174b6e180543 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -35,6 +35,12 @@ /* Current XLEN for the disassembler. */ static unsigned xlen = 0; +/* XLEN as inferred by the machine architecture. */ +static unsigned xlen_by_mach = 0; + +/* XLEN as inferred by ELF header. */ +static unsigned xlen_by_elf = 0; + /* Default ISA specification version (constant as of now). */ static enum riscv_spec_class default_isa_spec = ISA_SPEC_CLASS_DRAFT - 1; @@ -72,6 +78,48 @@ static const char * const *riscv_fpr_names; /* If set, disassemble as most general instruction. */ static bool no_aliases = false; + +/* If set, disassemble with numeric register names. */ +static bool is_numeric = false; + + +/* Guess and update current XLEN. */ + +static void +update_riscv_dis_xlen (struct disassemble_info *info) +{ + /* Set XLEN with following precedence rules: + 1. BFD machine architecture set by either: + a. -m riscv:rv[32|64] option (GDB: set arch riscv:rv[32|64]) + b. ELF class in actual ELF header (only on RISC-V ELF) + This is only effective if XLEN-specific BFD machine architecture is + chosen. If XLEN-neutral (like riscv), BFD machine architecture is + ignored on XLEN selection. + 2. ELF class in dummy ELF header. */ + if (xlen_by_mach != 0) + xlen = xlen_by_mach; + else if (xlen_by_elf != 0) + xlen = xlen_by_elf; + else if (info != NULL && info->section != NULL) + { + Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner); + xlen = xlen_by_elf = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32; + } +} + +/* Initialization (for arch and options). */ + +static void +init_riscv_dis_state_for_arch_and_options (void) +{ + /* Set GPR register names to disassemble. */ + riscv_gpr_names = is_numeric ? riscv_gpr_names_numeric : riscv_gpr_names_abi; + /* Set FPR register names to disassemble. */ + riscv_fpr_names + = !riscv_subset_supports (&riscv_rps_dis, "zfinx") + ? (is_numeric ? riscv_fpr_names_numeric : riscv_fpr_names_abi) + : riscv_gpr_names; +} /* Set default RISC-V disassembler options. */ @@ -79,9 +127,8 @@ static bool no_aliases = false; static void set_default_riscv_dis_options (void) { - riscv_gpr_names = riscv_gpr_names_abi; - riscv_fpr_names = riscv_fpr_names_abi; no_aliases = false; + is_numeric = false; } /* Parse RISC-V disassembler option (without arguments). */ @@ -92,10 +139,7 @@ parse_riscv_dis_option_without_args (const char *option) if (strcmp (option, "no-aliases") == 0) no_aliases = true; else if (strcmp (option, "numeric") == 0) - { - riscv_gpr_names = riscv_gpr_names_numeric; - riscv_fpr_names = riscv_fpr_names_numeric; - } + is_numeric = true; else return false; return true; @@ -163,8 +207,6 @@ parse_riscv_dis_options (const char *opts_in) { char *opts = xstrdup (opts_in), *opt = opts, *opt_end = opts; - set_default_riscv_dis_options (); - for ( ; opt_end != NULL; opt = opt_end + 1) { if ((opt_end = strchr (opt, ',')) != NULL) @@ -708,25 +750,6 @@ riscv_disassemble_insn (bfd_vma memaddr, matched_op = NULL; op = riscv_hash[OP_HASH_IDX (word)]; - /* If XLEN is not known, get its value from the ELF class. */ - if (info->mach == bfd_mach_riscv64) - xlen = 64; - else if (info->mach == bfd_mach_riscv32) - xlen = 32; - else if (info->section != NULL) - { - Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner); - xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32; - } - - /* If arch has the Zfinx extension, replace FPR with GPR. */ - if (riscv_subset_supports (&riscv_rps_dis, "zfinx")) - riscv_fpr_names = riscv_gpr_names; - else - riscv_fpr_names = riscv_gpr_names == riscv_gpr_names_abi - ? riscv_fpr_names_abi - : riscv_fpr_names_numeric; - for (; op && op->name; op++) { /* Does the opcode match? */ @@ -869,6 +892,7 @@ riscv_get_map_state (int n, { riscv_release_subset_list (&riscv_subsets); riscv_parse_subset (&riscv_rps_dis, arch); + init_riscv_dis_state_for_arch_and_options (); } return true; } @@ -1067,14 +1091,9 @@ print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info) int (*riscv_disassembler) (bfd_vma, insn_t, const bfd_byte *, struct disassemble_info *); - if (info->disassembler_options != NULL) - { - parse_riscv_dis_options (info->disassembler_options); - /* Avoid repeatedly parsing the options. */ - info->disassembler_options = NULL; - } - else if (riscv_gpr_names == NULL) - set_default_riscv_dis_options (); + /* Guess and update XLEN if we haven't determined it yet. */ + if (xlen == 0) + update_riscv_dis_xlen (info); mstate = riscv_search_mapping_symbol (memaddr, info); @@ -1136,9 +1155,32 @@ riscv_get_disassembler (bfd *abfd) riscv_release_subset_list (&riscv_subsets); riscv_parse_subset (&riscv_rps_dis, default_arch); + init_riscv_dis_state_for_arch_and_options (); return print_insn_riscv; } +/* Initialize disassemble_info and parse options. */ + +void +disassemble_init_riscv (struct disassemble_info *info) +{ + info->symbol_is_valid = riscv_symbol_is_valid; + /* Clear previous XLEN and guess by mach. */ + xlen = 0; + xlen_by_mach = 0; + xlen_by_elf = 0; + if (info->mach == bfd_mach_riscv64) + xlen_by_mach = 64; + else if (info->mach == bfd_mach_riscv32) + xlen_by_mach = 32; + update_riscv_dis_xlen (info); + /* Parse disassembler options. */ + set_default_riscv_dis_options (); + if (info->disassembler_options != NULL) + parse_riscv_dis_options (info->disassembler_options); + init_riscv_dis_state_for_arch_and_options (); +} + /* Prevent use of the fake labels that are generated as part of the DWARF and for relaxable relocations in the assembler. */ From patchwork Mon Nov 28 04:43:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 26508 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5434896wrr; Sun, 27 Nov 2022 20:54:44 -0800 (PST) X-Google-Smtp-Source: AA0mqf6hSODRzFXhTefPPICRHap+TzL92PY6bClD4G4yLNnTT38qpFC54K9Ncj3y70k4D2OR8NIT X-Received: by 2002:a17:907:2a92:b0:7bd:7f47:d5bb with SMTP id fl18-20020a1709072a9200b007bd7f47d5bbmr9226455ejc.625.1669611284446; Sun, 27 Nov 2022 20:54:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669611284; cv=none; d=google.com; s=arc-20160816; b=KF1mftIg0EjRyTceZQrTZ2sPoFkDcp6lvHOI5wqA2BfoU8gLSqn6ymTTPkABfuJp91 87kUE8khVa4tf7JHc30im6GIdRCQzdAJYENLnXUboJr8+k6zt3dEumwKlJ/wlA3F6YJ7 nGzTOOfPIRafwZG+ZyCEZkhfGP1yvkrxfRAXqdd0LS4A/K5E9QG1cZwJbbrH4R2q+mXu 017fco6a8OmJQ46kRWqKGOTG01CQL1VkdEWyj58nwpF2eXORGERDUC7RNsig1OxJtQNH 6dYbkngLq68rXizkPyqmI263huuW84/RpArlWv5/47cDq1jP0vFAADVj1TdmTRXTbrVo hlFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=Xv9yCy6nrI/FYewetKSo2IdLHAkBweuCgPGwJaVFQOs=; b=x2Otlq97i6oKdKN9kezsvQ6K4+MoPyxAVG2Eh0ZJRVLa0h1VwnbKJx0t4zmrMYV1s6 UuCvVCS+o+RSN+ALGKRUhqdocn6yyvSr3X1F25uwnIQxCfKhfdMn3XnRixSkR9uDxZsn 1/USMwT3XqouHBg7LX6us1PJSG/Cx6A5l+TifwKDj8PYxPyIEgko//h1S2GAvBQiv9Tn KNQBzK34qqCyfQcK/VEeQrq7i+vfC0ImYHzEP0QqU5ywtxQqOAGxpqjltZ/A/dN8P13t +uakrdMB2z03zsai7YSUCeZaiK7f3VJhDLv2Z7y7Zyawh3j7TqHP2gpB9zn7vTAZOJ8a HXkQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=gaK7aiso; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id g23-20020a170906349700b007b790c183cdsi7173617ejb.266.2022.11.27.20.54.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Nov 2022 20:54:44 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=gaK7aiso; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 99F51395C03E for ; Mon, 28 Nov 2022 04:49:45 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 99F51395C03E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1669610985; bh=Xv9yCy6nrI/FYewetKSo2IdLHAkBweuCgPGwJaVFQOs=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=gaK7aisoWISawDkwso63gKIySfdfzR3c0mlNtc+mVo/DY24IL6xlOvXysv8rG/Nee dVeHeQfXcevSBOP0u0e/YfQ6t8xlMP+xvML93rUjJKhqW30gFSFUezGD1ArLe8PvaW nAbgBFZ62jFg1Nyzr1FX8NUGVO6dwKd++pm8pW10= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id C974A38432D1 for ; Mon, 28 Nov 2022 04:45:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C974A38432D1 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 28693300089; Mon, 28 Nov 2022 04:45:50 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH v2 10/11] RISC-V: Reorganize arch-related initialization and management Date: Mon, 28 Nov 2022 04:43:45 +0000 Message-Id: <0e328130d90af42f30e3632fadd6c48e422b7b82.1669610611.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749537199887855908?= X-GMAIL-MSGID: =?utf-8?q?1750714321840506126?= From: Tsukasa OI objdump reuses the disassembler function returned by the disassembler function. That's good and benefits well from various optimizations. However, by default, GDB (default_print_insn in gdb/arch-utils.c) assumes that the disassembler function logic is simple and calls that function for every instruction to be disassembled. This is clearly a waste of time because it probes BFD (ELF information) and re-initializes riscv_rps_dis for every instruction. After the support of mapping symbol with ISA string with commit 40f1a1a4564b ("RISC-V: Output mapping symbols with ISA string."), this kind of per- instruction initialization of riscv_rps_dis can also occur on ELF files with mapping symbol + ISA string (in riscv_get_map_state function). It can be worse if the object is assembled using Binutils commit 0ce50fc900a5 ("RISC-V: Always generate mapping symbols at the start of the sections.") or later. To avoid repeated initialization, this commit - Caches the default / override architectures (in two "contexts") and - enables switching between them. riscv_dis_arch_context_t and new utility functions are defined for this purpose. We still have to read the ".riscv.attributes" section on every instruction on GDB but at least the most time-consuming part (updating the actual architecture from the architecture string) is avoided. Likewise, we still have to probe whether we have to update the architecture for every instruction with a mapping symbol with ISA string is suitable but at least we don't actually update the architecture unless necessary (either context itself or the ISA string of the current context is changed). This commit improves the disassembler performance well in those situations: - When long "disas" command is used on GDB - When ELF files with mapping symbols + ISA string is used This commit now implements new mapping symbol handling ("$x" means revert to the previous architecture [with "$x+arch"] if exists, otherwise revert to the default one usually read from an ELF attribute), the recent consensus made by Kito and Nelson. On the benchmark using GDB batch files, the author measured significant performance improvements (35-96% on various big RISC-V programs). Unfortunately, on interactive usecases of GDB, this improvement is rarely observable since we don't usually disassemble such a big chunk at once and the current disassembler is not very slow. On the benchmark using unstripped ELF files with mapping symbols + ISA string "$xrv...", performance improvements are significant and easily observable in the real world (150%-264% performance improvments). Aside from optimization, this commit, along with "RISC-V: Reorganize disassembler state initialization", makes state initialization clearer and makes further changes easier. Also, although not practical in the real world, this commit now allows multi-XLEN object disassembling if the object file has mapping symbols with ISA string and the machine is XLEN-neutral (e.g. objdump with "-m riscv" option). It may help testing Binutils / GAS. opcodes/ChangeLog: * riscv-dis.c (initial_default_arch): Special default architecture string which is handled separately. (riscv_dis_arch_context_t): New type to manage RISC-V architecture context for the disassembler. Two instance of this type is defined in this file - "default" and "override". (dis_arch_context_default): New. Architecture context inferred from either an ELF attribute or initial_default_arch. (dis_arch_context_override): New. Architecture context inferred from mapping symbols with ISA string. (dis_arch_context_current): New. A pointer to either dis_arch_context_default or dis_arch_context_override. (riscv_rps_dis): Add summary. Use initial values from the initial value of dis_arch_context_current - dis_arch_context_default. (from_last_map_symbol): Make it file scope to decide whether we should revert the architecture to the default in riscv_get_map_state function. (set_riscv_current_dis_arch_context): New function to update riscv_rps_dis and dis_arch_context_current. (set_riscv_dis_arch_context): New function to update the architecture for the given context. (update_riscv_dis_xlen): Consider dis_arch_context_current->xlen when guessing correct XLEN. (is_arch_changed): New. Set to true if the architecture is changed. (init_riscv_dis_state_for_arch): New function to track whether the architecture string is changed. (init_riscv_dis_state_for_arch_and_options): Keep track of the architecture string change and update XLEN if it has changed. (update_riscv_dis_arch): New function to set both the architecture and the context. Call initialization functions if needed. (riscv_get_map_state): Add update argument. Keep track of the mapping symbols with ISA string and update the architecture and the context if required. (riscv_search_mapping_symbol): Move from_last_map_symbol to file scope. Call riscv_get_map_state function with architecture and context updates enabled. (riscv_data_length): Call riscv_get_map_state function with architecture and context updates disabled. (riscv_get_disassembler): Add an error handling on Tag_RISCV_arch. Call update_riscv_dis_arch function to update the architecture and the context. Co-developed-by: Nelson Chu --- opcodes/riscv-dis.c | 174 ++++++++++++++++++++++++++++++++++++++------ 1 file changed, 152 insertions(+), 22 deletions(-) diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 174b6e180543..d48448bb3597 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -32,6 +32,9 @@ #include #include +/* Default architecture string (if not available). */ +static const char *const initial_default_arch = "rv64gc"; + /* Current XLEN for the disassembler. */ static unsigned xlen = 0; @@ -48,14 +51,36 @@ static enum riscv_spec_class default_isa_spec = ISA_SPEC_CLASS_DRAFT - 1; (as specified by the ELF attributes or the `priv-spec' option). */ static enum riscv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE; -static riscv_subset_list_t riscv_subsets; +/* RISC-V disassembler architecture context type. */ +typedef struct +{ + const char *arch_str; + const char *default_arch; + riscv_subset_list_t subsets; + unsigned xlen; + bool no_xlen_if_default; +} riscv_dis_arch_context_t; + +/* Context: default (either initial_default_arch or ELF attribute). */ +static riscv_dis_arch_context_t dis_arch_context_default + = { NULL, initial_default_arch, {}, 0, true }; + +/* Context: override (mapping symbols with ISA string). */ +static riscv_dis_arch_context_t dis_arch_context_override + = { NULL, NULL, {}, 0, false }; + +/* Pointer to the current disassembler architecture context. */ +static riscv_dis_arch_context_t *dis_arch_context_current + = &dis_arch_context_default; + +/* RISC-V ISA string parser structure (current). */ static riscv_parse_subset_t riscv_rps_dis = { - &riscv_subsets, /* subset_list. */ - opcodes_error_handler,/* error_handler. */ - &xlen, /* xlen. */ - &default_isa_spec, /* isa_spec. */ - false, /* check_unknown_prefixed_ext. */ + &(dis_arch_context_default.subsets), /* subset_list. */ + opcodes_error_handler, /* error_handler. */ + &(dis_arch_context_default.xlen), /* xlen. */ + &default_isa_spec, /* isa_spec. */ + false, /* check_unknown_prefixed_ext. */ }; /* Private data structure for the RISC-V disassembler. */ @@ -71,6 +96,7 @@ struct riscv_private_data /* Used for mapping symbols. */ static int last_map_symbol = -1; static bfd_vma last_stop_offset = 0; +static bool from_last_map_symbol = false; /* Register names as used by the disassembler. */ static const char * const *riscv_gpr_names; @@ -83,6 +109,59 @@ static bool no_aliases = false; static bool is_numeric = false; +/* Set current disassembler context (dis_arch_context_current). + Return true if successfully updated. */ + +static bool +set_riscv_current_dis_arch_context (riscv_dis_arch_context_t* context) +{ + if (context == dis_arch_context_current) + return false; + dis_arch_context_current = context; + riscv_rps_dis.subset_list = &(context->subsets); + riscv_rps_dis.xlen = &(context->xlen); + return true; +} + +/* Update riscv_dis_arch_context_t by an ISA string. + Return true if the architecture is updated by arch. */ + +static bool +set_riscv_dis_arch_context (riscv_dis_arch_context_t *context, + const char *arch) +{ + /* Check whether the architecture is changed and + return false if the architecture will not be changed. */ + if (context->arch_str) + { + if (context->default_arch && arch == context->default_arch) + return false; + if (strcmp (context->arch_str, arch) == 0) + return false; + } + /* Update architecture string. */ + if (context->arch_str != context->default_arch) + free ((void *) context->arch_str); + context->arch_str = (arch != context->default_arch) + ? xstrdup (arch) + : context->default_arch; + /* Update other contents (subset list and XLEN). */ + riscv_subset_list_t *prev_subsets = riscv_rps_dis.subset_list; + unsigned *prev_xlen = riscv_rps_dis.xlen; + riscv_rps_dis.subset_list = &(context->subsets); + riscv_rps_dis.xlen = &(context->xlen); + context->xlen = 0; + riscv_release_subset_list (&context->subsets); + riscv_parse_subset (&riscv_rps_dis, context->arch_str); + riscv_rps_dis.subset_list = prev_subsets; + riscv_rps_dis.xlen = prev_xlen; + /* Special handling on the default architecture. */ + if (context->no_xlen_if_default && arch == context->default_arch) + context->xlen = 0; + return true; +} + + /* Guess and update current XLEN. */ static void @@ -95,9 +174,13 @@ update_riscv_dis_xlen (struct disassemble_info *info) This is only effective if XLEN-specific BFD machine architecture is chosen. If XLEN-neutral (like riscv), BFD machine architecture is ignored on XLEN selection. - 2. ELF class in dummy ELF header. */ + 2. Non-default RISC-V architecture string set by either an ELF + attribute or a mapping symbol with ISA string. + 3. ELF class in dummy ELF header. */ if (xlen_by_mach != 0) xlen = xlen_by_mach; + else if (dis_arch_context_current->xlen != 0) + xlen = dis_arch_context_current->xlen; else if (xlen_by_elf != 0) xlen = xlen_by_elf; else if (info != NULL && info->section != NULL) @@ -107,11 +190,24 @@ update_riscv_dis_xlen (struct disassemble_info *info) } } +/* Initialization (for arch). */ + +static bool is_arch_changed = false; + +static void +init_riscv_dis_state_for_arch (void) +{ + is_arch_changed = true; +} + /* Initialization (for arch and options). */ static void init_riscv_dis_state_for_arch_and_options (void) { + /* If the architecture string is changed, update XLEN. */ + if (is_arch_changed) + update_riscv_dis_xlen (NULL); /* Set GPR register names to disassemble. */ riscv_gpr_names = is_numeric ? riscv_gpr_names_numeric : riscv_gpr_names_abi; /* Set FPR register names to disassemble. */ @@ -119,6 +215,25 @@ init_riscv_dis_state_for_arch_and_options (void) = !riscv_subset_supports (&riscv_rps_dis, "zfinx") ? (is_numeric ? riscv_fpr_names_numeric : riscv_fpr_names_abi) : riscv_gpr_names; + /* Save previous options and mark them "unchanged". */ + is_arch_changed = false; +} + +/* Update architecture for disassembler with its context. + Call initialization functions if either: + - the architecture for current context is changed or + - context is updated to a new one. */ + +static void +update_riscv_dis_arch (riscv_dis_arch_context_t *context, const char *arch) +{ + if ((set_riscv_dis_arch_context (context, arch) + && dis_arch_context_current == context) + || set_riscv_current_dis_arch_context (context)) + { + init_riscv_dis_state_for_arch (); + init_riscv_dis_state_for_arch_and_options (); + } } @@ -874,7 +989,8 @@ riscv_get_map_state_by_name (const char *name, const char** arch) static bool riscv_get_map_state (int n, enum riscv_seg_mstate *state, - struct disassemble_info *info) + struct disassemble_info *info, + bool update) { const char *name, *arch = NULL; @@ -888,12 +1004,25 @@ riscv_get_map_state (int n, if (newstate == MAP_NONE) return false; *state = newstate; - if (arch) - { - riscv_release_subset_list (&riscv_subsets); - riscv_parse_subset (&riscv_rps_dis, arch); - init_riscv_dis_state_for_arch_and_options (); - } + if (newstate == MAP_INSN && update) + { + if (arch) + { + /* Override the architecture. */ + update_riscv_dis_arch (&dis_arch_context_override, arch); + } + else if (!from_last_map_symbol + && set_riscv_current_dis_arch_context (&dis_arch_context_default)) + { + /* Revert to the default architecture and call init functions if: + - there's no ISA string in the mapping symbol, + - mapping symbol is not reused and + - current disassembler context is changed to the default one. + This is a shortcut path to avoid full update_riscv_dis_arch. */ + init_riscv_dis_state_for_arch (); + init_riscv_dis_state_for_arch_and_options (); + } + } return true; } @@ -905,7 +1034,6 @@ riscv_search_mapping_symbol (bfd_vma memaddr, struct disassemble_info *info) { enum riscv_seg_mstate mstate; - bool from_last_map_symbol; bool found = false; int symbol = -1; int n; @@ -945,7 +1073,7 @@ riscv_search_mapping_symbol (bfd_vma memaddr, /* We have searched all possible symbols in the range. */ if (addr > memaddr) break; - if (riscv_get_map_state (n, &mstate, info)) + if (riscv_get_map_state (n, &mstate, info, true)) { symbol = n; found = true; @@ -972,7 +1100,7 @@ riscv_search_mapping_symbol (bfd_vma memaddr, if (addr < (info->section ? info->section->vma : 0)) break; /* Stop searching once we find the closed mapping symbol. */ - if (riscv_get_map_state (n, &mstate, info)) + if (riscv_get_map_state (n, &mstate, info, true)) { symbol = n; found = true; @@ -1008,7 +1136,7 @@ riscv_data_length (bfd_vma memaddr, { bfd_vma addr = bfd_asymbol_value (info->symtab[n]); if (addr > memaddr - && riscv_get_map_state (n, &m, info)) + && riscv_get_map_state (n, &m, info, false)) { if (addr - memaddr < length) length = addr - memaddr; @@ -1134,7 +1262,7 @@ print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info) disassembler_ftype riscv_get_disassembler (bfd *abfd) { - const char *default_arch = "rv64gc"; + const char *default_arch = initial_default_arch; if (abfd && bfd_get_flavour (abfd) == bfd_target_elf_flavour) { @@ -1150,12 +1278,14 @@ riscv_get_disassembler (bfd *abfd) attr[Tag_c].i, &default_priv_spec); default_arch = attr[Tag_RISCV_arch].s; + /* For ELF files with (somehow) no architecture string + in the attributes, use the default value. */ + if (!default_arch) + default_arch = initial_default_arch; } } - riscv_release_subset_list (&riscv_subsets); - riscv_parse_subset (&riscv_rps_dis, default_arch); - init_riscv_dis_state_for_arch_and_options (); + update_riscv_dis_arch (&dis_arch_context_default, default_arch); return print_insn_riscv; } From patchwork Mon Nov 28 04:43:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 26500 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp5433584wrr; Sun, 27 Nov 2022 20:49:08 -0800 (PST) X-Google-Smtp-Source: AA0mqf7UTZ/wVGLI74LPp69khrPPDYlzq+NJZbBfEiyEpgA3Jqm3j0cR5ZuOnOOEOsh+NaOn/bdB X-Received: by 2002:aa7:ce86:0:b0:46b:1872:4194 with SMTP id y6-20020aa7ce86000000b0046b18724194mr4396522edv.362.1669610947988; Sun, 27 Nov 2022 20:49:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669610947; cv=none; d=google.com; s=arc-20160816; b=Eljub8JBGPaP/qnhX+j6JUxT8NqtraqiOdfF9fozNSdVjxZGQJelMefpNxs2X85PLL OZ2x7ZRzohu2Szph7tZaG/od9XyTvz35c/O0IuiynTo1d9zD5jh3HJHZDaprMgP0RssI w3Z/t5zwB/SCAj4Ag42KCvMiF7LfRXjQqvUvCytsNVnKt03bBIpxcOQqNidfo8aJUJm7 lCQk74xl9FjN5KguolauUokeuINQxIB7YPrKRzzYnPo3DOU3HJrm+YdLlZ3f2n2JQb2S IJAmsdzCLV03pZ2qdiKOp+dyT8XrDK9HaRVX8YNazF8GX/MBh56AJWDpdeQAGFFCu+dw TX+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=XSZD37qTJXO+TRvhUYpKHayjZGjaqevy/t0aZ5yKNqw=; b=wfXNWEygJ5bEz+IVDXrW+gUhPqZ2+SLAC6V1sBTZ+EOeSZ2NvQ08w/IypHQUmlUdzb 8WB8W5CsHKK5vGkQjIuwntVLiwIJ+1PLQ61i+qnetTfyqRKAAy3YtLlFse9lDiCQFuGN k+N67Xrb/36+K7VOVpOJDckeR8/NbzLgMMM8T6Y7TdQgRya52bp9Fngfa9QmE57ENA5n JsoYbAJ964LI5pQMpP9cLzodwj09OOM7yRbulhP0oZeCudXAO2smPfhSaJSU+zbzVpCn 5aYrM52HCJSekKR5DfVwLOHhg3VSKuX9OZGPjZVamARCc05jP3hpgb6jATMzxBve5aTX 6oUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=ZeLEc7y1; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id hr39-20020a1709073fa700b007aae0b30283si9680749ejc.691.2022.11.27.20.49.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Nov 2022 20:49:07 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=ZeLEc7y1; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0D78F38532C6 for ; Mon, 28 Nov 2022 04:46:51 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0D78F38532C6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1669610811; bh=XSZD37qTJXO+TRvhUYpKHayjZGjaqevy/t0aZ5yKNqw=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=ZeLEc7y1mhe8PJ0w55xQmCsHmb5wmUaZZ+nmR0v4saJWazRJcBdWu7FHmS7zsZxZQ fbcxjXJZIrwiWEfStzCNGUrYFxtzRiVJaV8yVDXld3Q0Cg0iyC2jdjOkQ0FaZhbB/w 2GccaL7gKfpSLfC5Yh2nzupXdqrM/DloqVS4eWdU= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 53CB33855175 for ; Mon, 28 Nov 2022 04:46:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 53CB33855175 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id AEA06300089; Mon, 28 Nov 2022 04:46:00 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH v2 11/11] RISC-V: Move disassembler private data initialization Date: Mon, 28 Nov 2022 04:43:46 +0000 Message-Id: <75d9e5b0cfebcce34c855e4c98a956de4d7d7753.1669610611.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749537243984054289?= X-GMAIL-MSGID: =?utf-8?q?1750713969388692992?= From: Tsukasa OI Because disassemble_info.private_data could be used not only by riscv_disassemble_insn, this commit splits the initialization of the private data to a separate function. This commit now allows storing mapping symbol and/or section-related information to riscv_private_data. In performance perspective, it also has a penalty. However, it can be easily paid back by other optimizations and it makes implementing some optimizations easier. opcodes/ChangeLog: * riscv-dis.c (init_riscv_dis_private_data): New. (riscv_disassemble_insn): Move private data initialization to init_riscv_dis_private_data. (print_insn_riscv): Start initializing the private data instead of instruction only riscv_disassemble_insn function. --- opcodes/riscv-dis.c | 51 +++++++++++++++++++++++++-------------------- 1 file changed, 28 insertions(+), 23 deletions(-) diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index d48448bb3597..b9309c092b17 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -219,6 +219,29 @@ init_riscv_dis_state_for_arch_and_options (void) is_arch_changed = false; } +/* Initialize private data of the disassemble_info. */ + +static void +init_riscv_dis_private_data (struct disassemble_info *info) +{ + struct riscv_private_data *pd; + + pd = info->private_data = xcalloc (1, sizeof (struct riscv_private_data)); + pd->gp = 0; + pd->print_addr = 0; + for (int i = 0; i < (int)ARRAY_SIZE (pd->hi_addr); i++) + pd->hi_addr[i] = -1; + pd->to_print_addr = false; + pd->has_gp = false; + + for (int i = 0; i < info->symtab_size; i++) + if (strcmp (bfd_asymbol_name (info->symtab[i]), RISCV_GP_SYMBOL) == 0) + { + pd->gp = bfd_asymbol_value (info->symtab[i]); + pd->has_gp = true; + } +} + /* Update architecture for disassembler with its context. Call initialization functions if either: - the architecture for current context is changed or @@ -809,7 +832,7 @@ riscv_disassemble_insn (bfd_vma memaddr, const struct riscv_opcode *op, *matched_op; static bool init = false; static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1]; - struct riscv_private_data *pd; + struct riscv_private_data *pd = info->private_data; int insnlen; #define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : OP_MASK_OP)) @@ -824,28 +847,6 @@ riscv_disassemble_insn (bfd_vma memaddr, init = true; } - if (info->private_data == NULL) - { - int i; - - pd = info->private_data = xcalloc (1, sizeof (struct riscv_private_data)); - pd->gp = 0; - pd->print_addr = 0; - for (i = 0; i < (int)ARRAY_SIZE (pd->hi_addr); i++) - pd->hi_addr[i] = -1; - pd->to_print_addr = false; - pd->has_gp = false; - - for (i = 0; i < info->symtab_size; i++) - if (strcmp (bfd_asymbol_name (info->symtab[i]), RISCV_GP_SYMBOL) == 0) - { - pd->gp = bfd_asymbol_value (info->symtab[i]); - pd->has_gp = true; - } - } - else - pd = info->private_data; - insnlen = riscv_insn_length (word); /* RISC-V instructions are always little-endian. */ @@ -1219,6 +1220,10 @@ print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info) int (*riscv_disassembler) (bfd_vma, insn_t, const bfd_byte *, struct disassemble_info *); + /* Initialize the private data. */ + if (info->private_data == NULL) + init_riscv_dis_private_data (info); + /* Guess and update XLEN if we haven't determined it yet. */ if (xlen == 0) update_riscv_dis_xlen (info);