From patchwork Fri Nov 25 11:42:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 25950 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp3949413wrr; Fri, 25 Nov 2022 03:43:38 -0800 (PST) X-Google-Smtp-Source: AA0mqf7KE9YI8ziyyYzZcHfiVTiX9rMY0IyvPctVT9HYPnNS1Ko1SUMrTcWldiiPJ7X66feV6kDw X-Received: by 2002:a05:6402:530b:b0:461:f919:caa4 with SMTP id eo11-20020a056402530b00b00461f919caa4mr34853707edb.255.1669376618734; Fri, 25 Nov 2022 03:43:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669376618; cv=none; d=google.com; s=arc-20160816; b=arwyIHyFgqNk7TZxiqElyxEFm6Hvuwtgy+6HnrqsN4Wbu7BTL7lUUal62qqfZnKZiQ CVOCwvBlY5A7rLU6KiZG5u7dXfPTb+hPDVc3UdYAFkVgITxnZw9k1RNLpw/2FFv69lgG 2McIZZLS/6ouoNqnwO7vCQY3vFlL0e6hHbeV6iGBC96/dFsu5VOFeKTxGbCBZH1TFNhm b3PiAZ2bHiJfcgE8ePAA0cZ1twI90nKn5ncr8IJ3kWt5nObPZzfNtUsAwOJnBMQR+cG/ bUwb/t+Q8tRUVfEXHoq9f/mGwDaRJoVAUe29k4joNtuvrkzw8JAmm0G6I4tv+w9yM5SK 31+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=SixdbpPU9QjqdR1hLfMZEqE2UlxzSRIQKVUHM5rhJCI=; b=h9ydLpA7Sk1Zy/knideY4PKpczUR72Mw/uS3lLhFoIsXKfE35dCp2X1k57qKJ/S6nc Psyv+XArJIDozHCZxMtXxg/78nsVKpRV4eiRf0UkroecrlAzSPxidlv72khveegmkyLL P9byAeK+pRLsyPh28A2SoiEeoEh3ev+NNdCdsvvuh7Wz8K9auf9GCSUtLqRqC+jo3xJu fewWP9fphmbkhC54sTeN3hW9eLtHrwiM25ObNQNRRUv8aeVaNHY1v98P6k6P2TO/qAA+ OQvJQsktY+tAF1uuRoYPC1hIJX4zwSa8lcHabBWvbUsryrxpQ7uq5yMpIA8gqiVmtpQb vImw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=eSCq13NS; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id t13-20020a170906178d00b007aac98ec3dfsi1748180eje.303.2022.11.25.03.43.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 03:43:38 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=eSCq13NS; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4165038400BF for ; Fri, 25 Nov 2022 11:43:09 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4165038400BF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1669376589; bh=SixdbpPU9QjqdR1hLfMZEqE2UlxzSRIQKVUHM5rhJCI=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=eSCq13NSwxYfKoo7gFKJzlo8JiHo2Ze71dsaqpMeYuVyuUnA7lSqOvq0jA64B+M3e 3Q0IJhyw7VsEArJ2/jP7kxkpwhfXmT4JtdKgx7HaamhLWZXWoBfxAoUI2Nid1UUZ+n 4KY3/qcP4hHD3N6B8EmngdkGOx8p5bDFh3gfKpMc= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id F0472384E39E for ; Fri, 25 Nov 2022 11:42:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org F0472384E39E Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 5617D300089; Fri, 25 Nov 2022 11:42:36 +0000 (UTC) To: Tsukasa OI , Jan Beulich , Nelson Chu Cc: binutils@sourceware.org Subject: [PATCH v4 1/3] RISC-V: Better support for long instructions (disassembler) Date: Fri, 25 Nov 2022 11:42:20 +0000 Message-Id: <2c04525e48f5fc135b6dcb35ca6f1fec4e9b122b.1669376539.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750432667094790247?= X-GMAIL-MSGID: =?utf-8?q?1750468257281793241?= From: Tsukasa OI Commit bb996692bd96 ("RISC-V/gas: allow generating up to 176-bit instructions with .insn") tried to start supporting long instructions but it was insufficient. On the disassembler, correct ".byte" output was limited to the first 64-bits of an instruction. After that, zeroes are incorrectly printed. Note that, it only happens on ".byte" output (instruction part) and not on hexdump (data) part. For example, before this commit, hexdump and ".byte" produces different values: Assembly: .insn 22, 0xfedcba98765432100123456789abcdef55aa33cc607f objdump output example (before the fix): 10: 607f 33cc 55aa cdef .byte 0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 18: 89ab 4567 0123 3210 20: 7654 ba98 fedc Note that, after 0xcd (after first 64-bits of the target instruction), all ".byte" values are incorrectly printed as zero while hexdump prints correct instruction bits. To resolve this, this commit adds "packet" argument to support dumping instructions longer than 64-bits (to print correct instruction bits on ".byte"). This commit will be tested on the separate commit. Assembly: .insn 22, 0xfedcba98765432100123456789abcdef55aa33cc607f objdump output example (after the fix): 10: 607f 33cc 55aa cdef .byte 0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe 18: 89ab 4567 0123 3210 20: 7654 ba98 fedc opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_insn): Print unknown instruction using the new argument packet. (riscv_disassemble_data): Add unused argument packet. (print_insn_riscv): Pass packet to the disassemble function. --- opcodes/riscv-dis.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 3a31647a2f80..0e1f3b4610aa 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -641,7 +641,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info this is little-endian code. */ static int -riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) +riscv_disassemble_insn (bfd_vma memaddr, + insn_t word, + const bfd_byte *packet, + disassemble_info *info) { const struct riscv_opcode *op; static bool init = false; @@ -806,8 +809,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) ", "); (*info->fprintf_styled_func) (info->stream, dis_style_immediate, "0x%02x", - (unsigned int) (word & 0xff)); - word >>= 8; + (unsigned int) (*packet++)); } } break; @@ -983,6 +985,7 @@ riscv_data_length (bfd_vma memaddr, static int riscv_disassemble_data (bfd_vma memaddr ATTRIBUTE_UNUSED, insn_t data, + const bfd_byte *packet ATTRIBUTE_UNUSED, disassemble_info *info) { info->display_endian = info->endian; @@ -1037,7 +1040,8 @@ print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info) bfd_vma dump_size; int status; enum riscv_seg_mstate mstate; - int (*riscv_disassembler) (bfd_vma, insn_t, struct disassemble_info *); + int (*riscv_disassembler) (bfd_vma, insn_t, const bfd_byte *, + struct disassemble_info *); if (info->disassembler_options != NULL) { @@ -1081,7 +1085,7 @@ print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info) } insn = (insn_t) bfd_get_bits (packet, dump_size * 8, false); - return (*riscv_disassembler) (memaddr, insn, info); + return (*riscv_disassembler) (memaddr, insn, packet, info); } disassembler_ftype From patchwork Fri Nov 25 11:42:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 25951 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp3950268wrr; Fri, 25 Nov 2022 03:45:17 -0800 (PST) X-Google-Smtp-Source: AA0mqf5yYbb1t6cGqBbo1/LGvqw04CMm4sq62ZTK9GplC1lPGtkN2OjKqnAbo+YZv6vMHWj1GgJR X-Received: by 2002:a17:906:1b52:b0:7ad:90dc:b7d4 with SMTP id p18-20020a1709061b5200b007ad90dcb7d4mr17970801ejg.278.1669376716950; Fri, 25 Nov 2022 03:45:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669376716; cv=none; d=google.com; s=arc-20160816; b=NVik53GIPTpgm0iMUxJTjEMVdxmAOKTlhAoc/31Z8vmatDWpOEkHbRur/tpme4C5A+ P3DHAirmtDBRT8HSoo2YDc6Cnwl0U+CuWfoiGAGgJI5WJZPrzXcsni4P4gzAeP9Y6ja6 TAchyoHa1h2Vi+5LfuMqXUWbcng4PUJJN7rXmGVdxskhv9PEOsAMxM7hWzcq7mir179A eSKMmTEVZVPx+9I1PFOVVGqxAKnSJeav2ziRdB6vmRxFhe1N9n83hh9nipkttS46/TK4 oDmYc3aS9sV6VNg0DsWzl70jLnGDHH5dFRWCKrZ7Bcbanejvu4twHjoWTHw2TbhRy4Ef rT/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=i8tYmFfAQITDugBgAIfslqpoTGqJFweoMTVPWJ0n+8Q=; b=bRyqgYYJHuF0yeiJ7sk1Tkhy/2AgupN6lyGwhlDIw4h6wTOuSRh7jKTzacWlU/2JZs XaB9TeNTnBIEWLo8tpBPBrlokH5LOtAB4Tooe7YDxCqkKDX60rXfkJl9ViObs4zho/0O X7uykuhRAmaDdaT95eAtFRC8HWzla1rut7M4RpRq/kGq3dhOXKs4SDOaylO7U8JhHp5x sDgoT/Te4w2ZhuhvUu7iEbJMcbuJm6alaVh7axLd+MW9XuoP4lhIbY0D3xjFnaocjeVY asn8u9GFrm1eoEEfpQmD0Zmw6P1bqLtKygo0roSG8/6eVgSI08paQrFukekIDMlCowYm nfTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=wE6tgwKM; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id m21-20020a056402431500b0046aa986a23bsi2200890edc.186.2022.11.25.03.45.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 03:45:16 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=wE6tgwKM; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 64F02384EF49 for ; Fri, 25 Nov 2022 11:44:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 64F02384EF49 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1669376648; bh=i8tYmFfAQITDugBgAIfslqpoTGqJFweoMTVPWJ0n+8Q=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=wE6tgwKMVcWFO9ae0RW6bbFkt97UBMXoI3zmC96brqPTuvFEBr6eUksbMeIzLSShx nLi8IXMGUnQX91BI5jqSwsZVITav/gozqBnQDWUk+7bJEW64j5SM91VIRHzK1u6c4H PW3ZUD7u4HpcoSrMxknjuoRhbPKM+i8ocddViCKs= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 852F03840080 for ; Fri, 25 Nov 2022 11:42:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 852F03840080 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id D8982300089; Fri, 25 Nov 2022 11:42:46 +0000 (UTC) To: Tsukasa OI , Jan Beulich , Nelson Chu Cc: binutils@sourceware.org Subject: [PATCH v4 2/3] RISC-V: Better support for long instructions (assembler) Date: Fri, 25 Nov 2022 11:42:21 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750432684211848273?= X-GMAIL-MSGID: =?utf-8?q?1750468360677887607?= From: Tsukasa OI Commit bb996692bd96 ("RISC-V/gas: allow generating up to 176-bit instructions with .insn") tried to start supporting long instructions but it was insufficient. 1. It heavily depended on the bignum internals (radix of 2^16), 2. It generates "value conflicts with instruction length" even if a big number instruction encoding does not exceed its expected length and 3. Because long opcode was handled separately (from struct riscv_cl_insn), some information like DWARF line number correspondence was missing. To resolve these problems, this commit: 1. Handles bignum (and its encodings) precisely and 2. Incorporates long opcode handling into regular instruction handling. This commit will be tested on the separate commit. gas/ChangeLog: * config/tc-riscv.c (struct riscv_cl_insn): Add long opcode field. (create_insn) Clear long opcode marker. (install_insn) Install longer opcode as well. (s_riscv_insn) Likewise. (riscv_ip_hardcode): Make big number handling stricter. Length and the value conflicts only if the bignum size exceeds the expected maximum length. --- gas/config/tc-riscv.c | 41 ++++++++++++++++++++++++++++++++--------- 1 file changed, 32 insertions(+), 9 deletions(-) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 96d71dd1db60..0682eb355241 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -42,9 +42,13 @@ struct riscv_cl_insn /* The opcode's entry in riscv_opcodes. */ const struct riscv_opcode *insn_mo; - /* The encoded instruction bits. */ + /* The encoded instruction bits + (first bits enough to extract instruction length on a long opcode). */ insn_t insn_opcode; + /* The long encoded instruction bits ([0] is non-zero on a long opcode). */ + char insn_long_opcode[RISCV_MAX_INSN_LEN]; + /* The frag that contains the instruction. */ struct frag *frag; @@ -720,6 +724,7 @@ create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo) { insn->insn_mo = mo; insn->insn_opcode = mo->match; + insn->insn_long_opcode[0] = 0; insn->frag = NULL; insn->where = 0; insn->fixp = NULL; @@ -731,7 +736,10 @@ static void install_insn (const struct riscv_cl_insn *insn) { char *f = insn->frag->fr_literal + insn->where; - number_to_chars_littleendian (f, insn->insn_opcode, insn_length (insn)); + if (insn->insn_long_opcode[0] != 0) + memcpy (f, insn->insn_long_opcode, insn_length (insn)); + else + number_to_chars_littleendian (f, insn->insn_opcode, insn_length (insn)); } /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly @@ -3503,7 +3511,9 @@ riscv_ip_hardcode (char *str, values[num++] = (insn_t) imm_expr->X_add_number; break; case O_big: - values[num++] = generic_bignum[0]; + /* Extract lower 32-bits of a big number. + Assume that generic_bignum_to_int32 work on such number. */ + values[num++] = (insn_t) generic_bignum_to_int32 (); break; default: /* The first value isn't constant, so it should be @@ -3530,12 +3540,25 @@ riscv_ip_hardcode (char *str, if (imm_expr->X_op == O_big) { - if (bytes != imm_expr->X_add_number * CHARS_PER_LITTLENUM) + unsigned int llen = 0; + for (LITTLENUM_TYPE lval = generic_bignum[imm_expr->X_add_number - 1]; + lval != 0; llen++) + lval >>= BITS_PER_CHAR; + unsigned int repr_bytes + = (imm_expr->X_add_number - 1) * CHARS_PER_LITTLENUM + llen; + if (bytes < repr_bytes) return _("value conflicts with instruction length"); - char *f = frag_more (bytes); - for (num = 0; num < imm_expr->X_add_number; ++num) - number_to_chars_littleendian (f + num * CHARS_PER_LITTLENUM, - generic_bignum[num], CHARS_PER_LITTLENUM); + for (num = 0; num < imm_expr->X_add_number - 1; ++num) + number_to_chars_littleendian ( + ip->insn_long_opcode + num * CHARS_PER_LITTLENUM, + generic_bignum[num], + CHARS_PER_LITTLENUM); + if (llen != 0) + number_to_chars_littleendian ( + ip->insn_long_opcode + num * CHARS_PER_LITTLENUM, + generic_bignum[num], + llen); + memset(ip->insn_long_opcode + repr_bytes, 0, bytes - repr_bytes); return NULL; } @@ -4612,7 +4635,7 @@ s_riscv_insn (int x ATTRIBUTE_UNUSED) else as_bad ("%s `%s'", error.msg, error.statement); } - else if (imm_expr.X_op != O_big) + else { gas_assert (insn.insn_mo->pinfo != INSN_MACRO); append_insn (&insn, &imm_expr, imm_reloc); From patchwork Fri Nov 25 11:42:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 25949 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp3949393wrr; Fri, 25 Nov 2022 03:43:35 -0800 (PST) X-Google-Smtp-Source: AA0mqf6eSUVeloMP0UdiXKtQ6mDyZTxNG0wWgvL1OUUcXI9FVD/dlbdXQlEpS96VpImuYMDe7xT7 X-Received: by 2002:aa7:dd4d:0:b0:45c:98a9:7bbf with SMTP id o13-20020aa7dd4d000000b0045c98a97bbfmr18473037edw.372.1669376614939; Fri, 25 Nov 2022 03:43:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669376614; cv=none; d=google.com; s=arc-20160816; b=S5K+CmH9FR1iXqXEkBC736d7zqNgVnMIe/4Vv3AZS4T0tSIw5f5P+JmoaPvOenHwyb GqzvAOwryllYS7M9K7pv7edFpCUC2O6LRs18DDSPSYsSsMxIex+QPi3fjKRyOdEcrgCo wfRapsWYpoL5s8zm8znKJu3w4kqfVMMAvZ1Ol6YHamn78zmnN+1N8lU8E1Rv2CTaEo5X pUJdW68XoFeoisbz7akqLyFR9Zccg1AnLrINUgQaVgpcgUyzL/kcm7w6mgxJlkyunCQg zk4Js9lhTJzGG5j3sGytDuGmPCWlA5ALsk72sSlPSqbfaxUDWjvL7cDDmHRQiwBBBHPd Nm5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=ZUltnga3cS48i2rJN5AGb35hY4tvqkJg4RshDN53PJs=; b=W/bhIGAHqFtt1ZR76r3bW2ESSS/NBG0HrbZxghf0ZQ0fnXNfgwatOQJKecoZbgqw/A LMM3e0723ClkMGKeCM5H0b6s1ysccrxEfwMy66XslAQGz1w2XogQTBg3rP7yUs5miNU7 G1d8IEjIpHDBTHnytoEACgWv5F+sQdvuBM25l5pNf6gqdRilVkZoVngz+AOdXVOVzjRb OlwFqUKaq0Yib2GTR8g5X9borxmrQXOg5Z0Y2IskyWPrOL+uiLKXtn3Zupk+PlLxrP2W m88mmc+FId37c+XVylJ+t9ZakM8dsXg7fcaOPkoy0rOTINmxZJwyV+GwHYsuxLDazu3U smcg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=O1jci7K8; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (server2.sourceware.org. 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Tsukasa OI , Jan Beulich , Nelson Chu Cc: binutils@sourceware.org Subject: [PATCH v4 3/3] RISC-V: Better support for long instructions (tests) Date: Fri, 25 Nov 2022 11:42:22 +0000 Message-Id: <523d1243d28a817c7ab371daed61335ab1dd31bc.1669376539.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_LOTSOFHASH, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750468253538482553?= X-GMAIL-MSGID: =?utf-8?q?1750468253538482553?= From: Tsukasa OI This commit tests both (assembler and disassembler) fixes of "Better support for long instructions". gas/ChangeLog: * testsuite/gas/riscv/insn.s: Add testcases such that big number handling is required and should be disassembled as long ".byte" sequence with correct instruction bits. * testsuite/gas/riscv/insn.d: Likewise. * testsuite/gas/riscv/insn-na.d: Likewise. * testsuite/gas/riscv/insn-dwarf.d: Likewise. --- gas/testsuite/gas/riscv/insn-dwarf.d | 10 +++++++++- gas/testsuite/gas/riscv/insn-na.d | 8 ++++++++ gas/testsuite/gas/riscv/insn.d | 22 ++++++++++++++++++++++ gas/testsuite/gas/riscv/insn.s | 9 +++++++++ 4 files changed, 48 insertions(+), 1 deletion(-) diff --git a/gas/testsuite/gas/riscv/insn-dwarf.d b/gas/testsuite/gas/riscv/insn-dwarf.d index 89dc8d58ff09..b8bd42dff18c 100644 --- a/gas/testsuite/gas/riscv/insn-dwarf.d +++ b/gas/testsuite/gas/riscv/insn-dwarf.d @@ -74,5 +74,13 @@ insn.s +69 +0xf6.* insn.s +70 +0xfe.* insn.s +71 +0x108.* insn.s +72 +0x114.* -insn.s +- +0x12a +insn.s +74 +0x12a.* +insn.s +75 +0x134.* +insn.s +76 +0x13e.* +insn.s +77 +0x154.* +insn.s +78 +0x16a.* +insn.s +79 +0x180.* +insn.s +80 +0x196.* +insn.s +81 +0x1ac.* +insn.s +- +0x1c2 #pass diff --git a/gas/testsuite/gas/riscv/insn-na.d b/gas/testsuite/gas/riscv/insn-na.d index 66dce71ebc21..6928ba9ba0f2 100644 --- a/gas/testsuite/gas/riscv/insn-na.d +++ b/gas/testsuite/gas/riscv/insn-na.d @@ -73,3 +73,11 @@ Disassembly of section .text: [^:]+:[ ]+007f 0000 0000 0000 0000[ ]+[._a-z].* [^:]+:[ ]+0000107f 00000000 00000000[ ]+[._a-z].* [^:]+:[ ]+607f 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000[ ]+[._a-z].* +[^:]+:[ ]+007f 0000 0000 0000 8000[ ]+\.byte[ ]+0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80 +[^:]+:[ ]+007f 0000 0000 0000 8000[ ]+\.byte[ ]+0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80 +[^:]+:[ ]+607f 89ab 4567 0123 3210 7654 ba98 fedc 0000 0000 0000[ ]+\.byte[ ]+0x7f, 0x60, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +[^:]+:[ ]+607f 89ab 4567 0123 3210 7654 ba98 fedc 0000 0000 0000[ ]+\.byte[ ]+0x7f, 0x60, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +[^:]+:[ ]+607f 33cc 55aa cdef 89ab 4567 0123 3210 7654 ba98 00dc[ ]+\.byte[ ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0x00 +[^:]+:[ ]+607f 33cc 55aa cdef 89ab 4567 0123 3210 7654 ba98 00dc[ ]+\.byte[ ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0x00 +[^:]+:[ ]+607f 33cc 55aa cdef 89ab 4567 0123 3210 7654 ba98 fedc[ ]+\.byte[ ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe +[^:]+:[ ]+607f 33cc 55aa cdef 89ab 4567 0123 3210 7654 ba98 fedc[ ]+\.byte[ ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe diff --git a/gas/testsuite/gas/riscv/insn.d b/gas/testsuite/gas/riscv/insn.d index 2e5d35b39702..b25bc35553fd 100644 --- a/gas/testsuite/gas/riscv/insn.d +++ b/gas/testsuite/gas/riscv/insn.d @@ -92,3 +92,25 @@ Disassembly of section .text: [^:]+:[ ]+607f 0000 0000 0000[ ]+[._a-z].* [^:]+:[ ]+0000 0000 0000 0000 ? [^:]+:[ ]+0000 0000 0000 ? +[^:]+:[ ]+007f 0000 0000 0000[ ]+\.byte[ ]+0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80 +[^:]+:[ ]+8000 ? +[^:]+:[ ]+007f 0000 0000 0000[ ]+\.byte[ ]+0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80 +[^:]+:[ ]+8000 ? +[^:]+:[ ]+607f 89ab 4567 0123[ ]+\.byte[ ]+0x7f, 0x60, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +[^:]+:[ ]+3210 7654 ba98 fedc ? +[^:]+:[ ]+0000 0000 0000 ? +[^:]+:[ ]+607f 89ab 4567 0123[ ]+\.byte[ ]+0x7f, 0x60, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +[^:]+:[ ]+3210 7654 ba98 fedc ? +[^:]+:[ ]+0000 0000 0000 ? +[^:]+:[ ]+607f 33cc 55aa cdef[ ]+\.byte[ ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0x00 +[^:]+:[ ]+89ab 4567 0123 3210 ? +[^:]+:[ ]+7654 ba98 00dc ? +[^:]+:[ ]+607f 33cc 55aa cdef[ ]+\.byte[ ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0x00 +[^:]+:[ ]+89ab 4567 0123 3210 ? +[^:]+:[ ]+7654 ba98 00dc ? +[^:]+:[ ]+607f 33cc 55aa cdef[ ]+\.byte[ ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe +[^:]+:[ ]+89ab 4567 0123 3210 ? +[^:]+:[ ]+7654 ba98 fedc ? +[^:]+:[ ]+607f 33cc 55aa cdef[ ]+\.byte[ ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe +[^:]+:[ ]+89ab 4567 0123 3210 ? +[^:]+:[ ]+7654 ba98 fedc ? diff --git a/gas/testsuite/gas/riscv/insn.s b/gas/testsuite/gas/riscv/insn.s index 94f62fe5672e..48db59b14e88 100644 --- a/gas/testsuite/gas/riscv/insn.s +++ b/gas/testsuite/gas/riscv/insn.s @@ -70,3 +70,12 @@ target: .insn 10, 0x007f .insn 12, 0x107f .insn 22, 0x607f + + .insn 0x8000000000000000007f + .insn 10, 0x8000000000000000007f + .insn 0x000000000000fedcba98765432100123456789ab607f + .insn 22, 0x000000000000fedcba98765432100123456789ab607f + .insn 0x00dcba98765432100123456789abcdef55aa33cc607f + .insn 22, 0x00dcba98765432100123456789abcdef55aa33cc607f + .insn 0xfedcba98765432100123456789abcdef55aa33cc607f + .insn 22, 0xfedcba98765432100123456789abcdef55aa33cc607f