From patchwork Fri Nov 25 05:39:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 25824 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp3786007wrr; Thu, 24 Nov 2022 21:41:54 -0800 (PST) X-Google-Smtp-Source: AA0mqf5y3suduQqDI114szdz1GGMLnB4AGsESUL9+92JF4NoCMH/qJvQBLgQSTE67YQaDo4XIeWr X-Received: by 2002:a05:6402:916:b0:46a:c2d:127f with SMTP id g22-20020a056402091600b0046a0c2d127fmr12284560edz.220.1669354914246; Thu, 24 Nov 2022 21:41:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669354914; cv=none; d=google.com; s=arc-20160816; b=bGm3JrZ14iNagEKhfGLZjyyPLGNhdJkoHeeEVtEzm4J1lk++vo/l9cDh89gc9q4K7i OG4rwzpS38K6ahZAFEn47YuCSVwB/fMWK4eUDgz2jOe3nt8podF1VOl2uv5VfeRQh9Wt obpeo9TIVJ6q4Hf49oEDSvYY38kxQVQVfTsM+xWN8NJIbfewJXijxUqox5i6r4NZiT6R i8WnbtHDdADP/jr4FVcVgWrx7CH+lgzOZ8WKcDxIlVH21CEi7sQbSJnKQtGckYKPHq7u wrB8EA1VrWm1f16hhWAcVHECvXRk6jBOrj36w4+IBaiZtiMLBskMz8ofRoSpAXeg7Mol ZsFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=O/et5Xy+N58rsNGe7UFpUiwYZRDrhTtEP8e0BOyYDQQ=; b=H247FC+n8dIgki+xmy6SikQs9tQG1EkEnZu2R11R7iWOCrjM1TR2EdrgWF4vvbtOWv YusAK5IukZaoNRqJcNTP1nx21zQ2hdFVXfo/i/Lz1mz9prYZyOsqOHbLsWuUm7Do16QM 0PKjI3zZndrDo6IafPjjivkelSHzE5oP2+kVA+wPir47fgOO5Vv+wJrlbJ2M9/mnrC1d 79tNqlQ4P5rzgDnJ4TZ1maUxRBBKuPm970qKHn7tz2GHgHmU+i6ZED0OMJKRWyA6rKk2 agcAroZU9b562qeA/Q4ENdnZd0rrWhZqxwSzTrWC3okSmwcAIsKD9vyNho14r16jw7KW 0zjA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="eyCjb/tI"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id cw7-20020a170906478700b007ae86742c39si2694665ejc.504.2022.11.24.21.41.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Nov 2022 21:41:54 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="eyCjb/tI"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0D3B6393BA65 for ; Fri, 25 Nov 2022 05:41:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0D3B6393BA65 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1669354913; bh=O/et5Xy+N58rsNGe7UFpUiwYZRDrhTtEP8e0BOyYDQQ=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=eyCjb/tIbJOupcODvNHNvmyuq6CYXLT1QeoiUOthHIHnbHV/GGjJd+EtUrVJ5/+Gk Dal61xcNiYRSNvpSy9uB8zaVPvotLqjN0bYlV24t6LYm3vsLmzm5kD0juWOu62KJOo zlrVd4uEd7m5y/9Y8o4aULLHC4PS1YM4/HzyEYY8= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by sourceware.org (Postfix) with ESMTPS id 2F719393BA61 for ; Fri, 25 Nov 2022 05:41:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 2F719393BA61 X-IronPort-AV: E=McAfee;i="6500,9779,10541"; a="301986101" X-IronPort-AV: E=Sophos;i="5.96,192,1665471600"; d="scan'208";a="301986101" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Nov 2022 21:41:07 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10541"; a="817042502" X-IronPort-AV: E=Sophos;i="5.96,192,1665471600"; d="scan'208";a="817042502" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga005.jf.intel.com with ESMTP; 24 Nov 2022 21:41:05 -0800 Received: from shliclel4051.sh.intel.com (shliclel4051.sh.intel.com [10.239.240.51]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 927B01005680; Fri, 25 Nov 2022 13:41:04 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: jakub@redhat.com Subject: [PATCH V3] [x86] Fix incorrect _mm_cvtsbh_ss. Date: Fri, 25 Nov 2022 13:39:04 +0800 Message-Id: <20221125053904.1984263-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750338727896066629?= X-GMAIL-MSGID: =?utf-8?q?1750445498446492415?= Update in V3: Remove !flag_signaling_nans since there's already HONOR_NANS (BFmode). Here's the patch: After supporting real __bf16, the implementation of _mm_cvtsbh_ss went wrong. The patch add a builtin to generate pslld for the intrinsic, also extendbfsf2 is supported with pslld when !HONOR_NANS (BFmode). truncsfbf2 is supported with vcvtneps2bf16 when !HONOR_NANS (BFmode) && flag_unsafe_math_optimizations. gcc/ChangeLog: PR target/107748 * config/i386/avx512bf16intrin.h (_mm_cvtsbh_ss): Refined. * config/i386/i386-builtin-types.def (FLOAT_FTYPE_BFLOAT16): New function type. * config/i386/i386-builtin.def (BDESC): New builtin. * config/i386/i386-expand.cc (ix86_expand_args_builtin): Handle the builtin. * config/i386/i386.md (extendbfsf2): New expander. (extendbfsf2_1): New define_insn. (truncsfbf2): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/avx512bf16-cvtsbh2ss-1.c: Scan pslld. * gcc.target/i386/extendbfsf.c: New test. --- gcc/config/i386/avx512bf16intrin.h | 4 +- gcc/config/i386/i386-builtin-types.def | 1 + gcc/config/i386/i386-builtin.def | 2 + gcc/config/i386/i386-expand.cc | 1 + gcc/config/i386/i386.md | 40 ++++++++++++++++++- .../gcc.target/i386/avx512bf16-cvtsbh2ss-1.c | 3 +- gcc/testsuite/gcc.target/i386/extendbfsf.c | 16 ++++++++ 7 files changed, 61 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/extendbfsf.c diff --git a/gcc/config/i386/avx512bf16intrin.h b/gcc/config/i386/avx512bf16intrin.h index ea1d0125b3f..75378af5584 100644 --- a/gcc/config/i386/avx512bf16intrin.h +++ b/gcc/config/i386/avx512bf16intrin.h @@ -46,9 +46,7 @@ extern __inline float __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) _mm_cvtsbh_ss (__bf16 __A) { - union{ float a; unsigned int b;} __tmp; - __tmp.b = ((unsigned int)(__A)) << 16; - return __tmp.a; + return __builtin_ia32_cvtbf2sf (__A); } /* vcvtne2ps2bf16 */ diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i386-builtin-types.def index d10de32643f..65fe070e37f 100644 --- a/gcc/config/i386/i386-builtin-types.def +++ b/gcc/config/i386/i386-builtin-types.def @@ -1281,6 +1281,7 @@ DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, UHI) DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, UHI) # BF16 builtins +DEF_FUNCTION_TYPE (FLOAT, BFLOAT16) DEF_FUNCTION_TYPE (V32BF, V16SF, V16SF) DEF_FUNCTION_TYPE (V32BF, V16SF, V16SF, V32BF, USI) DEF_FUNCTION_TYPE (V32BF, V16SF, V16SF, USI) diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index 5e0461acc00..d85b1753039 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -2838,6 +2838,8 @@ BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_dpbf16ps_v8sf_maskz, "__ BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_dpbf16ps_v4sf, "__builtin_ia32_dpbf16ps_v4sf", IX86_BUILTIN_DPBF16PS_V4SF, UNKNOWN, (int) V4SF_FTYPE_V4SF_V8BF_V8BF) BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_dpbf16ps_v4sf_mask, "__builtin_ia32_dpbf16ps_v4sf_mask", IX86_BUILTIN_DPBF16PS_V4SF_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V8BF_V8BF_UQI) BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_dpbf16ps_v4sf_maskz, "__builtin_ia32_dpbf16ps_v4sf_maskz", IX86_BUILTIN_DPBF16PS_V4SF_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V8BF_V8BF_UQI) +BDESC (OPTION_MASK_ISA_SSE2, 0, CODE_FOR_extendbfsf2_1, "__builtin_ia32_cvtbf2sf", IX86_BUILTIN_CVTBF2SF, UNKNOWN, (int) FLOAT_FTYPE_BFLOAT16) + /* AVX512FP16. */ BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_addv8hf3_mask, "__builtin_ia32_addph128_mask", IX86_BUILTIN_ADDPH128_MASK, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF_UQI) diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index 0373c3614a4..d26e7e41445 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -10423,6 +10423,7 @@ ix86_expand_args_builtin (const struct builtin_description *d, return ix86_expand_sse_ptest (d, exp, target); case FLOAT128_FTYPE_FLOAT128: case FLOAT_FTYPE_FLOAT: + case FLOAT_FTYPE_BFLOAT16: case INT_FTYPE_INT: case UINT_FTYPE_UINT: case UINT16_FTYPE_UINT16: diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 01faa911b77..9451883396c 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -130,6 +130,7 @@ (define_c_enum "unspec" [ ;; For AVX/AVX512F support UNSPEC_SCALEF UNSPEC_PCMP + UNSPEC_CVTBFSF ;; Generic math support UNSPEC_IEEE_MIN ; not commutative @@ -4961,6 +4962,31 @@ (define_insn "*extendhf2" (set_attr "prefix" "evex") (set_attr "mode" "")]) +(define_expand "extendbfsf2" + [(set (match_operand:SF 0 "register_operand") + (unspec:SF + [(match_operand:BF 1 "register_operand")] + UNSPEC_CVTBFSF))] + "TARGET_SSE2 && !HONOR_NANS (BFmode)") + +;; Don't use float_extend since psrlld doesn't raise +;; exceptions and turn a sNaN into a qNaN. +(define_insn "extendbfsf2_1" + [(set (match_operand:SF 0 "register_operand" "=x,Yw") + (unspec:SF + [(match_operand:BF 1 "register_operand" " 0,Yw")] + UNSPEC_CVTBFSF))] + "TARGET_SSE2" + "@ + pslld\t{$16, %0|%0, 16} + vpslld\t{$16, %1, %0|%0, %1, 16}" + [(set_attr "isa" "noavx,avx") + (set_attr "type" "sseishft") + (set_attr "length_immediate" "1") + (set_attr "prefix_data16" "1,*") + (set_attr "prefix" "orig,vex") + (set_attr "mode" "TI") + (set_attr "memory" "none")]) (define_expand "extendxf2" [(set (match_operand:XF 0 "nonimmediate_operand") @@ -5177,7 +5203,19 @@ (define_insn "*trunchf2" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") (set_attr "mode" "HF")]) - + +(define_insn "truncsfbf2" + [(set (match_operand:BF 0 "register_operand" "=x, v") + (float_truncate:BF + (match_operand:SF 1 "register_operand" "x,v")))] + "((TARGET_AVX512BF16 && TARGET_AVX512VL) || TARGET_AVXNECONVERT) + && !HONOR_NANS (BFmode) && flag_unsafe_math_optimizations" + "@ + %{vex%} vcvtneps2bf16\t{%1, %0|%0, %1} + vcvtneps2bf16\t{%1, %0|%0, %1}" + [(set_attr "isa" "avxneconvert,avx512bf16vl") + (set_attr "prefix" "vex,evex")]) + ;; Signed conversion to DImode. (define_expand "fix_truncxfdi2" diff --git a/gcc/testsuite/gcc.target/i386/avx512bf16-cvtsbh2ss-1.c b/gcc/testsuite/gcc.target/i386/avx512bf16-cvtsbh2ss-1.c index 8e929e6f159..edf30b583b9 100644 --- a/gcc/testsuite/gcc.target/i386/avx512bf16-cvtsbh2ss-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512bf16-cvtsbh2ss-1.c @@ -1,8 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-mavx512bf16 -O2" } */ /* { dg-additional-options "-fno-PIE -mfpmath=sse" { target ia32 } } */ -/* { dg-final { scan-assembler-times "sall\[ \\t\]+\[^\{\n\]*16" 1 } } */ -/* { dg-final { scan-assembler-times "movl" 1 } } */ +/* { dg-final { scan-assembler-times "pslld" 1 } } */ #include diff --git a/gcc/testsuite/gcc.target/i386/extendbfsf.c b/gcc/testsuite/gcc.target/i386/extendbfsf.c new file mode 100644 index 00000000000..a38fa68bdc9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/extendbfsf.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512bf16 -mavx512vl -O2 -ffast-math" } */ +/* { dg-final { scan-assembler-times "pslld" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtneps2bf16" 1 } } */ + +float +extendsfbf (__bf16 a) +{ + return a; +} + +__bf16 +truncsfbf (float a) +{ + return a; +}