From patchwork Thu Nov 24 19:13:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Patchwork-Id: 25694 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp3570871wrr; Thu, 24 Nov 2022 11:16:35 -0800 (PST) X-Google-Smtp-Source: AA0mqf4OTsjPxvGXDDpHe7yN5klpvPVVPdxOX8H7L0Y0L0e7iZooM8lqlcy3KXHeorQzjGKkZgo5 X-Received: by 2002:a63:5d0d:0:b0:43c:6413:322c with SMTP id r13-20020a635d0d000000b0043c6413322cmr18165452pgb.472.1669317394738; Thu, 24 Nov 2022 11:16:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669317394; cv=none; d=google.com; s=arc-20160816; b=RKPA4d3uwsU4bhYztd8ZM2NxDEdVoeGgv+bLC00+JtPlJJ8ndMPUKUd6ajQtUzw2z4 S2J6dLm5dwvbHd2KiZC8rVo9OrYpQGlbSBFYX6H0jN/zlOmJLrtwWgjPLXdOK4eWfpRm VsSpPxIDDZYxw4ZZWlDQongLBMV6rnPOJbd2vq0ZMCvbPhLr/pLgAm5ZCmPyPcdIkBOh f63UnI4+IFLAmJbSYJFbria4LzN6JtehNOFfygb/F7EMHwARCKQK+vtUyEf8O0Kkphn2 pD96hypbP8OatepqkrK9Y2Vn9EzWAxS7uzpZ1A/MJID2SxpyZdIpmW8GaNXLHAkbM4Bk ++XQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:ui-outboundreport:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=/TgZq33J74/MTqFVMdBUu92oMaQp1+1oT4xNLOVhzh4=; b=k/Qclv9SqRnC2H5V65C7AIiiRRBLF9p6Z+2ack2LZjU88hdoGEWG5VckL5RaQfgumm BIkCJifPSttbsWcJQKGeUVKI5HFObZlT15QblIP7jYYv1alAMAu+yxudjBcjTWew2bYG 8zcOKpeMOxaY6g96HtUgHs/WVcrtY+0M/XPHYlESkWe0S2xbjOuWJ3frIov/EP3FV1+F FQHSj4TW+LwRNY0nKMpBNKSFT+pzrNRCnHc8j4xJAVv3ZUPPudXC6vLadoY/+gzaumsF Gy6+wLBni01WdoqgP76EWtey8XYwpK0vh4GIzhML8YVO0eLAyXj8/eBbQuIt1L0omJiV 4cLg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmx.net header.s=s31663417 header.b=XKdzizcM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmx.net Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id q10-20020a170902daca00b00188d116d214si1644405plx.294.2022.11.24.11.16.22; Thu, 24 Nov 2022 11:16:34 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmx.net header.s=s31663417 header.b=XKdzizcM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmx.net Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229624AbiKXTOV (ORCPT + 99 others); Thu, 24 Nov 2022 14:14:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56292 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229379AbiKXTOO (ORCPT ); Thu, 24 Nov 2022 14:14:14 -0500 Received: from mout.gmx.net (mout.gmx.net [212.227.17.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A74A587574; Thu, 24 Nov 2022 11:14:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=s31663417; t=1669317247; bh=A7+kRg9M9OJjUrVN+1XPzm8xYzLJxjTtaBFDySHGKIg=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=XKdzizcMj/O2kXKtKqgBCj872UihpKCmQ4RLJEuNI2lgqxHqzLUWfqVWBm6rbQ1kE TTe/ZMfYpvtUFrM0Etw8YEILZVRwAoDZxUd5yYABEqBvuby/pGqMNfLVPOGxyRTH4g paqtOdVX4x8fGwqoPcK+Qey9jZ7jZw7JqlzT46MFfh+X2ZW9sjAx/hIlT0oE689zsT uF7skhibkQL+LwLd0jFSbMhd0KZ1LY7MNODrI85uDlXLuK1zfea8cy436idIc3FGRH shLIMnMzpySWta4QPZzK8NEg8P+PAhIvMGzD9fxUuB/PZZiJNuertwJA9/yRzJ1sD6 QZk4tfrPYhl7Q== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from probook ([95.223.44.31]) by mail.gmx.net (mrgmx104 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MDQeU-1ons4H1EKU-00AS86; Thu, 24 Nov 2022 20:14:07 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-spi@vger.kernel.org, openbmc@lists.ozlabs.org Cc: Rob Herring , Krzysztof Kozlowski , =?utf-8?q?Jonathan?= =?utf-8?q?_Neusch=C3=A4fer?= , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown Subject: [PATCH v2 1/3] dt-bindings: spi: Add Nuvoton WPCM450 Flash Interface Unit (FIU) Date: Thu, 24 Nov 2022 20:13:58 +0100 Message-Id: <20221124191400.287918-2-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221124191400.287918-1-j.neuschaefer@gmx.net> References: <20221124191400.287918-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:ckIn9pSJN3WyPdbYcKFI7A6cVRRUearrUf0sPopHpbcINteKWjG omFY4zDNUITjwoTj7QLzl95Muz3yWfdgiVwPaxBQLPrcwNTMB/EDv2FriLlhZ6sSucYsWg0 xLL+lzvpBuyjmZf4rwvRdU0MZZ7R2lHheIAz+rpcu6h5PuVUTkLeFt1BHwvyNJ/cF2zgImy +d5VlAe5ykNxCzM03aR6w== UI-OutboundReport: notjunk:1;M01:P0:AU9B7Gf2Lr8=;Smh9J9Ev/mBdm6dZKHdLh0SLauO MBeaG822gFbmtFbpq6XAL2QpnAflSWXTeuWeNAGPF+Zo5LEEFye2aJDKYKIyuIQg/Ajw9Uqao vvDt3tSQ53JFWtjZcjeIDZj3gkG+d2bSa2JC5bmATR5PuhGgYHM1nye+TMrpctSwtitI0o1tA maUAJbSxPjTdzo/yXFYKufnWt89tqrMyc9vOMrvEv8QmfP1eBfg886p1MA0JMP5m0vHrf3On/ +glG/HCUZljG9qq4Sn0YbZ97K7UMuUdLdFC1F7uKVXuzVElZ5WVCJEKJ5/jX05b9tB1zLJNKC EFFaZes8pXFPgqy70Dm7W16QkGiqibXcib+R00DtRFPZeUJ3h6/hgdqeWBQFS6Tr/EYUIksJn BZ6hVBuu13MevbylCSYt9mWpNLAwzTb5mZEhn67kG3vFaLspWuTR0dTLf0hj+YH0b8ssFdWzA uz+riMudVfR9s565eLtdJoaCqGGR/K0Km2rr4Z2ceUFrG0Mrhj902Rlltym2fJwbixA3WNu3J mlrjzeEu6ph4QmBS66wZip7hwUVjgmWAasps6Anfx9blyPD6GjzNWAbytoSknIqsDXqkMiDht xVmGXHqJoTCjBTyZ7I16EorO3LeeBBcQhPPOyJPGs8HWejhEiTSB9QgtWcQ+0KblrcmXF60T6 XUi58vHff/aYKY350zt69PwYtXqS/E/b5p5lxu1bejsDFgZDddX9P4esmRnqPhs6GXkoA32V1 2eosHzxl4BjSlb9GCpJjhLoCZai+95z+TxqnBkoQAO94nFpUnk7dEyOWNwnNkbOnN+ecAZMQb watOz/2FiMeWDkTNniSzPYKXCwynN+NjoFyUDOnNQAKFw+FhX6zhTQblHR416Q969XYPHPLX5 teWgLpfSNNUHK3nT/Oeq3DI9fyR7+NYjzTLBgCofl9qg7kiBA60nyVaygVwAtumCI3s+95zZH uzn2Urqd25ag1E//yVZB0oJs38E= X-Spam-Status: No, score=0.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2,RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750406156234238918?= X-GMAIL-MSGID: =?utf-8?q?1750406156234238918?= The Flash Interface Unit (FIU) is the SPI flash controller in the Nuvoton WPCM450 BMC SoC. It supports four chip selects, and direct (memory-mapped) access to 16 MiB per chip. Larger flash chips can be accessed by software-defined SPI transfers. The FIU in newer NPCM7xx SoCs is not compatible with the WPCM450 FIU. Signed-off-by: Jonathan Neuschäfer Reviewed-by: Krzysztof Kozlowski --- v2: - A few cleanups suggested by Krzysztof Kozlowski - Simplify binding by making second reg item mandatory v1: - https://lore.kernel.org/lkml/20221105185911.1547847-4-j.neuschaefer@gmx.net/ --- .../bindings/spi/nuvoton,wpcm450-fiu.yaml | 66 +++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml -- 2.35.1 diff --git a/Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml b/Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml new file mode 100644 index 0000000000000..ef94803e75d90 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/nuvoton,wpcm450-fiu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton WPCM450 Flash Interface Unit (FIU) + +maintainers: + - Jonathan Neuschäfer + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + const: nuvoton,wpcm450-fiu + + reg: + items: + - description: FIU registers + - description: Memory-mapped flash contents + + reg-names: + items: + - const: control + - const: memory + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + nuvoton,shm: + $ref: /schemas/types.yaml#/definitions/phandle + description: a phandle to the SHM block (see ../arm/nuvoton,shm.yaml) + +required: + - compatible + - reg + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + spi@c8000000 { + compatible = "nuvoton,wpcm450-fiu"; + reg = <0xc8000000 0x1000>, <0xc0000000 0x4000000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "control", "memory"; + clocks = <&clk WPCM450_CLK_FIU>; + nuvoton,shm = <&shm>; + + flash@0 { + compatible = "jedec,spi-nor"; + }; + }; + + shm: syscon@c8001000 { + compatible = "nuvoton,wpcm450-shm", "syscon"; + reg = <0xc8001000 0x1000>; + }; From patchwork Thu Nov 24 19:13:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Patchwork-Id: 25693 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp3570250wrr; Thu, 24 Nov 2022 11:15:18 -0800 (PST) X-Google-Smtp-Source: AA0mqf6e9SkkU4h7wQt8oC2m+ICXiBlE/m1uekdZEhCFru/EkSsSOsv+s8ql2jIXrUNeeOUxLAA7 X-Received: by 2002:a17:90a:b298:b0:212:f923:2f90 with SMTP id c24-20020a17090ab29800b00212f9232f90mr36032710pjr.93.1669317318215; Thu, 24 Nov 2022 11:15:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669317318; cv=none; d=google.com; s=arc-20160816; b=Puyq13bhsQ0oNVrsKuFOC9odlMW2Uqib1J2MF5G3qV1Fj77DUVgOL/tPO/uRORVfDm zCHSAXkUTv1OPpolbc9Uu7aJpEO5umz89HFxo80u1PlfxdxRtkEdzV1EmRkVGdtqTzJ6 7CfdPlLB7SHCGAZxsiNwwr/nefyjy8P9VJUZ51TQfLJ+87avs9iTTOi8OvCxTECNke6D ChZN7Z+8f5/eIL9h2YndaNC4AdUYHYNbSfWWO2Du/7AiBy9A7tvHl9t03ovfbxcuYY8G oEnye7fvNSHQvEV2SKiRvHGC8SqrMQ62V/Deo1Cik+D4EJzCG5xbC2u94jWp6IV76TD3 gXhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:ui-outboundreport:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=N6bG0prdMDR77mUJZ7/ylfDq6ihAQ1lyY5+PHP7S1L8=; b=TBKzYUzL/XyJ+jcnhvcPNF52Ul/egUaItelKcsKweY1ShWpUBdstTO8ub8uNQmcZfA VUYDRLDvpxBdVrHgaQwuxAklwyTBr8Z2e4nGxHkX/0/iLe0ZLtXnVM23w+z3u5UcmmfJ qrdFgX7s95OIzKltM7FPBrmXixWjETAFh3y/EwBoDKJGEmfvEU/hpFFRhc0KoAb0EvOP qRqqbMhSN3F9O2qbqTfsm9d6TDr1OanmPajxCD2QHgMiI0J52TfosTxI1TWxNdGbxxmE Vb/Xlkljhv5ACRYZD5DlzyW+p8pi+y4Zf/0IFp5T5Ec3qch8ZgF0Upz6O2hGiOniFLIn TCSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmx.net header.s=s31663417 header.b=hR34tRgh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmx.net Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id k21-20020a056a00135500b00572f208f7basi1655392pfu.149.2022.11.24.11.15.05; Thu, 24 Nov 2022 11:15:18 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmx.net header.s=s31663417 header.b=hR34tRgh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmx.net Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229612AbiKXTOb (ORCPT + 99 others); Thu, 24 Nov 2022 14:14:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56314 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229576AbiKXTOS (ORCPT ); Thu, 24 Nov 2022 14:14:18 -0500 Received: from mout.gmx.net (mout.gmx.net [212.227.17.22]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB53981581; Thu, 24 Nov 2022 11:14:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=s31663417; t=1669317248; bh=CYsr5tJ0QaVRBVO/yN1jBjt0uLLMgUBwFTddqBg5weI=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=hR34tRghKMlqyaB9dyiRcEadzTTQbM+s7CLZ6OBJePC5Q0I4cSXQ8y5Q/BqpVShk2 Nve4X5t8x1qDIL0TTiN2mPNSdedeiqVl9ko2Q/CnmgTVPxnHAZcgK4R0c4ZA9U2Xf/ bbo2TftgIXAuiNx9gIdo/32nX8VlGoh+vYXHye3q4hQhWF7aWOTHuidVf+WU9T2ctA U8vrwmGlYyfEbyPBjCZwQ8gPF07YrqTmQSDRN0pii1RR9SOPFoxcJvyYbNXC2qfkhK 9B60KSz92Jn3rPaGMy3aoTe4YIxTOt1fVq/Zc3Wov6yl/TvQOrbcCFJSPfkFAlGXgx eQT6RBdOpJVPw== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from probook ([95.223.44.31]) by mail.gmx.net (mrgmx104 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MhlGq-1pSxf62saG-00dn0R; Thu, 24 Nov 2022 20:14:08 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-spi@vger.kernel.org, openbmc@lists.ozlabs.org Cc: Rob Herring , Krzysztof Kozlowski , =?utf-8?q?Jonathan?= =?utf-8?q?_Neusch=C3=A4fer?= , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown Subject: [PATCH v2 2/3] spi: wpcm-fiu: Add driver for Nuvoton WPCM450 Flash Interface Unit (FIU) Date: Thu, 24 Nov 2022 20:13:59 +0100 Message-Id: <20221124191400.287918-3-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221124191400.287918-1-j.neuschaefer@gmx.net> References: <20221124191400.287918-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:2+9Lz7pKn8yHl4IGh9pmL4EHb+uRdGDokz4ZRJ6fKyxgx3blswA HC5fQed9RiiLWxwxPk34ui7Bfr/7EhIev/kEfSHKb3OiUxldmjBCjk5endjecORBJmpIHb0 eEsPT6BJFRjSiyRe534CDTBS47hjsva9ThUTcNs5hbYMMRbrQgwM2wTXLLJbtiZA0A1C4p5 QdslNIZsboOm81HmVlMOg== UI-OutboundReport: notjunk:1;M01:P0:0pi1/xX06GI=;TBVvnzwGj27zAzHdP9x71mumlel gKvi/rPNsTnthIElR2p1t5SbtLUCiJwSvZVjjt0O/8FTnpV5M1V4YkVIXKhsFS6KJmIPqPQdN 8yT2mTP2VqPJc33EfVGpiJR401HgeM6McGGQLnj89Zfrv2bGhctwTube0Li4z7oIE17bHSLvo 38JaYwcSH5OkPSlghiQvcU1ucNXx79GEyjFGQqDd7Gg2DIKrxKgv83+dsCm6ORfIqWF7pJ9QG AOVUtas4Gz9A9eNUM+A/maNkhe/WcJSizPV2/ljDupup9pKKCBeJyz/9qrlvzX+1FEDsTv6r/ PFaAvHKUegFv613ZmS/6vrEcEhX5PC0KFkIqH/Pgx2GUO1DYTqGuH9ttWz4EHx94e6TNbyD8D Xc1D7t7QPP2zBw9kW9W4c02J1ReTUSYcjD4FxVr6RBC3ZbvKcUzQYLO6xOUvk1d29UtBA9FE3 RggeL4ML8YoPdt6m7MNslJQsLBQhjwolPNrSTS0QyNiG1fSyRZq2HeH+2t4/HmkKAPPWitfh1 a462mJssC2//YAs6uMl4PRJIotsDS11cLqnqdSOP+e/4XwRJuUElvaufBanh7YdZT2gbUXvT2 Zh8U9DBe0a4vZ4h6s8QSvEQTG4kWmBrS8yVMcyaGc52g4Pb03sTtoaSqa8F6ilI0iHvve2q3y 18/DI3ySEcJaE1BnKaroCfhgmQcT7Wm5m9GKjq6GP5Rv9MWd+DWF2QbDBJV/aC03diELjIFxZ cNsT/kZm4Tdxj6cuOtIwBJbI5ne9OqWGuT9JMI49aIUfiCZVq00yF4TQyu+AidXAjd7WV9mef HHglbPqNf5yUwocf14Eckzk4PjDy396fQoAwdpVloQAyQh/XyELO+d7vmD7us5TIJrN5P8cjw 8EdzK4mZ6JoV+iivWmAtxTY/q9oimqXV8U/64rLGKTVqvXGoTk4D6BDXZmLl452wqNjvA0Er8 Docd7qDwegCIhiOgm9lCipNFU88= X-Spam-Status: No, score=0.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2,RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750406076524765898?= X-GMAIL-MSGID: =?utf-8?q?1750406076524765898?= The Flash Interface Unit (FIU) is the SPI flash controller in the Nuvoton WPCM450 BMC SoC. It supports four chip selects, and direct (memory-mapped) access to 16 MiB per chip. Larger flash chips can be accessed by software-defined SPI transfers. The FIU in newer NPCM7xx SoCs is not compatible with the WPCM450 FIU. Signed-off-by: Jonathan Neuschäfer --- v2: - Fix a few nits from the kernel test robot v1: - https://lore.kernel.org/lkml/20221105185911.1547847-8-j.neuschaefer@gmx.net/ --- drivers/spi/Kconfig | 11 + drivers/spi/Makefile | 1 + drivers/spi/spi-wpcm-fiu.c | 444 +++++++++++++++++++++++++++++++++++++ 3 files changed, 456 insertions(+) create mode 100644 drivers/spi/spi-wpcm-fiu.c -- 2.35.1 diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index d1bb62f7368b7..ee5f9e61cc280 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -635,6 +635,17 @@ config SPI_MTK_SNFI is implemented as a SPI-MEM controller with pipelined ECC capcability. +config SPI_WPCM_FIU + tristate "Nuvoton WPCM450 Flash Interface Unit" + depends on ARCH_NPCM || COMPILE_TEST + select REGMAP + help + This enables support got the Flash Interface Unit SPI controller + present in the Nuvoton WPCM450 SoC. + + This driver does not support generic SPI. The implementation only + supports the spi-mem interface. + config SPI_NPCM_FIU tristate "Nuvoton NPCM FLASH Interface Unit" depends on ARCH_NPCM || COMPILE_TEST diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 4b34e855c8412..e30196d0a4cf9 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -83,6 +83,7 @@ obj-$(CONFIG_SPI_MTK_NOR) += spi-mtk-nor.o obj-$(CONFIG_SPI_MTK_SNFI) += spi-mtk-snfi.o obj-$(CONFIG_SPI_MXIC) += spi-mxic.o obj-$(CONFIG_SPI_MXS) += spi-mxs.o +obj-$(CONFIG_SPI_WPCM_FIU) += spi-wpcm-fiu.o obj-$(CONFIG_SPI_NPCM_FIU) += spi-npcm-fiu.o obj-$(CONFIG_SPI_NPCM_PSPI) += spi-npcm-pspi.o obj-$(CONFIG_SPI_NXP_FLEXSPI) += spi-nxp-fspi.o diff --git a/drivers/spi/spi-wpcm-fiu.c b/drivers/spi/spi-wpcm-fiu.c new file mode 100644 index 0000000000000..e525fe074f883 --- /dev/null +++ b/drivers/spi/spi-wpcm-fiu.c @@ -0,0 +1,444 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2022 Jonathan Neuschäfer + +#include +#include +#include +#include +#include +#include +#include +#include + +#define FIU_CFG 0x00 +#define FIU_BURST_BFG 0x01 +#define FIU_RESP_CFG 0x02 +#define FIU_CFBB_PROT 0x03 +#define FIU_FWIN1_LOW 0x04 +#define FIU_FWIN1_HIGH 0x06 +#define FIU_FWIN2_LOW 0x08 +#define FIU_FWIN2_HIGH 0x0a +#define FIU_FWIN3_LOW 0x0c +#define FIU_FWIN3_HIGH 0x0e +#define FIU_PROT_LOCK 0x10 +#define FIU_PROT_CLEAR 0x11 +#define FIU_SPI_FL_CFG 0x14 +#define FIU_UMA_CODE 0x16 +#define FIU_UMA_AB0 0x17 +#define FIU_UMA_AB1 0x18 +#define FIU_UMA_AB2 0x19 +#define FIU_UMA_DB0 0x1a +#define FIU_UMA_DB1 0x1b +#define FIU_UMA_DB2 0x1c +#define FIU_UMA_DB3 0x1d +#define FIU_UMA_CTS 0x1e +#define FIU_UMA_ECTS 0x1f + +#define FIU_BURST_CFG_R16 3 + +#define FIU_UMA_CTS_D_SIZE(x) (x) +#define FIU_UMA_CTS_A_SIZE BIT(3) +#define FIU_UMA_CTS_WR BIT(4) +#define FIU_UMA_CTS_CS(x) ((x) << 5) +#define FIU_UMA_CTS_EXEC_DONE BIT(7) + +#define SHM_FLASH_SIZE 0x02 +#define SHM_FLASH_SIZE_STALL_HOST BIT(6) + +/* + * I observed a typical wait time of 16 iterations for a UMA transfer to + * finish, so this should be a safe limit. + */ +#define UMA_WAIT_ITERATIONS 100 + +struct wpcm_fiu_spi { + struct device *dev; + struct clk *clk; + void __iomem *regs; + struct regmap *shm_regmap; +}; + +static void wpcm_fiu_set_opcode(struct wpcm_fiu_spi *fiu, u8 opcode) +{ + writeb(opcode, fiu->regs + FIU_UMA_CODE); +} + +static void wpcm_fiu_set_addr(struct wpcm_fiu_spi *fiu, u32 addr) +{ + writeb((addr >> 0) & 0xff, fiu->regs + FIU_UMA_AB0); + writeb((addr >> 8) & 0xff, fiu->regs + FIU_UMA_AB1); + writeb((addr >> 16) & 0xff, fiu->regs + FIU_UMA_AB2); +} + +static void wpcm_fiu_set_data(struct wpcm_fiu_spi *fiu, const u8 *data, unsigned int nbytes) +{ + int i; + + for (i = 0; i < nbytes; i++) + writeb(data[i], fiu->regs + FIU_UMA_DB0 + i); +} + +static void wpcm_fiu_get_data(struct wpcm_fiu_spi *fiu, u8 *data, unsigned int nbytes) +{ + int i; + + for (i = 0; i < nbytes; i++) + data[i] = readb(fiu->regs + FIU_UMA_DB0 + i); +} + +/* + * Perform a UMA (User Mode Access) operation, i.e. a software-controlled SPI transfer. + */ +static int wpcm_fiu_do_uma(struct wpcm_fiu_spi *fiu, unsigned int cs, + bool use_addr, bool write, int data_bytes) +{ + int i = 0; + u8 cts = FIU_UMA_CTS_EXEC_DONE | FIU_UMA_CTS_CS(cs); + + if (use_addr) + cts |= FIU_UMA_CTS_A_SIZE; + if (write) + cts |= FIU_UMA_CTS_WR; + cts |= FIU_UMA_CTS_D_SIZE(data_bytes); + + writeb(cts, fiu->regs + FIU_UMA_CTS); + + for (i = 0; i < UMA_WAIT_ITERATIONS; i++) + if (!(readb(fiu->regs + FIU_UMA_CTS) & FIU_UMA_CTS_EXEC_DONE)) + return 0; + + dev_info(fiu->dev, "UMA transfer has not finished in %d iterations\n", UMA_WAIT_ITERATIONS); + return -EIO; +} + +static void wpcm_fiu_ects_assert(struct wpcm_fiu_spi *fiu, unsigned int cs) +{ + u8 ects = readb(fiu->regs + FIU_UMA_ECTS); + + ects &= ~BIT(cs); + writeb(ects, fiu->regs + FIU_UMA_ECTS); +} + +static void wpcm_fiu_ects_deassert(struct wpcm_fiu_spi *fiu, unsigned int cs) +{ + u8 ects = readb(fiu->regs + FIU_UMA_ECTS); + + ects |= BIT(cs); + writeb(ects, fiu->regs + FIU_UMA_ECTS); +} + +struct wpcm_fiu_op_shape { + bool (*match)(const struct spi_mem_op *op); + int (*exec)(struct spi_mem *mem, const struct spi_mem_op *op); +}; + +static bool wpcm_fiu_normal_match(const struct spi_mem_op *op) +{ + // Opcode 0x0b (FAST READ) is treated differently in hardware + if (op->cmd.opcode == 0x0b) + return false; + + return (op->addr.nbytes == 0 || op->addr.nbytes == 3) && + op->dummy.nbytes == 0 && op->data.nbytes <= 4; +} + +static int wpcm_fiu_normal_exec(struct spi_mem *mem, const struct spi_mem_op *op) +{ + struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller); + int ret; + + wpcm_fiu_set_opcode(fiu, op->cmd.opcode); + wpcm_fiu_set_addr(fiu, op->addr.val); + if (op->data.dir == SPI_MEM_DATA_OUT) + wpcm_fiu_set_data(fiu, op->data.buf.out, op->data.nbytes); + + ret = wpcm_fiu_do_uma(fiu, mem->spi->chip_select, op->addr.nbytes == 3, + op->data.dir == SPI_MEM_DATA_OUT, op->data.nbytes); + + if (op->data.dir == SPI_MEM_DATA_IN) + wpcm_fiu_get_data(fiu, op->data.buf.in, op->data.nbytes); + + return ret; +} + +static bool wpcm_fiu_fast_read_match(const struct spi_mem_op *op) +{ + return op->cmd.opcode == 0x0b && op->addr.nbytes == 3 && + op->dummy.nbytes == 1 && + op->data.nbytes >= 1 && op->data.nbytes <= 4 && + op->data.dir == SPI_MEM_DATA_IN; +} + +static int wpcm_fiu_fast_read_exec(struct spi_mem *mem, const struct spi_mem_op *op) +{ + return -EINVAL; +} + +/* + * 4-byte addressing. + * + * Flash view: [ C A A A A D D D D] + * bytes: 13 aa bb cc dd -> 5a a5 f0 0f + * FIU's view: [ C A A A][ C D D D D] + * FIU mode: [ read/write][ read ] + */ +static bool wpcm_fiu_4ba_match(const struct spi_mem_op *op) +{ + return op->addr.nbytes == 4 && op->dummy.nbytes == 0 && op->data.nbytes <= 4; +} + +static int wpcm_fiu_4ba_exec(struct spi_mem *mem, const struct spi_mem_op *op) +{ + struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller); + int cs = mem->spi->chip_select; + + wpcm_fiu_ects_assert(fiu, cs); + + wpcm_fiu_set_opcode(fiu, op->cmd.opcode); + wpcm_fiu_set_addr(fiu, op->addr.val >> 8); + wpcm_fiu_do_uma(fiu, cs, true, false, 0); + + wpcm_fiu_set_opcode(fiu, op->addr.val & 0xff); + wpcm_fiu_set_addr(fiu, 0); + if (op->data.dir == SPI_MEM_DATA_OUT) + wpcm_fiu_set_data(fiu, op->data.buf.out, op->data.nbytes); + wpcm_fiu_do_uma(fiu, cs, false, op->data.dir == SPI_MEM_DATA_OUT, op->data.nbytes); + + wpcm_fiu_ects_deassert(fiu, cs); + + if (op->data.dir == SPI_MEM_DATA_IN) + wpcm_fiu_get_data(fiu, op->data.buf.in, op->data.nbytes); + + return 0; +} + +/* + * RDID (Read Identification) needs special handling because Linux expects to + * be able to read 6 ID bytes and FIU can only read up to 4 at once. + * + * We're lucky in this case, because executing the RDID instruction twice will + * result in the same result. + * + * What we do is as follows (C: write command/opcode byte, D: read data byte, + * A: write address byte): + * + * 1. C D D D + * 2. C A A A D D D + */ +static bool wpcm_fiu_rdid_match(const struct spi_mem_op *op) +{ + return op->cmd.opcode == 0x9f && op->addr.nbytes == 0 && + op->dummy.nbytes == 0 && op->data.nbytes == 6 && + op->data.dir == SPI_MEM_DATA_IN; +} + +static int wpcm_fiu_rdid_exec(struct spi_mem *mem, const struct spi_mem_op *op) +{ + struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller); + int cs = mem->spi->chip_select; + + /* First transfer */ + wpcm_fiu_set_opcode(fiu, op->cmd.opcode); + wpcm_fiu_set_addr(fiu, 0); + wpcm_fiu_do_uma(fiu, cs, false, false, 3); + wpcm_fiu_get_data(fiu, op->data.buf.in, 3); + + /* Second transfer */ + wpcm_fiu_set_opcode(fiu, op->cmd.opcode); + wpcm_fiu_set_addr(fiu, 0); + wpcm_fiu_do_uma(fiu, cs, true, false, 3); + wpcm_fiu_get_data(fiu, op->data.buf.in + 3, 3); + + return 0; +} + +/* + * With some dummy bytes. + * + * C A A A X* X D D D D + * [C A A A D*][C D D D D] + */ +static bool wpcm_fiu_dummy_match(const struct spi_mem_op *op) +{ + // Opcode 0x0b (FAST READ) is treated differently in hardware + if (op->cmd.opcode == 0x0b) + return false; + + return (op->addr.nbytes == 0 || op->addr.nbytes == 3) && + op->dummy.nbytes >= 1 && op->dummy.nbytes <= 5 && + op->data.nbytes <= 4; +} + +static int wpcm_fiu_dummy_exec(struct spi_mem *mem, const struct spi_mem_op *op) +{ + struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller); + int cs = mem->spi->chip_select; + + wpcm_fiu_ects_assert(fiu, cs); + + /* First transfer */ + wpcm_fiu_set_opcode(fiu, op->cmd.opcode); + wpcm_fiu_set_addr(fiu, op->addr.val); + wpcm_fiu_do_uma(fiu, cs, op->addr.nbytes != 0, true, op->dummy.nbytes - 1); + + /* Second transfer */ + wpcm_fiu_set_opcode(fiu, 0); + wpcm_fiu_set_addr(fiu, 0); + wpcm_fiu_do_uma(fiu, cs, false, false, op->data.nbytes); + wpcm_fiu_get_data(fiu, op->data.buf.in, op->data.nbytes); + + wpcm_fiu_ects_deassert(fiu, cs); + + return 0; +} + +static const struct wpcm_fiu_op_shape wpcm_fiu_op_shapes[] = { + { .match = wpcm_fiu_normal_match, .exec = wpcm_fiu_normal_exec }, + { .match = wpcm_fiu_fast_read_match, .exec = wpcm_fiu_fast_read_exec }, + { .match = wpcm_fiu_4ba_match, .exec = wpcm_fiu_4ba_exec }, + { .match = wpcm_fiu_rdid_match, .exec = wpcm_fiu_rdid_exec }, + { .match = wpcm_fiu_dummy_match, .exec = wpcm_fiu_dummy_exec }, +}; + +static const struct wpcm_fiu_op_shape *wpcm_fiu_find_op_shape(const struct spi_mem_op *op) +{ + size_t i; + + for (i = 0; i < ARRAY_SIZE(wpcm_fiu_op_shapes); i++) { + const struct wpcm_fiu_op_shape *shape = &wpcm_fiu_op_shapes[i]; + + if (shape->match(op)) + return shape; + } + + return NULL; +} + +static bool wpcm_fiu_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) +{ + if (!spi_mem_default_supports_op(mem, op)) + return false; + + if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr) + return false; + + if (op->cmd.buswidth > 1 || op->addr.buswidth > 1 || + op->dummy.buswidth > 1 || op->data.buswidth > 1) + return false; + + return wpcm_fiu_find_op_shape(op) != NULL; +} + +/* + * In order to ensure the integrity of SPI transfers performed via UMA, + * temporarily disable (stall) memory accesses coming from the host CPU. + */ +static void wpcm_fiu_stall_host(struct wpcm_fiu_spi *fiu, bool stall) +{ + if (fiu->shm_regmap) { + int res = regmap_update_bits(fiu->shm_regmap, SHM_FLASH_SIZE, + SHM_FLASH_SIZE_STALL_HOST, + stall ? SHM_FLASH_SIZE_STALL_HOST : 0); + if (res) + dev_warn(fiu->dev, "Failed to (un)stall host memory accesses: %d\n", res); + } +} + +static int wpcm_fiu_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) +{ + struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller); + const struct wpcm_fiu_op_shape *shape = wpcm_fiu_find_op_shape(op); + + wpcm_fiu_stall_host(fiu, true); + + if (shape) + return shape->exec(mem, op); + + wpcm_fiu_stall_host(fiu, false); + + return -ENOTSUPP; +} + +static int wpcm_fiu_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) +{ + if (op->data.nbytes > 4) + op->data.nbytes = 4; + + return 0; +} + +static const struct spi_controller_mem_ops wpcm_fiu_mem_ops = { + .adjust_op_size = wpcm_fiu_adjust_op_size, + .supports_op = wpcm_fiu_supports_op, + .exec_op = wpcm_fiu_exec_op, +}; + +static void wpcm_fiu_hw_init(struct wpcm_fiu_spi *fiu) +{ + /* Deassert all manually asserted chip selects */ + writeb(0x0f, fiu->regs + FIU_UMA_ECTS); +} + +static int wpcm_fiu_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct spi_controller *ctrl; + struct wpcm_fiu_spi *fiu; + struct resource *res; + + ctrl = devm_spi_alloc_master(dev, sizeof(*fiu)); + if (!ctrl) + return -ENOMEM; + + fiu = spi_controller_get_devdata(ctrl); + fiu->dev = dev; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "control"); + fiu->regs = devm_ioremap_resource(dev, res); + if (IS_ERR(fiu->regs)) { + dev_err(dev, "Failed to map registers\n"); + return PTR_ERR(fiu->regs); + } + + fiu->clk = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(fiu->clk)) + return PTR_ERR(fiu->clk); + + fiu->shm_regmap = syscon_regmap_lookup_by_phandle_optional(dev->of_node, "nuvoton,shm"); + + wpcm_fiu_hw_init(fiu); + + ctrl->bus_num = -1; + ctrl->mem_ops = &wpcm_fiu_mem_ops; + ctrl->num_chipselect = 4; + ctrl->dev.of_node = dev->of_node; + + /* + * The FIU doesn't include a clock divider, the clock is entirely + * determined by the AHB3 bus clock. + */ + ctrl->min_speed_hz = clk_get_rate(fiu->clk); + ctrl->max_speed_hz = clk_get_rate(fiu->clk); + + return devm_spi_register_controller(dev, ctrl); +} + +static const struct of_device_id wpcm_fiu_dt_ids[] = { + { .compatible = "nuvoton,wpcm450-fiu", }, + { } +}; +MODULE_DEVICE_TABLE(of, wpcm_fiu_dt_ids); + +static struct platform_driver wpcm_fiu_driver = { + .driver = { + .name = "wpcm450-fiu", + .bus = &platform_bus_type, + .of_match_table = wpcm_fiu_dt_ids, + }, + .probe = wpcm_fiu_probe, +}; +module_platform_driver(wpcm_fiu_driver); + +MODULE_DESCRIPTION("Nuvoton WPCM450 FIU SPI controller driver"); +MODULE_AUTHOR("Jonathan Neuschäfer "); +MODULE_LICENSE("GPL"); From patchwork Thu Nov 24 19:14:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Patchwork-Id: 25692 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp3570196wrr; Thu, 24 Nov 2022 11:15:12 -0800 (PST) X-Google-Smtp-Source: AA0mqf47JMwCJeeVhugKBJFVJXpV+r8XUk4qc9spZXZEkJI+dRn5fkunr3r4RcroRR+0ZSXUpL8e X-Received: by 2002:a17:903:3311:b0:186:d5b9:fbcd with SMTP id jk17-20020a170903331100b00186d5b9fbcdmr17931466plb.64.1669317312428; Thu, 24 Nov 2022 11:15:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669317312; cv=none; d=google.com; s=arc-20160816; b=CUuMYo0Eqxs9ujeAtts9bwhv4l/6EDODZPl+fqhC0D4TUqleMKp6t/2F1OZKbnTlaF JJw8jC5pEVpWbY4J309EnR53NxW0Q4CO+a4v2b0MDzX1hBtETN38LblxFQ7QecxzU2wa MvIsIYZtVVjekayXMo31y46lAjerDQMbuR+/5Ej6D91VYZp5XTkmbZPi1/N5qj9eI4Be FRXNgcQifxO5jTu6cJIlo7mTVIMmp6Ma5gi6hFqfq6YV9M0U+ZXKjoK0FaqVa7GVwNk6 mEGJ1d471AX6AbNG5a7CE0HK+9cdCR8xH5krbj2fVc5iJeMHyJPm+3T2wKHdN09++mrr yqEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:ui-outboundreport:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=g597qjZ3xJNU43qRM2nl2+zh+pITvE3U655INd7TlcI=; b=VECM8aZkd3E9srdtODuAzJs6scURfTb9+mLTC2qrP9yV1tUwdLo/Eaap+R1sqtHAPW MIVe3bSZmVQyyVn+nAg1AZ8NkHCK/+91s5YbOEitm3DL1dRlvRhhH+mTQepQgsOo+32a NCdkw8xqXx+cvRGHe/Td/UlSzZaelJyiNRxtGzKBNgLofICDEZru+ExHlPezKO4Bv6HM vzqzZZXcyarsruEOpM+0xOZb5eVRJIBfr5ruNqs/ht1A1zOXAMbgk++xcEWRx4kIxpAD rqRBteeiNh1yVnc5vIPCpRxoLvoJf3XyhCGhv+/JGnW5xrM2f90+DfuhgAr/ytsqcZZY aUeg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmx.net header.s=s31663417 header.b=AHL1Snn1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmx.net Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id l16-20020a170903121000b00179f8a3f838si1882454plh.593.2022.11.24.11.14.59; Thu, 24 Nov 2022 11:15:12 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmx.net header.s=s31663417 header.b=AHL1Snn1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmx.net Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229625AbiKXTOZ (ORCPT + 99 others); Thu, 24 Nov 2022 14:14:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56310 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229564AbiKXTOS (ORCPT ); Thu, 24 Nov 2022 14:14:18 -0500 Received: from mout.gmx.net (mout.gmx.net [212.227.17.21]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD08287574; Thu, 24 Nov 2022 11:14:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=s31663417; t=1669317250; bh=3d5wRu8H4rV67y0AcOBjPXJoU2peJtLzij7b7I+rk+E=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=AHL1Snn1Vm7i2/aVQdLF4IOE8e6Emt2n8GJq4hhGCRo7W84WAj0lzNSs19P9nPz0d MtPAobnGdOcJL5PLVM5VvciM4xnJUhzMTk3nNc2QYA0XZTdNtOwJOA0k5JByXZcJ/D 6Naz04BTGYa/mwo4Aplg1GkvvWxKm73YkObQJO9JFTN1H9fOgRaJBA2V5TCuSmsFo2 iqW6AjOJx1fa0BCD0enYWaGDyZPN0muE4wPZmAoVmIWQDvleP25saEVVBS6xawDAon h8+NPdxMDBLHD0Qc6v2xn9/cYnxNt0eAhEFbGVrMbvwE213A+GsH5H9IWi2iuWbDP6 qGj6JFWRVh4dg== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from probook ([95.223.44.31]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1N9dsb-1p19wy493t-015WKW; Thu, 24 Nov 2022 20:14:10 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-spi@vger.kernel.org, openbmc@lists.ozlabs.org Cc: Rob Herring , Krzysztof Kozlowski , =?utf-8?q?Jonathan?= =?utf-8?q?_Neusch=C3=A4fer?= , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown Subject: [PATCH v2 3/3] spi: wpcm-fiu: Add direct map support Date: Thu, 24 Nov 2022 20:14:00 +0100 Message-Id: <20221124191400.287918-4-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221124191400.287918-1-j.neuschaefer@gmx.net> References: <20221124191400.287918-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:t39AaDJmFgdivvbDoFkLkv/flCQ4QNQrXQ2seNnr38jxbz8uLGN JD5xXUQIO3bnfEZqbhcRCCIQ7El0WW/RjX68OSU1BTf4yRQmWiuiBh5cynZYZNGPp+ZXuAq jUobt8Pk/6DCZUVg+Qkzytu+B72pAH86tu5NN0Fm4aEiA5OkEdYTgfIGH4gjNswKxHjN8hy x7AT8dVbmva2t2HUQDN8w== UI-OutboundReport: notjunk:1;M01:P0:DSc4kqUiQ7M=;FiW4VAxGlixqn7OX9WfgMCy5tx+ 2oAG/ANhk0sOGSzuKDGhfJlQKLYfHl0xMBP6zguUlv4VAx775fS9BDJ2DBFw+1HmYWZPxcsDI udtzt1BzbYNodInMXUL3zq593vuqK2mJULpIyinQ0W4crSXJSIm/LGNKOLLrpDTg2UJoNYCRV CEGs4jYQ1Gf/sUyTDskQpQRLPOG+ShwPQabTi2go+jRBbit0ZmTvS1/erKJgrmUlR4MxAK2go h5MOt9mbOUQERi9ujqm5yYzQk5V1z18h56HGvMDGR0WSOObAkZxxqk3ZV8qZu/03TxmABRVHE 44wML3KRU0luG0PWJSZq9pHR2qWeN8cXxnKnb8YxBQdptXUzZ9fByV0GW/VwM/Fw010NeXW3e LUKFSWkvytsWUWX1jKjTB21DlF01pr+OgRAHUyfAx/d+k4Eq1aN3jYvXxHKHMN/U7FRbO90m7 It9e+b+E/0C3GVqhpMshViU2E32CYWPPUxlVoKq41UaEEbWPTipSz/etR/A/JrKAQ5Zdyd6Vz IoxMNkZuxz1COLQw1lR59BEPjL1Jm09tWeLC8po6K/QFzxasx0cm+VCaRhdcCwkjZfWJhSRH4 qKq5BFSTL1rpQ9yYapDK4kxpadGD1tQhzzF5mvmvIJuxaILpFTd8SQzrLEKwQ0SB9FASxPlfQ D+NPkF5syRHmnETUYlncYBjTjnB/aXh80CewmfWS8g1hF6qZLqswaqd3zy9HDXl5yZY8xIq3t 1xAm9vn3otlFzCWFzCSCiaj5XztwqOCUzdZRMEPfxB86/lM1rZ/uDjs46+TMofkrELGaFNq6r Dh2viJeBV5ovODz/8ionBN6tyCyO9irM/HvT9MAQxGNJAzUdJNlmUpZylnyQduRlsKloTZU+u LyGr20/QujC6HZGZJZiz0nDODqazXh6M+/anxi1KSDZMwph4SffihQrSnV9MpJ7Q2dcBuvjua AbJ0vO8ivqIpH0kXMbcPZ2jyKiI= X-Spam-Status: No, score=0.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2,RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750406069909149765?= X-GMAIL-MSGID: =?utf-8?q?1750406069909149765?= Besides software controlled SPI transfers (UMA, "user mode access"), FIU also supports a 16 MiB mapping window per attached flash chip. This patch implements direct mapped read access, to speed up flash reads. Without direct mapping: # time dd if=/dev/mtd0ro of=dump bs=1M 16+0 records in 16+0 records out real 1m 47.74s user 0m 0.00s sys 1m 47.75s With direct mapping: # time dd if=/dev/mtd0ro of=dump bs=1M 16+0 records in 16+0 records out real 0m 30.81s user 0m 0.00s sys 0m 30.81s Signed-off-by: Jonathan Neuschäfer --- v2: - Fix a few nits from the kernel test robot - Fix check for fiu->memory mapping error v1: - https://lore.kernel.org/lkml/20221105185911.1547847-9-j.neuschaefer@gmx.net/ --- drivers/spi/spi-wpcm-fiu.c | 64 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) -- 2.35.1 diff --git a/drivers/spi/spi-wpcm-fiu.c b/drivers/spi/spi-wpcm-fiu.c index e525fe074f883..ab33710d50ac8 100644 --- a/drivers/spi/spi-wpcm-fiu.c +++ b/drivers/spi/spi-wpcm-fiu.c @@ -51,10 +51,16 @@ */ #define UMA_WAIT_ITERATIONS 100 +/* The memory-mapped view of flash is 16 MiB long */ +#define MAX_MEMORY_SIZE_PER_CS (16 << 20) +#define MAX_MEMORY_SIZE_TOTAL (4 * MAX_MEMORY_SIZE_PER_CS) + struct wpcm_fiu_spi { struct device *dev; struct clk *clk; void __iomem *regs; + void __iomem *memory; + size_t memory_size; struct regmap *shm_regmap; }; @@ -367,14 +373,64 @@ static int wpcm_fiu_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) return 0; } +static int wpcm_fiu_dirmap_create(struct spi_mem_dirmap_desc *desc) +{ + struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(desc->mem->spi->controller); + int cs = desc->mem->spi->chip_select; + + if (desc->info.op_tmpl.data.dir != SPI_MEM_DATA_IN) + return -ENOTSUPP; + + /* + * Unfortunately, FIU only supports a 16 MiB direct mapping window (per + * attached flash chip), but the SPI MEM core doesn't support partial + * direct mappings. This means that we can't support direct mapping on + * flashes that are bigger than 16 MiB. + */ + if (desc->info.offset + desc->info.length > MAX_MEMORY_SIZE_PER_CS) + return -ENOTSUPP; + + /* Don't read past the memory window */ + if (cs * MAX_MEMORY_SIZE_PER_CS + desc->info.offset + desc->info.length > fiu->memory_size) + return -ENOTSUPP; + + return 0; +} + +static ssize_t wpcm_fiu_direct_read(struct spi_mem_dirmap_desc *desc, u64 offs, size_t len, void *buf) +{ + struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(desc->mem->spi->controller); + int cs = desc->mem->spi->chip_select; + + if (offs >= MAX_MEMORY_SIZE_PER_CS) + return -ENOTSUPP; + + offs += cs * MAX_MEMORY_SIZE_PER_CS; + + if (!fiu->memory || offs >= fiu->memory_size) + return -ENOTSUPP; + + len = min_t(size_t, len, fiu->memory_size - offs); + memcpy_fromio(buf, fiu->memory + offs, len); + + return len; +} + static const struct spi_controller_mem_ops wpcm_fiu_mem_ops = { .adjust_op_size = wpcm_fiu_adjust_op_size, .supports_op = wpcm_fiu_supports_op, .exec_op = wpcm_fiu_exec_op, + .dirmap_create = wpcm_fiu_dirmap_create, + .dirmap_read = wpcm_fiu_direct_read, }; static void wpcm_fiu_hw_init(struct wpcm_fiu_spi *fiu) { + /* Configure memory-mapped flash access */ + writeb(FIU_BURST_CFG_R16, fiu->regs + FIU_BURST_BFG); + writeb(MAX_MEMORY_SIZE_TOTAL / (512 << 10), fiu->regs + FIU_CFG); + writeb(MAX_MEMORY_SIZE_PER_CS / (512 << 10) | BIT(6), fiu->regs + FIU_SPI_FL_CFG); + /* Deassert all manually asserted chip selects */ writeb(0x0f, fiu->regs + FIU_UMA_ECTS); } @@ -404,6 +460,14 @@ static int wpcm_fiu_probe(struct platform_device *pdev) if (IS_ERR(fiu->clk)) return PTR_ERR(fiu->clk); + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "memory"); + fiu->memory = devm_ioremap_resource(dev, res); + fiu->memory_size = min_t(size_t, resource_size(res), MAX_MEMORY_SIZE_TOTAL); + if (IS_ERR(fiu->memory)) { + dev_err(dev, "Failed to map flash memory window\n"); + return PTR_ERR(fiu->memory); + } + fiu->shm_regmap = syscon_regmap_lookup_by_phandle_optional(dev->of_node, "nuvoton,shm"); wpcm_fiu_hw_init(fiu);