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[2620:137:e000::1:20]) by mx.google.com with ESMTP id e8-20020a170902b78800b00186c3af9680si1009757pls.98.2022.11.24.05.25.43; Thu, 24 Nov 2022 05:25:56 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b="vZSRB/vr"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230059AbiKXNGv (ORCPT + 99 others); Thu, 24 Nov 2022 08:06:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57710 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230056AbiKXNGr (ORCPT ); Thu, 24 Nov 2022 08:06:47 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8E721025CA; Thu, 24 Nov 2022 05:06:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1669295206; x=1700831206; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jkht1lqZ+yao+3lR7ZjiS5rsmbUp+VlY/aGj4tz6xiw=; b=vZSRB/vrqLIKAW0wvTSHPdSH/gGIgAcFy/pmppL0b/Szcidir6NFsiKN ZXqDcOTXy/jDGZwPXRPM84EP5lO482xaxpzmAlmjEiRmLqFD0DZEY5P3n q+nu4nvLZM2d4VHwxVfb8ig2gPG3RnlIv73gpw3E/sAyuqf8T+CbRfCkQ J9X+Npl5xG+M8XsqVru6v7Zv76hLm5hnbCNuq6fKfvXxtsYbRwgO6RQrx ooEJTlXcnyKhJl111zYNPiZgZTfI+V1elQ9EZU+NhL6jSeM5o6sDav7Os jIDbf37vl0t+bzW00IvBx/r9YAqLTnveBt1DSsGIGzDaieq2uI/FSyYEN A==; X-IronPort-AV: E=Sophos;i="5.96,190,1665471600"; d="scan'208";a="185029556" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 24 Nov 2022 06:06:45 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 24 Nov 2022 06:06:44 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 24 Nov 2022 06:06:42 -0700 From: Conor Dooley To: CC: Conor Dooley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Heiko Stuebner , Andrew Jones , Guo Ren , , Subject: [PATCH 1/2] dt-bindings: riscv: fix underscore requirement for addtional standard extensions Date: Thu, 24 Nov 2022 13:04:40 +0000 Message-ID: <20221124130440.306771-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221124130440.306771-1-conor.dooley@microchip.com> References: <20221124130440.306771-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750384096604189392?= X-GMAIL-MSGID: =?utf-8?q?1750384096604189392?= The RISC-V ISA Manual allows for the first Additional Standard Extension having no leading underscore. Only if there are multiple Additional Standard Extensions is it needed to have an underscore. The dt-binding does not validate that a multi-letter extension is canonically ordered, as that'd need an even worse regex than is here, but it should not fail validation for valid ISA strings. Allow the first Z multi-letter extension to appear immediately prior after the single-letter extensions. Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5 Fixes: 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators") Signed-off-by: Conor Dooley Acked-by: Guo Ren --- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 90a7cabf58fe..e80c967a4fa4 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -80,7 +80,7 @@ properties: insensitive, letters in the riscv,isa string must be all lowercase to simplify parsing. $ref: "/schemas/types.yaml#/definitions/string" - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$ + pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false From patchwork Thu Nov 24 13:04:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 25529 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp3396644wrr; Thu, 24 Nov 2022 05:28:23 -0800 (PST) X-Google-Smtp-Source: AA0mqf6SjbjAVVNd7fYoH7raKpzETnqN46Lgck/cIuGOfElreqJkIlfzhaIBbpMGfxDSXPqcSYhV X-Received: by 2002:a17:906:4556:b0:7ae:eaf1:c9e3 with SMTP id s22-20020a170906455600b007aeeaf1c9e3mr27712827ejq.551.1669296503742; Thu, 24 Nov 2022 05:28:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669296503; cv=none; d=google.com; s=arc-20160816; b=EQJ/Zbht42t6e5AblCz+kPaAA0lSLyq32IPh+LwdGQuizFn+9mBEtYGjRnHpKg/0+K SmeVS2oBYQ4/i8I5c43UmvodRs2I7vxrKXZozUv8zrunaNOeHRvJ0NAyMp/GtRC1XNML Bm11JuI33d/w0Xoa56eRm3gvcQim8hla9KTC1RgsEyYKzB327FEehIKdoUCwNwlUJlPg zjAvzvjXwRSUvxL0052zZVG0U3JoO/0A9xvZktpmY029k7wqNfZefYGgvT48gGYvF000 TaLlnSC18MeirakbUkiHxLgh6Bb518AFywwra3Anh8BeT8BGcAbfA9AIj/8TfoJnPiee 7QFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=cREo1w5lwP2WNJXm7PDH8SlkxY2dIcjNz7EAtLz+Xxw=; b=FGgXcYJ+AVEIcCUADZkjhWs56W1gX9cqsk/bUQ95P3g2OVzrOO7AxI2zpQ7izBWZ/K hn5ldlMQ2KOXrcO3t2hf7QmtrWWa3Xzr+45TEhf8jLrIFfEgXI/TRFrCp281IuK/F2E0 48RQYKfNU8TyVE8kFlGV74EBYZHXb+firK+X9ZdkKjeepcXlya3bPMsIM44fiGki7Ph8 v1HIimLe99kvGdQq0qUSB+uy2Ou0MJs1faH6glvWgECXKGnWUsy6LAc3GPGJR39PGYvb iw3aKgJ8Vo8bV0iJ/EJ6maEtHjHT4nCDpp8G6SUDI1gg28XLLBUftCxqmXC0FdlV9Lqc YYuQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=TrXY+1j7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Unfortunately that table did not match canonical order, as defined by the RISC-V ISA Manual, which defines extension ordering in (what is currently) Table 41, "Standard ISA extension names". Fix things up by re-sorting v (vector) and adding p (packed-simd) & j (dynamic languages). The e (reduced integer) and g (general) extensions are still intentionally left out. Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5 Fixes: 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators") Signed-off-by: Conor Dooley Reviewed-by: Heiko Stuebner Acked-by: Guo Ren Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt --- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index e80c967a4fa4..b7462ea2dbe4 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -80,7 +80,7 @@ properties: insensitive, letters in the riscv,isa string must be all lowercase to simplify parsing. $ref: "/schemas/types.yaml#/definitions/string" - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ + pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false