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Peter Anvin" , Subject: [PATCH v5 1/4] dt-bindings: x86: apic: Convert Intel's APIC bindings to YAML schema Date: Thu, 24 Nov 2022 16:41:40 +0800 Message-ID: <20221124084143.21841-2-rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221124084143.21841-1-rtanwar@maxlinear.com> References: <20221124084143.21841-1-rtanwar@maxlinear.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750367039068816070?= X-GMAIL-MSGID: =?utf-8?q?1750367039068816070?= Intel's APIC family of interrupt controllers support local APIC (lapic) & I/O APIC (ioapic). Convert existing bindings for lapic & ioapic from text to YAML schema. Separate lapic & ioapic schemas. Addditionally, add description which was missing in text file and add few more required standard properties which were also missing in text file. Suggested-by: Andy Shevchenko Signed-off-by: Rahul Tanwar Reviewed-by: Rob Herring --- .../intel,ce4100-ioapic.txt | 26 -------- .../intel,ce4100-ioapic.yaml | 60 +++++++++++++++++++ .../intel,ce4100-lapic.yaml | 57 ++++++++++++++++++ 3 files changed, 117 insertions(+), 26 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml create mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt deleted file mode 100644 index 7d19f494f19a..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt +++ /dev/null @@ -1,26 +0,0 @@ -Interrupt chips ---------------- - -* Intel I/O Advanced Programmable Interrupt Controller (IO APIC) - - Required properties: - -------------------- - compatible = "intel,ce4100-ioapic"; - #interrupt-cells = <2>; - - Device's interrupt property: - - interrupts =

; - - The first number (P) represents the interrupt pin which is wired to the - IO APIC. The second number (S) represents the sense of interrupt which - should be configured and can be one of: - 0 - Edge Rising - 1 - Level Low - 2 - Level High - 3 - Edge Falling - -* Local APIC - Required property: - - compatible = "intel,ce4100-lapic"; diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml new file mode 100644 index 000000000000..39ab8cdd19b4 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioapic.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel I/O Advanced Programmable Interrupt Controller (IO APIC) + +maintainers: + - Rahul Tanwar + +description: | + Intel's Advanced Programmable Interrupt Controller (APIC) is a + family of interrupt controllers. The APIC is a split + architecture design, with a local component (LAPIC) integrated + into the processor itself and an external I/O APIC. Local APIC + (lapic) receives interrupts from the processor's interrupt pins, + from internal sources and from an external I/O APIC (ioapic). + And it sends these to the processor core for handling. + See [1] Chapter 8 for more details. + + Many of the Intel's generic devices like hpet, ioapic, lapic have + the ce4100 name in their compatible property names because they + first appeared in CE4100 SoC. + + This schema defines bindings for I/O APIC interrupt controller. + + [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf + +properties: + compatible: + const: intel,ce4100-ioapic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + ioapic1: interrupt-controller@fec00000 { + compatible = "intel,ce4100-ioapic"; + reg = <0xfec00000 0x1000>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml new file mode 100644 index 000000000000..55184cb49432 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel Local Advanced Programmable Interrupt Controller (LAPIC) + +maintainers: + - Rahul Tanwar + +description: | + Intel's Advanced Programmable Interrupt Controller (APIC) is a + family of interrupt controllers. The APIC is a split + architecture design, with a local component (LAPIC) integrated + into the processor itself and an external I/O APIC. Local APIC + (lapic) receives interrupts from the processor's interrupt pins, + from internal sources and from an external I/O APIC (ioapic). + And it sends these to the processor core for handling. + See [1] Chapter 8 for more details. + + Many of the Intel's generic devices like hpet, ioapic, lapic have + the ce4100 name in their compatible property names because they + first appeared in CE4100 SoC. + + This schema defines bindings for local APIC interrupt controller. + + [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf + +properties: + compatible: + const: intel,ce4100-lapic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + lapic0: interrupt-controller@fee00000 { + compatible = "intel,ce4100-lapic"; + reg = <0xfee00000 0x1000>; + interrupt-controller; + #interrupt-cells = <2>; + }; From patchwork Thu Nov 24 08:41:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Tanwar X-Patchwork-Id: 25378 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp3272308wrr; Thu, 24 Nov 2022 00:54:53 -0800 (PST) X-Google-Smtp-Source: AA0mqf7HL7aQFxv7sRSC31uVICVKeYcG/0JXB32cOPRfwSTmSBIu8aSLgfz7gjyq3j7q16dUITjj X-Received: by 2002:a63:f925:0:b0:470:88:8c18 with SMTP id h37-20020a63f925000000b0047000888c18mr12741789pgi.23.1669280093298; Thu, 24 Nov 2022 00:54:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669280093; cv=none; d=google.com; s=arc-20160816; b=Zh0v5aN5CqBLCRUjexNzLIWzm3KzQ1zn8RlTfKNktK/rrYnXEPv/T7P37FdBnhDcPk LlNNAevtFYzSTAxJgPnrbj9dcBWjw90ZnC1MR75c0nspnkVtATebXD1tTEouJvTTYMYm I9DzT8XUlzYbhsxTl8tkdQsoo7F6o9kW/wvi6tQHLvja1tAaGOCgogt5ALAubkpPE8A4 mJoZdyGi+7zEO8vSrkh2f1znhYeCJdtJXwcXK7mxquxwQ8m7wg7KdT+vzAZRBs/9lLZm 7ljkFNayM3YYMAV6d9AfQtrVHIi4dE6WW+tkpI67pOxPT0iN1KPlzkcL5IeTAduGItGg r6GA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=bSWgzt8uUrAzN6dnc8c6kjh1UlFQHYngZsNHw6hiwAw=; b=uOpiduc70H2kvsUG7wN6oXCE/IG9mDqc4lDT6ZLB7xP3Z8IIcsiATDJBD1PHh/3XlR mRB+U0yRH5doweaDf+qft0yc/P0XV8CIt0kvpD6ChJlRXhnxQntkDNyKst5703C7eXZs LRnT88XrynzHDvOWd50WWpTgUxlbRrxchI4YZx4RLoC8GVX6pu+Go9T5RF0jk6BYjEFT Q0A2Z3jxXX1Z/FaMiS0cSOy6vjpyYlQzSy2IJfcsYrik8++jmHbtqTxXXRWkwMy8Swkn u5GIeLnBgNefdmaxkEm6L5UQ42zUzdl8I7yAwb1o1IXg6bRF52CQQJV8YfMldH168p0m P5eQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@maxlinear.com header.s=selector header.b=ayVJ013r; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=maxlinear.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" , Subject: [PATCH v5 2/4] dt-bindings: x86: apic: Introduce new optional bool property for lapic Date: Thu, 24 Nov 2022 16:41:41 +0800 Message-ID: <20221124084143.21841-3-rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221124084143.21841-1-rtanwar@maxlinear.com> References: <20221124084143.21841-1-rtanwar@maxlinear.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750367043436570489?= X-GMAIL-MSGID: =?utf-8?q?1750367043436570489?= Intel defines a few possible interrupt delivery modes. With respect to boot/init time, mainly two interrupt delivery modes are possible. PIC Mode - Legacy external 8259 compliant PIC interrupt controller. Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode. For ACPI or MPS spec compliant systems, it is figured out by some read only bit field/s available in their respective defined data structures. But for OF based systems, it is by default set to PIC mode. Presently, it is hardcoded to legacy PIC mode for OF based x86 systems with no option to choose the configuration between PIC mode & virtual wire mode. For this purpose, introduce a new boolean property for interrupt controller node of lapic which can allow it to be configured to virtual wire mode as well. Property name: 'intel,virtual-wire-mode' Type: Boolean If not present/not defined, interrupt delivery mode defaults to legacy PIC mode. If present/defined, interrupt delivery mode is set to virtual wire mode. Suggested-by: Andy Shevchenko Signed-off-by: Rahul Tanwar Reviewed-by: Rob Herring --- .../interrupt-controller/intel,ce4100-lapic.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml index 55184cb49432..d2d0145cb889 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml @@ -39,6 +39,19 @@ properties: '#interrupt-cells': const: 2 + intel,virtual-wire-mode: + description: Intel defines a few possible interrupt delivery + modes. With respect to boot/init time, mainly two interrupt + delivery modes are possible. + PIC Mode - Legacy external 8259 compliant PIC interrupt controller. + Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode. + For ACPI or MPS spec compliant systems, it is figured out by some read + only bit field/s available in their respective defined data structures. + For OF based systems, it is by default set to PIC mode. + But if this optional boolean property is set, then the interrupt delivery + mode is configured to virtual wire compatibility mode. + type: boolean + required: - compatible - reg @@ -54,4 +67,5 @@ examples: reg = <0xfee00000 0x1000>; interrupt-controller; #interrupt-cells = <2>; + intel,virtual-wire-mode; }; From patchwork Thu Nov 24 08:41:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Tanwar X-Patchwork-Id: 25380 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp3272424wrr; Thu, 24 Nov 2022 00:55:15 -0800 (PST) X-Google-Smtp-Source: AA0mqf5NBh2j3nZv0dTAkhcLJCwo98Ns5jCQ1ox52Cv/3LiRg0PnhzsPB1gC5G3fYA8NueYvlyfb X-Received: by 2002:a17:90a:4206:b0:213:2039:64c2 with SMTP id o6-20020a17090a420600b00213203964c2mr40801441pjg.165.1669280114889; Thu, 24 Nov 2022 00:55:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669280114; cv=none; d=google.com; s=arc-20160816; b=yrj3e01YBe75630fxg9d6N7EAztI5Ep6rcADc0lEuoU22v07BE6B+tUv0TUen9N6ZL a8CO5MEO/f0I6agWbnaW1O2AGyTuzpOliSqdtG0o4Qw9Yj29iUzYCN+c+xMu9KXnRXbj gpBitaFj1yLYW+M+h1v5EgPB+d5AHL00W9Vr0YIrSWUcxmea+mNtYTfRxqiC4mc+pA7G xV4+sCUm/xpR6vMG5SAahz5KYNgjRp7xVvwp+SSvNWjjLkYedXlO8rIWWuEa2zPwXVLo yg6xIWhDT1bPODNPn95gRQUQXbiPkHmBUr29SQ65VPK3aRLHscYQLtWrV4S0brcfpp9+ dc+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=AkBrFNa8JXU1rnG3IW0QD6QbjBzAOYoAULmyjQGwhog=; b=Szp5lkl6pnIVCIJR+vlTzB1dHKbCjKjLPWVlekMu7ycc04uOWMncrUyFGtrgu1/F1y PDZAUNSmmeZ0SNt/r1c5/DZmyZWUQL7UC9di3eQMUAaS9SgE65jY7KZvP86LFUkX+ZgB Y7z4gp1tf0QWnBpzXn7dLosj3PFhChcjqWvDdXSHO96dxCbkb4OCaeVE9+MXHl3/ERb8 cYJdDPpXgGxXes/CEOMZozwsgiukr/Vwmr423BDcvMXJgQQcqu+SLRFqJvJFruGBsoa9 FfoHr0DAGWCgGGSPqb1qjDRkIdoE2ARNpg9jQxJInxWNXL9CvCfTHvGvKxZngPinv5IX HpKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@maxlinear.com header.s=selector header.b=pxayFnwu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=maxlinear.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" , Subject: [PATCH v5 3/4] x86/of: Replace printk(KERN_LVL) with pr_lvl() Date: Thu, 24 Nov 2022 16:41:42 +0800 Message-ID: <20221124084143.21841-4-rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221124084143.21841-1-rtanwar@maxlinear.com> References: <20221124084143.21841-1-rtanwar@maxlinear.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750367065582433799?= X-GMAIL-MSGID: =?utf-8?q?1750367065582433799?= Use latest available pr_lvl() instead of older printk(KERN_LVL) Just a upgrade of print utilities usage no functional changes. Reviewed-by: Andy Shevchenko Suggested-by: Andy Shevchenko Signed-off-by: Rahul Tanwar --- arch/x86/kernel/devicetree.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index 5cd51f25f446..fcc6f1b7818f 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -248,7 +248,7 @@ static void __init dtb_add_ioapic(struct device_node *dn) ret = of_address_to_resource(dn, 0, &r); if (ret) { - printk(KERN_ERR "Can't obtain address from device node %pOF.\n", dn); + pr_err("Can't obtain address from device node %pOF.\n", dn); return; } mp_register_ioapic(++ioapic_id, r.start, gsi_top, &cfg); @@ -265,7 +265,7 @@ static void __init dtb_ioapic_setup(void) of_ioapic = 1; return; } - printk(KERN_ERR "Error: No information about IO-APIC in OF.\n"); + pr_err("Error: No information about IO-APIC in OF.\n"); } #else static void __init dtb_ioapic_setup(void) {} From patchwork Thu Nov 24 08:41:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Tanwar X-Patchwork-Id: 25379 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp3272398wrr; Thu, 24 Nov 2022 00:55:09 -0800 (PST) X-Google-Smtp-Source: AA0mqf6LaPeBOZQqlGm7U7LG4TCJVqUndeAZAlyVbRoKQvBAKPLuk+3DiHIWW7wLtNXyl0wn1I7L X-Received: by 2002:a17:902:d4c8:b0:188:a40b:47cd with SMTP id o8-20020a170902d4c800b00188a40b47cdmr13153357plg.72.1669280109123; Thu, 24 Nov 2022 00:55:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669280109; cv=none; d=google.com; s=arc-20160816; b=0obpMRtudXHsl/fXVb9O6hP8g4+j+Emgx7aZGST6OMtzSC5M5xbKr0BUVMSGQiOxr+ 7i9crDHS2l0BYohy2msALzKDrGWdqP4CAGlmwr5rUcttNs8q/kfh3OblDqFPKEcoeqg9 t/dxtY7qIyHCIgtkwBv9k3p2/eWVWPZ5PUXlMJDVREMDVW/aNwTtde0sS2wQswjvTxov x/PI6JO/ad1g13yGWwQw7u/o6giECBESRVZqGTODZDenpzFqYMCYH+matLQFGIFC+10p H+6LIMMXjbWGWLVeirDrW//Ku6SYHjPEJos3snO6co6ReNCVHGnoOVNN56g2lsZ0LcA0 66bw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=OKxjoXJRVhUevg2ny6svax9/xOJH1NA1wD73iH6x5No=; b=mX9R/NyAY77+bC7jUMcvOBQp9W7WjD84CrYl2uOPVkb5PJy4VO0NeEVR5ldYaL/rHI /eTfXHcozk4aFZYC3sEj/FHBk+KLDmhNeqS22kJVkhj4pYOas6TuwfWQMyzrqndNK1io SlWPqDbdSAkUquqqsdp0Gu2lj/QkGzzHtTYqoHPTYgC2F1rU5TUaPFCJHkYLT9anrLXU 80v+5BI181xtikOxptjVxUL76fKZdcVdV2JTZNg+ff57STg8P32q7QDGk4tWVqDkqNQe 3yW8ZsQl9pTt8j1tOBDdkvRfu7zFMZDBbrTfLEHIDz6QwDKV0yfK0mS+CnrFadZ4HNdQ DiPw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@maxlinear.com header.s=selector header.b=jlPE16zy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=maxlinear.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" , Subject: [PATCH v5 4/4] x86/of: Add support for boot time interrupt delivery mode configuration Date: Thu, 24 Nov 2022 16:41:43 +0800 Message-ID: <20221124084143.21841-5-rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221124084143.21841-1-rtanwar@maxlinear.com> References: <20221124084143.21841-1-rtanwar@maxlinear.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750367059982910483?= X-GMAIL-MSGID: =?utf-8?q?1750367059982910483?= Presently, init/boot time interrupt delivery mode is enumerated only for ACPI enabled systems by parsing MADT table or for older systems by parsing MP table. But for OF based x86 systems, it is assumed & hardcoded to legacy PIC mode. This causes boot time crash for platforms which do not use 8259 compliant legacy PIC. Add support for configuration of init time interrupt delivery mode for x86 OF based systems by introducing a new optional boolean property 'intel,virtual-wire-mode' for interrupt-controller node of local APIC. This property emulates IMCRP Bit 7 of MP feature info byte 2 of MP floating pointer structure. Defaults to legacy PIC mode if absent. Configures it to virtual wire compatibility mode if present. Reviewed-by: Andy Shevchenko Signed-off-by: Rahul Tanwar --- arch/x86/kernel/devicetree.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index fcc6f1b7818f..458e43490414 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -167,7 +167,14 @@ static void __init dtb_lapic_setup(void) return; } smp_found_config = 1; - pic_mode = 1; + if (of_property_read_bool(dn, "intel,virtual-wire-mode")) { + pr_info("Virtual Wire compatibility mode.\n"); + pic_mode = 0; + } else { + pr_info("IMCR and PIC compatibility mode.\n"); + pic_mode = 1; + } + register_lapic_address(lapic_addr); }