Message ID | f4789b3f9c963f0d8f2653d787abb73d58b91360.1695804418.git.unicornxw@gmail.com |
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Wed, 27 Sep 2023 02:03:05 -0700 (PDT) From: Chen Wang <unicornxw@gmail.com> To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org, guoren@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, xiaoguang.xing@sophgo.com, apatel@ventanamicro.com Cc: Chen Wang <unicornxw@gmail.com>, Conor Dooley <conor.dooley@microchip.com>, Chen Wang <wangchen20@iscas.ac.cn> Subject: [PATCH v3 11/11] riscv: defconfig: enable SOPHGO SoC Date: Wed, 27 Sep 2023 17:02:58 +0800 Message-Id: <f4789b3f9c963f0d8f2653d787abb73d58b91360.1695804418.git.unicornxw@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <cover.1695804418.git.unicornxw@gmail.com> References: <cover.1695804418.git.unicornxw@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-0.6 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); 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Series |
Add Milk-V Pioneer RISC-V board support
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Commit Message
Chen Wang
Sept. 27, 2023, 9:02 a.m. UTC
Enable SOPHGO SoC config in defconfig to allow the default upstream kernel to boot on Milk-V Pioneer board. Acked-by: Chao Wei <chao.wei@sophgo.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Guo Ren <guoren@kernel.org> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn> Signed-off-by: Chen Wang <unicornxw@gmail.com> --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index ab86ec3b9eab..bf737cfa1d2c 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -32,6 +32,7 @@ CONFIG_SOC_SIFIVE=y CONFIG_SOC_STARFIVE=y CONFIG_ARCH_SUNXI=y CONFIG_SOC_VIRT=y +CONFIG_ARCH_SOPHGO=y CONFIG_SMP=y CONFIG_HOTPLUG_CPU=y CONFIG_PM=y