Message ID | dde2e4b5ac6018adb9bfae05bb3800af6b7c0f0e.1684767562.git.michal.simek@amd.com |
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State | New |
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Mon, 22 May 2023 10:00:37 -0500 From: Michal Simek <michal.simek@amd.com> To: <linux-kernel@vger.kernel.org>, <monstr@monstr.eu>, <michal.simek@xilinx.com>, <git@xilinx.com> CC: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>, Conor Dooley <conor+dt@kernel.org>, Harini Katakam <harini.katakam@amd.com>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, Laurent Pinchart <laurent.pinchart@ideasonboard.com>, Michael Grzeschik <m.grzeschik@pengutronix.de>, Rob Herring <robh+dt@kernel.org>, "Robert Hancock" <robert.hancock@calian.com>, Tanmay Shah <tanmay.shah@amd.com>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org> Subject: [PATCH v2 5/6] arm64: zynqmp: Add pmu interrupt-affinity Date: Mon, 22 May 2023 16:59:52 +0200 Message-ID: <dde2e4b5ac6018adb9bfae05bb3800af6b7c0f0e.1684767562.git.michal.simek@amd.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <cover.1684767562.git.michal.simek@amd.com> References: <cover.1684767562.git.michal.simek@amd.com> MIME-Version: 1.0 X-Developer-Signature: v=1; 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arm64: zynqmp: Misc zynqmp changes
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Commit Message
Michal Simek
May 22, 2023, 2:59 p.m. UTC
From: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Based on dt-binding "This property should present when there is more than a single SPI" that's also case that's why explicitly specify interrupt affinity to avoid incorrect usage. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> --- Changes in v2: - Update commit message to remove OS content - reported by Laurent This avoids the following error upon linux boot: armv8-pmu pmu: hw perfevents: no interrupt-affinity property, guessing. --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++++ 1 file changed, 4 insertions(+)
Comments
On 5/22/23 16:59, Michal Simek wrote: > From: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > Based on dt-binding "This property should present when there is more than a > single SPI" that's also case that's why explicitly specify interrupt > affinity to avoid incorrect usage. > > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > Signed-off-by: Michal Simek <michal.simek@amd.com> > --- > > Changes in v2: > - Update commit message to remove OS content - reported by Laurent > > This avoids the following error upon linux boot: > armv8-pmu pmu: hw perfevents: no interrupt-affinity property, > guessing. > > --- > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > index 02bd75900238..fc5e21bc647c 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > @@ -164,6 +164,10 @@ pmu { > <0 144 4>, > <0 145 4>, > <0 146 4>; > + interrupt-affinity = <&cpu0>, > + <&cpu1>, > + <&cpu2>, > + <&cpu3>; > }; > > psci { Applied. M
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 02bd75900238..fc5e21bc647c 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -164,6 +164,10 @@ pmu { <0 144 4>, <0 145 4>, <0 146 4>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; }; psci {