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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Lorenzo Bianconi , Matthias Brugger , AngeloGioacchino Del Regno , Andrew Lunn , Heiner Kallweit , Russell King , Alexander Couzens , Daniel Golle , Philipp Zabel , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org Subject: [RFC PATCH 7/8] dt-bindings: net: mediatek,net: fix and complete mt7988-eth binding Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Thu, 09 Nov 2023 13:53:05 -0800 (PST) X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782124966811800365 X-GMAIL-MSGID: 1782124966811800365 Remove clocks which were copied from the vendor driver but are now taken care of by dedicated drivers for PCS and PHY in the upstream driver. Also remove mediatek,sgmiisys phandle which isn't required on MT7988 because we use pcs-handle on the MAC nodes instead. Last but not least, add an example for MT7988. Fixes: c94a9aabec36 ("dt-bindings: net: mediatek,net: add mt7988-eth binding") Signed-off-by: Daniel Golle --- .../devicetree/bindings/net/mediatek,net.yaml | 171 +++++++++++++++--- 1 file changed, 142 insertions(+), 29 deletions(-) diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Documentation/devicetree/bindings/net/mediatek,net.yaml index e74502a0afe86..c0f7bb6f3ef8d 100644 --- a/Documentation/devicetree/bindings/net/mediatek,net.yaml +++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml @@ -27,9 +27,6 @@ properties: - mediatek,mt7988-eth - ralink,rt5350-eth - reg: - maxItems: 1 - clocks: true clock-names: true @@ -115,6 +112,9 @@ allOf: - mediatek,mt7623-eth then: properties: + reg: + maxItems: 1 + interrupts: maxItems: 3 @@ -149,6 +149,9 @@ allOf: - mediatek,mt7621-eth then: properties: + reg: + maxItems: 1 + interrupts: maxItems: 1 @@ -174,6 +177,9 @@ allOf: const: mediatek,mt7622-eth then: properties: + reg: + maxItems: 1 + interrupts: maxItems: 3 @@ -215,6 +221,9 @@ allOf: const: mediatek,mt7629-eth then: properties: + reg: + maxItems: 1 + interrupts: maxItems: 3 @@ -257,6 +266,9 @@ allOf: const: mediatek,mt7981-eth then: properties: + reg: + maxItems: 1 + interrupts: minItems: 4 @@ -295,6 +307,9 @@ allOf: const: mediatek,mt7986-eth then: properties: + reg: + maxItems: 1 + interrupts: minItems: 4 @@ -333,36 +348,32 @@ allOf: const: mediatek,mt7988-eth then: properties: + reg: + maxItems: 2 + minItems: 2 + interrupts: minItems: 4 + maxItems: 4 clocks: - minItems: 34 - maxItems: 34 + minItems: 24 + maxItems: 24 clock-names: items: - - const: crypto + - const: xgp1 + - const: xgp2 + - const: xgp3 - const: fe - const: gp2 - const: gp1 - const: gp3 + - const: esw + - const: crypto - const: ethwarp_wocpu2 - const: ethwarp_wocpu1 - const: ethwarp_wocpu0 - - const: esw - - const: netsys0 - - const: netsys1 - - const: sgmii_tx250m - - const: sgmii_rx250m - - const: sgmii2_tx250m - - const: sgmii2_rx250m - - const: top_usxgmii0_sel - - const: top_usxgmii1_sel - - const: top_sgm0_sel - - const: top_sgm1_sel - - const: top_xfi_phy0_xtal_sel - - const: top_xfi_phy1_xtal_sel - const: top_eth_gmii_sel - const: top_eth_refck_50m_sel - const: top_eth_sys_200m_sel @@ -375,18 +386,9 @@ allOf: - const: top_netsys_sync_250m_sel - const: top_netsys_ppefb_250m_sel - const: top_netsys_warp_sel - - const: wocpu1 - - const: wocpu0 - - const: xgp1 - - const: xgp2 - - const: xgp3 - - mediatek,sgmiisys: - minItems: 2 - maxItems: 2 patternProperties: - "^mac@[0-1]$": + "^mac@[0-2]$": type: object unevaluatedProperties: false allOf: @@ -577,3 +579,114 @@ examples: }; }; }; + + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + ethernet@15100000 { + compatible = "mediatek,mt7988-eth"; + reg = <0 0x15100000 0 0x80000>, <0 0x15400000 0 0x380000>; + interrupts = , + , + , + ; + + clocks = <ðsys CLK_ETHDMA_XGP1_EN>, + <ðsys CLK_ETHDMA_XGP2_EN>, + <ðsys CLK_ETHDMA_XGP3_EN>, + <ðsys CLK_ETHDMA_FE_EN>, + <ðsys CLK_ETHDMA_GP2_EN>, + <ðsys CLK_ETHDMA_GP1_EN>, + <ðsys CLK_ETHDMA_GP3_EN>, + <ðsys CLK_ETHDMA_ESW_EN>, + <ðsys CLK_ETHDMA_CRYPT0_EN>, + <ðwarp CLK_ETHWARP_WOCPU2_EN>, + <ðwarp CLK_ETHWARP_WOCPU1_EN>, + <ðwarp CLK_ETHWARP_WOCPU0_EN>, + <&topckgen CLK_TOP_ETH_GMII_SEL>, + <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>, + <&topckgen CLK_TOP_ETH_SYS_200M_SEL>, + <&topckgen CLK_TOP_ETH_SYS_SEL>, + <&topckgen CLK_TOP_ETH_XGMII_SEL>, + <&topckgen CLK_TOP_ETH_MII_SEL>, + <&topckgen CLK_TOP_NETSYS_SEL>, + <&topckgen CLK_TOP_NETSYS_500M_SEL>, + <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>, + <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>, + <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>, + <&topckgen CLK_TOP_NETSYS_WARP_SEL>; + + clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1", + "gp3", "esw", "crypto", + "ethwarp_wocpu2", "ethwarp_wocpu1", + "ethwarp_wocpu0", "top_eth_gmii_sel", + "top_eth_refck_50m_sel", "top_eth_sys_200m_sel", + "top_eth_sys_sel", "top_eth_xgmii_sel", + "top_eth_mii_sel", "top_netsys_sel", + "top_netsys_500m_sel", "top_netsys_pao_2x_sel", + "top_netsys_sync_250m_sel", + "top_netsys_ppefb_250m_sel", + "top_netsys_warp_sel"; + assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, + <&topckgen CLK_TOP_NETSYS_GSW_SEL>, + <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>, + <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>, + <&topckgen CLK_TOP_SGM_0_SEL>, + <&topckgen CLK_TOP_SGM_1_SEL>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, + <&topckgen CLK_TOP_NET1PLL_D4>, + <&topckgen CLK_TOP_NET1PLL_D8_D4>, + <&topckgen CLK_TOP_NET1PLL_D8_D4>, + <&apmixedsys CLK_APMIXED_SGMPLL>, + <&apmixedsys CLK_APMIXED_SGMPLL>; + mediatek,ethsys = <ðsys>; + mediatek,infracfg = <&topmisc>; + #address-cells = <1>; + #size-cells = <0>; + + mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "internal"; + status = "disabled"; + + fixed-link { + speed = <10000>; + full-duplex; + pause; + }; + }; + + mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + status = "disabled"; + pcs-handle = <&usxgmiisys1>; + }; + + mac@2 { + compatible = "mediatek,eth-mac"; + reg = <2>; + status = "disabled"; + pcs-handle = <&usxgmiisys0>; + }; + + mdio_bus: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + /* internal 2.5G PHY */ + int_2p5g_phy: ethernet-phy@15 { + reg = <15>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "internal"; + }; + }; + }; + };