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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ1PEPF00001CE0.mail.protection.outlook.com (10.167.242.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7202.16 via Frontend Transport; Fri, 19 Jan 2024 18:24:06 +0000 Received: from bmoger-ubuntu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Fri, 19 Jan 2024 12:24:04 -0600 From: Babu Moger To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 13/17] x86/resctrl: Add data structures for ABMC assignment Date: Fri, 19 Jan 2024 12:22:15 -0600 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: <20231201005720.235639-1-babu.moger@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE0:EE_|IA1PR12MB6556:EE_ X-MS-Office365-Filtering-Correlation-Id: b6b2b605-7c44-4b2d-9776-08dc191bd260 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2024 18:24:06.2874 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b6b2b605-7c44-4b2d-9776-08dc191bd260 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6556 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784039146946894720 X-GMAIL-MSGID: 1788544324725512167 ABMC (Bandwidth Monitoring Event Configuration) counters can be configured by writing to L3_QOS_ABMC_CFG MSR. When ABMC is enabled, the user can configure a counter by writing to L3_QOS_ABMC_CFG setting the CfgEn field while specifying the Bandwidth Source, Bandwidth Types, and Counter Identifier. Add the MSR definition and individual field definitions. MSR L3_QOS_ABMC_CFG (C000_03FDh) definitions. ========================================================================== Bits Mnemonic Description Access Type Reset Value ========================================================================== 63 CfgEn Configuration Enable R/W 0 62 CtrEn Counter Enable R/W 0 61:53 – Reserved MBZ 0 52:48 CtrID Counter Identifier R/W 0 47 IsCOS BwSrc field is a COS R/W 0 (not an RMID) R/W 0 46:44 – Reserved MBZ 0 43:32 BwSrc Bandwidth Source R/W 0 (RMID or COS) 31:0 BwType Bandwidth types to R/W 0 track for this counter ========================================================================== The feature details are documentd in the APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth Monitoring (ABMC). Signed-off-by: Babu Moger Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 --- v2: No changes. --- arch/x86/include/asm/msr-index.h | 1 + arch/x86/kernel/cpu/resctrl/internal.h | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index ac0ce88a5978..148c2b8a2264 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1127,6 +1127,7 @@ #define MSR_IA32_SMBA_BW_BASE 0xc0000280 #define MSR_IA32_EVT_CFG_BASE 0xc0000400 #define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff +#define MSR_IA32_L3_QOS_ABMC_CFG 0xc00003fd /* MSR_IA32_VMX_MISC bits */ #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h index 865101c5e1c2..130854dc8b7f 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -63,6 +63,9 @@ #define TOTAL_ASSIGN BIT(0) #define LOCAL_ASSIGN BIT(1) +/* Maximum assignable counters per resctrl group */ +#define ABMC_MAX_CTR_PER_GROUP 2 + struct rdt_fs_context { struct kernfs_fs_context kfc; bool enable_cdpl2; @@ -170,6 +173,7 @@ enum rdtgrp_mode { * @crdtgrp_list: child rdtgroup node list * @rmid: rmid for this rdtgroup * @monitor_state: Assignment state of the group + * @abmc_ctr_id: ABMC counterids assigned to this group */ struct mongroup { struct kernfs_node *mon_data_kn; @@ -177,6 +181,7 @@ struct mongroup { struct list_head crdtgrp_list; u32 rmid; u32 monitor_state; + u32 abmc_ctr_id[ABMC_MAX_CTR_PER_GROUP]; }; /** @@ -532,6 +537,24 @@ union cpuid_0x10_x_edx { unsigned int full; }; +/* + * L3_QOS_ABMC_CFG MSR details. ABMC counters can be configured + * by writing to L3_QOS_ABMC_CFG. + */ +union l3_qos_abmc_cfg { + struct { + unsigned long bw_type :32, + bw_src :12, + rsvrd1 : 3, + is_cos : 1, + ctr_id : 5, + rsvrd : 9, + ctr_en : 1, + cfg_en : 1; + } split; + unsigned long full; +}; + void rdt_last_cmd_clear(void); void rdt_last_cmd_puts(const char *s); __printf(1, 2)