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Tue, 2 May 2023 08:36:13 -0500 From: Michal Simek To: , , , CC: Radhey Shyam Pandey , Harini Katakam , Krzysztof Kozlowski , Laurent Pinchart , Mathieu Poirier , Michael Grzeschik , Rob Herring , Robert Hancock , Tanmay Shah , , Subject: [PATCH 05/23] arm64: zynqmp: Add L2 cache nodes Date: Tue, 2 May 2023 15:35:33 +0200 Message-ID: X-Mailer: git-send-email 2.36.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E636:EE_|SA0PR12MB7075:EE_ X-MS-Office365-Filtering-Correlation-Id: 29505f44-0d7d-4a3e-3a2a-08db4b123433 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: o5FpvT1PT6gk38hELV2/cson+ItdbHeUMuLVvxMxOq+PBxlmqb7CV7LcylP5DIYU74gwNCL46/Pq1xA6+B9VJ5nAwsgpDvOSqHlEAETIavZJ3AYROSFUZ9HQ/jXJBR+KRhfThF4p37QLarP9QqyvefstqS/Qv8HeVwFhBcwoevN5jKl2eJYgdBstpwG47Op1L+5+ef0WBpXNU/UItvJ23o275YQMsFXrBijzZ9I8TV2nLSF4PF1KzqIhn6+4Im5H0UqhQBHsWYde5iT8qMkGgOZhNCJfGpebNfQ3fwIjjQLZByXT53si9a5eTEaP/ZDU04pzAiuBw+D275cw6Ma5wh5s7pCv/nPcIH4FzpHqscR+9yryLt09GcGAwT1Yfs+8svFttn93xb4qyXcUrAKlG6PSE/Fbv+/vrQa9/gEGNHvzURXVziEXOfl4aWdcMtfUfntd+5akejZiWpsYU+VxeaOUXGECaMAa0AO1oGvPICaNgMrVo4/+oKuek54szZCtUZ76wOa0vT8XgiO1mdU0za6caAUNJvJ32MRvFRGwxQA/CpGXLehyqSBz22RRih4fmDhruOYGMyY81/5VYbhyw6Cw2L9MD5RCA9aGMVlq/ww68awECJyStkMq8pKRxPUBAhN1FriV4ycRDklNMcIIn+DRk56SZu5D9QWREWwGG9o5sbDtCZ43JNiMuydA0FbsRz83hL5w3qjn+zMROhd15Q6A1V4NXr32q4wvOaxUnq6ZcreLzq8vGfQ+RXSsauW2 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(136003)(346002)(39860400002)(396003)(451199021)(46966006)(36840700001)(40470700004)(2616005)(16526019)(86362001)(356005)(4326008)(41300700001)(82740400003)(81166007)(40480700001)(316002)(83380400001)(6666004)(82310400005)(426003)(336012)(47076005)(26005)(186003)(36756003)(54906003)(40460700003)(36860700001)(110136005)(5660300002)(2906002)(70206006)(70586007)(8676002)(478600001)(44832011)(8936002)(7416002)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 May 2023 13:36:15.9542 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 29505f44-0d7d-4a3e-3a2a-08db4b123433 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E636.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB7075 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764790575658996074?= X-GMAIL-MSGID: =?utf-8?q?1764790575658996074?= From: Radhey Shyam Pandey Linux kernel throws "cacheinfo: Unable to detect cache hierarchy for CPU 0" warning when booting on zu+ Soc. To fix it add the L2 cache node and let each CPU point to it. Signed-off-by: Radhey Shyam Pandey Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index bb0d0be30aa0..c2d80c7967e9 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -33,6 +33,7 @@ cpu0: cpu@0 { operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; }; cpu1: cpu@1 { @@ -42,6 +43,7 @@ cpu1: cpu@1 { reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; }; cpu2: cpu@2 { @@ -51,6 +53,7 @@ cpu2: cpu@2 { reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; }; cpu3: cpu@3 { @@ -60,6 +63,12 @@ cpu3: cpu@3 { reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; }; idle-states {