[4/7] arm64: dts: ti: iot2050: Refactor the m.2 and minipcie power pin
Commit Message
From: Su Bao Cheng <baocheng.su@siemens.com>
Make the m.2 power control pin also available on miniPCIE variants.
This can fix some miniPCIE card hang issue, by forcing a power on reset
during boot.
Signed-off-by: Baocheng Su <baocheng.su@siemens.com>
---
.../arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi | 4 +++-
arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 11 +++++++++++
.../boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts | 8 +-------
3 files changed, 15 insertions(+), 8 deletions(-)
Comments
On 15:34-20231027, Jan Kiszka wrote:
> From: Su Bao Cheng <baocheng.su@siemens.com>
>
> Make the m.2 power control pin also available on miniPCIE variants.
>
> This can fix some miniPCIE card hang issue, by forcing a power on reset
> during boot.
>
> Signed-off-by: Baocheng Su <baocheng.su@siemens.com>
> ---
Jan - please Sign-off for the carried chain..
On 27.10.23 15:43, Nishanth Menon wrote:
> On 15:34-20231027, Jan Kiszka wrote:
>> From: Su Bao Cheng <baocheng.su@siemens.com>
>>
>> Make the m.2 power control pin also available on miniPCIE variants.
>>
>> This can fix some miniPCIE card hang issue, by forcing a power on reset
>> during boot.
>>
>> Signed-off-by: Baocheng Su <baocheng.su@siemens.com>
>> ---
>
> Jan - please Sign-off for the carried chain..
>
Sure, can do. Was intentionally not doing that because I somewhere
picked up that this is not desired.
Jan
On 15:45-20231027, Jan Kiszka wrote:
> On 27.10.23 15:43, Nishanth Menon wrote:
> > On 15:34-20231027, Jan Kiszka wrote:
> >> From: Su Bao Cheng <baocheng.su@siemens.com>
> >>
> >> Make the m.2 power control pin also available on miniPCIE variants.
> >>
> >> This can fix some miniPCIE card hang issue, by forcing a power on reset
> >> during boot.
> >>
> >> Signed-off-by: Baocheng Su <baocheng.su@siemens.com>
> >> ---
> >
> > Jan - please Sign-off for the carried chain..
> >
>
> Sure, can do. Was intentionally not doing that because I somewhere
> picked up that this is not desired.
Hmm... Documentation/process/submitting-patches.rst
Signed-off-by: must always be that of the developer submitting the
patch. --> I assume you are this ;).
Signed-off-by: First Co-Author <first@coauthor.example.org>
Signed-off-by: Second Co-Author <second@coauthor.example.org>
Signed-off-by: From Author <from@author.example.org>
Signed-off-by: Random Co-Author <random@coauthor.example.org>
Signed-off-by: From Author <from@author.example.org>
Signed-off-by: Submitting Co-Author <sub@coauthor.example.org>
@@ -20,7 +20,9 @@ AM65X_IOPAD(0x01e0, PIN_OUTPUT, 7)
&main_gpio1 {
pinctrl-names = "default";
- pinctrl-0 = <&cp2102n_reset_pin_default>;
+ pinctrl-0 =
+ <&main_pcie_enable_pins_default>,
+ <&cp2102n_reset_pin_default>;
gpio-line-names =
"", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
@@ -852,6 +852,12 @@ AM65X_IOPAD(0x00CC, PIN_INPUT_PULLDOWN, 7)
>;
};
+ main_pcie_enable_pins_default: main-pcie-enable-default-pins {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */
+ >;
+ };
+
main_uart1_pins_default: main-uart1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0174, PIN_INPUT, 6) /* (AE23) UART1_RXD */
@@ -981,6 +987,11 @@ &main_gpio0 {
"", "IO9";
};
+&main_gpio1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_pcie_enable_pins_default>;
+};
+
&wkup_gpio0 {
pinctrl-names = "default";
pinctrl-0 =
@@ -27,12 +27,6 @@ &mcu_r5fss0 {
};
&main_pmx0 {
- main_m2_enable_pins_default: main-m2-enable-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */
- >;
- };
-
main_bkey_pcie_reset: main-bkey-pcie-reset-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01bc, PIN_OUTPUT_PULLUP, 7) /* (AG13) GPIO1_15 */
@@ -72,7 +66,7 @@ &main_gpio0 {
&main_gpio1 {
pinctrl-names = "default";
pinctrl-0 =
- <&main_m2_enable_pins_default>,
+ <&main_pcie_enable_pins_default>,
<&main_pmx0_m2_config_pins_default>,
<&main_pmx1_m2_config_pins_default>,
<&cp2102n_reset_pin_default>;