diff mbox series

[v3,4/4] x86/of: Add support for boot time interrupt delivery mode configuration

Message ID c62b81d5b91514e905d97e37feff6920f598e0ac.1669100394.git.rtanwar@maxlinear.com
State New
Headers
Series x86/of: Fix a bug in x86 arch OF support |

Commit Message

Rahul Tanwar Nov. 22, 2022, 7:39 a.m. UTC 
  Presently, init/boot time interrupt delivery mode is enumerated
only for ACPI enabled systems by parsing MADT table or for older
systems by parsing MP table. But for OF based x86 systems, it is
assumed & hardcoded to legacy PIC mode. This is a bug for
platforms which are OF based but do not use 8259 compliant legacy
PIC interrupt controller. Such platforms can not even boot because
of this bug/hardcoding.

Fix this bug by adding support for configuration of init time
interrupt delivery mode for x86 OF based systems by introducing a
new optional boolean property 'intel,virtual-wire-mode' for
interrupt-controller node of local APIC. This property emulates
IMCRP Bit 7 of MP feature info byte 2 of MP floating pointer
structure.

Defaults to legacy PIC mode if absent. Configures it to virtual
wire compatibility mode if present.

Fixes: 3879a6f32948 ("x86: dtb: Add early parsing of IO_APIC")
Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
---
 arch/x86/kernel/devicetree.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

Comments

Andy Shevchenko Nov. 22, 2022, 9:14 a.m. UTC | #1 
On Tue, Nov 22, 2022 at 03:39:10PM +0800, Rahul Tanwar wrote:
> Presently, init/boot time interrupt delivery mode is enumerated
> only for ACPI enabled systems by parsing MADT table or for older
> systems by parsing MP table. But for OF based x86 systems, it is
> assumed & hardcoded to legacy PIC mode. This is a bug for
> platforms which are OF based but do not use 8259 compliant legacy
> PIC interrupt controller. Such platforms can not even boot because
> of this bug/hardcoding.
> 
> Fix this bug by adding support for configuration of init time
> interrupt delivery mode for x86 OF based systems by introducing a
> new optional boolean property 'intel,virtual-wire-mode' for
> interrupt-controller node of local APIC. This property emulates
> IMCRP Bit 7 of MP feature info byte 2 of MP floating pointer
> structure.
> 
> Defaults to legacy PIC mode if absent. Configures it to virtual
> wire compatibility mode if present.

> Fixes: 3879a6f32948 ("x86: dtb: Add early parsing of IO_APIC")

If it was never working, there is nothing to fix.
OTOH, without Cc: stable@ this is up to stable maintainers to
backport.


> Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

I definitely haven't suggested this fix.

...

The code looks good to me.
Rahul Tanwar Nov. 22, 2022, 9:45 a.m. UTC | #2 
On 22/11/2022 5:14 pm, Andy Shevchenko wrote:
> This email was sent from outside of MaxLinear.
> 
> 
> On Tue, Nov 22, 2022 at 03:39:10PM +0800, Rahul Tanwar wrote:
>> Presently, init/boot time interrupt delivery mode is enumerated
>> only for ACPI enabled systems by parsing MADT table or for older
>> systems by parsing MP table. But for OF based x86 systems, it is
>> assumed & hardcoded to legacy PIC mode. This is a bug for
>> platforms which are OF based but do not use 8259 compliant legacy
>> PIC interrupt controller. Such platforms can not even boot because
>> of this bug/hardcoding.
>>
>> Fix this bug by adding support for configuration of init time
>> interrupt delivery mode for x86 OF based systems by introducing a
>> new optional boolean property 'intel,virtual-wire-mode' for
>> interrupt-controller node of local APIC. This property emulates
>> IMCRP Bit 7 of MP feature info byte 2 of MP floating pointer
>> structure.
>>
>> Defaults to legacy PIC mode if absent. Configures it to virtual
>> wire compatibility mode if present.
> 
>> Fixes: 3879a6f32948 ("x86: dtb: Add early parsing of IO_APIC")
> 
> If it was never working, there is nothing to fix.
> OTOH, without Cc: stable@ this is up to stable maintainers to
> backport.
>

Agree, will remove fixes tag..


> 
>> Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> 
> I definitely haven't suggested this fix.
> 

Yes, i copy pasted to entire series. I will remove it from this patch.

> ...
> 
> The code looks good to me.
>

Thanks.

Regards,
Rahul


> --
> With Best Regards,
> Andy Shevchenko
> 
> 
>
Andy Shevchenko Nov. 22, 2022, 10:10 a.m. UTC | #3 
On Tue, Nov 22, 2022 at 09:45:29AM +0000, Rahul Tanwar wrote:
> On 22/11/2022 5:14 pm, Andy Shevchenko wrote:
> > On Tue, Nov 22, 2022 at 03:39:10PM +0800, Rahul Tanwar wrote:

...

> >> Fixes: 3879a6f32948 ("x86: dtb: Add early parsing of IO_APIC")
> > 
> > If it was never working, there is nothing to fix.
> > OTOH, without Cc: stable@ this is up to stable maintainers to
> > backport.
> 
> Agree, will remove fixes tag..

Don't forget to update cover letter and messages accordingly.
diff mbox series

Patch

diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index fcc6f1b7818f..458e43490414 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -167,7 +167,14 @@  static void __init dtb_lapic_setup(void)
 			return;
 	}
 	smp_found_config = 1;
-	pic_mode = 1;
+	if (of_property_read_bool(dn, "intel,virtual-wire-mode")) {
+		pr_info("Virtual Wire compatibility mode.\n");
+		pic_mode = 0;
+	} else {
+		pr_info("IMCR and PIC compatibility mode.\n");
+		pic_mode = 1;
+	}
+
 	register_lapic_address(lapic_addr);
 }