diff mbox series

[v2,1/2] PCI: dwc: Fix a 64bit bug in dw_pcie_ep_raise_msix_irq()

Message ID c5035dc2-a379-48f0-8544-aa57d642136b@moroto.mountain
State New
Headers
Series [v2,1/2] PCI: dwc: Fix a 64bit bug in dw_pcie_ep_raise_msix_irq() |

Commit Message

Dan Carpenter Jan. 19, 2024, 8:19 a.m. UTC 
  The "msg_addr" variable is u64.  However, the "aligned_offset" is an
unsigned int.  This means that when the code does:

        msg_addr &= ~aligned_offset;

it will unintentionally zero out the high 32 bits.  Declare
"aligned_offset" as a u64 to address this bug.

Fixes: 2217fffcd63f ("PCI: dwc: endpoint: Fix dw_pcie_ep_raise_msix_irq() alignment support")
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
---
v2: fix a typo in the commit message

 drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Ilpo Järvinen Jan. 19, 2024, 11:30 a.m. UTC | #1 
On Fri, 19 Jan 2024, Dan Carpenter wrote:

> The "msg_addr" variable is u64.  However, the "aligned_offset" is an
> unsigned int.  This means that when the code does:
> 
>         msg_addr &= ~aligned_offset;

Wouldn't it be more obvious to replace the entire line with this:
	msg_addr = ALIGN_DOWN(msg_addr, epc->mem->window.page_size);

+ add the #include for it. It should handle the casting to the same type 
internally.
diff mbox series

Patch

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 5befed2dc02b..2b6607c23541 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -525,7 +525,7 @@  int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
 	struct dw_pcie_ep_func *ep_func;
 	struct pci_epc *epc = ep->epc;
 	u32 reg, msg_data, vec_ctrl;
-	unsigned int aligned_offset;
+	u64 aligned_offset;
 	u32 tbl_offset;
 	u64 msg_addr;
 	int ret;