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[23.128.96.36]) by mx.google.com with ESMTPS id f3-20020aa79683000000b0068fb5ca50cdsi1228058pfk.126.2023.10.31.10.26.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Oct 2023 10:26:12 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) client-ip=23.128.96.36; Authentication-Results: mx.google.com; dkim=pass header.i=@siemens.com header.s=fm1 header.b=dOlcNtY+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=siemens.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id 91B01807C861; Tue, 31 Oct 2023 10:25:19 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346728AbjJaRYv (ORCPT + 33 others); Tue, 31 Oct 2023 13:24:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50064 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345489AbjJaRYt (ORCPT ); Tue, 31 Oct 2023 13:24:49 -0400 X-Greylist: delayed 61 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Tue, 31 Oct 2023 10:24:45 PDT Received: from mta-65-226.siemens.flowmailer.net (mta-65-226.siemens.flowmailer.net [185.136.65.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36DB99F for ; Tue, 31 Oct 2023 10:24:45 -0700 (PDT) Received: by mta-65-226.siemens.flowmailer.net with ESMTPSA id 2023103117234232e603a688e0e5a902 for ; Tue, 31 Oct 2023 18:23:42 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=jan.kiszka@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=uS7U8M/H5M0ZERJscFkJlzWuo4FJxRd/TE7u0fDUc7o=; b=dOlcNtY+H+d8XLuI1q3FMbUBeRUnxsQNvhetWmbP/YcXe6OjgvQ2dtYat32EIqxcploBYh Dtzg5MuD2NhnRMUbUQdyXsz+LCeDjPHxr5KZpdAis60e/vNasPcWUKPhdSjlO1Lv2kF023PT LDKIf/1TSM7GqWCSLoV6aQ9gi76gk=; From: Jan Kiszka To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bao Cheng Su , Benedikt Niedermayr Subject: [PATCH v2 4/5] arm64: dts: ti: iot2050: Refactor the m.2 and minipcie power pin Date: Tue, 31 Oct 2023 18:23:38 +0100 Message-Id: In-Reply-To: References: MIME-Version: 1.0 X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-294854:519-21489:flowmailer X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_MED,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Tue, 31 Oct 2023 10:25:19 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781292778865755234 X-GMAIL-MSGID: 1781292778865755234 From: Su Bao Cheng Make the m.2 power control pin also available on miniPCIE variants. This can fix some miniPCIE card hang issue, by forcing a power on reset during boot. Signed-off-by: Baocheng Su Signed-off-by: Jan Kiszka --- .../arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi | 4 +++- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 11 +++++++++++ .../boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts | 8 +------- 3 files changed, 15 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi index e9419c4fe605..e9b57b87e42e 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi @@ -20,7 +20,9 @@ AM65X_IOPAD(0x01e0, PIN_OUTPUT, 7) &main_gpio1 { pinctrl-names = "default"; - pinctrl-0 = <&cp2102n_reset_pin_default>; + pinctrl-0 = + <&main_pcie_enable_pins_default>, + <&cp2102n_reset_pin_default>; gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index 74c4accff4b7..53bd296ba310 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -852,6 +852,12 @@ AM65X_IOPAD(0x00CC, PIN_INPUT_PULLDOWN, 7) >; }; + main_pcie_enable_pins_default: main-pcie-enable-default-pins { + pinctrl-single,pins = < + AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */ + >; + }; + main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0174, PIN_INPUT, 6) /* (AE23) UART1_RXD */ @@ -981,6 +987,11 @@ &main_gpio0 { "", "IO9"; }; +&main_gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_pcie_enable_pins_default>; +}; + &wkup_gpio0 { pinctrl-names = "default"; pinctrl-0 = diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts index 8301c35c31b3..bd6f2e696e94 100644 --- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts @@ -27,12 +27,6 @@ &mcu_r5fss0 { }; &main_pmx0 { - main_m2_enable_pins_default: main-m2-enable-default-pins { - pinctrl-single,pins = < - AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */ - >; - }; - main_bkey_pcie_reset: main-bkey-pcie-reset-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01bc, PIN_OUTPUT_PULLUP, 7) /* (AG13) GPIO1_15 */ @@ -72,7 +66,7 @@ &main_gpio0 { &main_gpio1 { pinctrl-names = "default"; pinctrl-0 = - <&main_m2_enable_pins_default>, + <&main_pcie_enable_pins_default>, <&main_pmx0_m2_config_pins_default>, <&main_pmx1_m2_config_pins_default>, <&cp2102n_reset_pin_default>;