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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2023 03:34:23.0692 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3dd222a3-07f6-4038-f5cf-08db5107729c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000145B8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5190 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765477814843276286?= X-GMAIL-MSGID: =?utf-8?q?1765477814843276286?= Add the following data structures for corresponding ioctls: iommu_hwpt_arm_smmuv3 => IOMMUFD_CMD_HWPT_ALLOC iommu_hwpt_invalidate_arm_smmuv3 => IOMMUFD_CMD_HWPT_INVALIDATE The iommu_hwpt_arm_smmuv3 is a data structure to allocate an SMMU specific translation table, either a stage-1 Context Descriptor table or a stage-2 translation table, which would need the user Stream Table Entry or just a simple S2 flag respectively. The iommu_hwpt_invalidate_arm_smmuv3 is a data structure for a request of stage-1 cache invalidations that could be for TLB invalidations, Context Descriptor invalidations, and Address Translation Cache invalidations. The data structure contains all the necessary information about a user-space Command Queue, so the kernel can handle all invalidation commands with a single batch. Also, add IOMMU_HWPT_TYPE_ARM_SMMUV3 and IOMMU_HW_INFO_TYPE_ARM_SMMUV3. Signed-off-by: Nicolin Chen --- drivers/iommu/iommufd/main.c | 1 + include/uapi/linux/iommufd.h | 59 ++++++++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/drivers/iommu/iommufd/main.c b/drivers/iommu/iommufd/main.c index 7d7c11c1c912..8461b12c43b7 100644 --- a/drivers/iommu/iommufd/main.c +++ b/drivers/iommu/iommufd/main.c @@ -288,6 +288,7 @@ union ucmd_buffer { */ struct iommu_hwpt_invalidate_intel_vtd vtd; struct iommu_hwpt_invalidate_request_intel_vtd req_vtd; + struct iommu_hwpt_invalidate_arm_smmuv3 smmuv3; }; struct iommufd_ioctl_op { diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index c8f5801d3439..6845ce6e1e76 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -354,10 +354,12 @@ struct iommu_vfio_ioas { * enum iommu_hwpt_type - IOMMU HWPT Type * @IOMMU_HWPT_TYPE_DEFAULT: default * @IOMMU_HWPT_TYPE_VTD_S1: Intel VT-d stage-1 page table + * @IOMMU_HWPT_TYPE_ARM_SMMUV3: ARM SMMUv3 Translation table */ enum iommu_hwpt_type { IOMMU_HWPT_TYPE_DEFAULT, IOMMU_HWPT_TYPE_VTD_S1, + IOMMU_HWPT_TYPE_ARM_SMMUV3, }; /** @@ -413,6 +415,32 @@ struct iommu_hwpt_intel_vtd { __u32 __reserved; }; +/** + * struct iommu_hwpt_arm_smmuv3 - ARM SMMUv3 specific translation table data + * + * @flags: Translation table entry attributes + * @ste_len: Length of the user Stream Table Entry + * @ste_uptr: User pointer to a user Stream Table Entry + * @event_len: Length of the returning event + * @out_event_uptr: User pointer to a returning event, to report a C_BAD_STE upon + * an STE configuration failure + * + * If event_len or out_event_uptr is unset, remainning at value 0, an STE + * configuration failure during the hwpt allocation will not be reported. + * + * The data structure can be used to allocate a stage-2 translation table, in + * which case only IOMMU_SMMUV3_FLAG_S2 would matter, i.e. all other ste_* and + * envent_* inputs would be ignored. + */ +struct iommu_hwpt_arm_smmuv3 { +#define IOMMU_SMMUV3_FLAG_S2 (1 << 0) /* if unset, stage-1 */ + __u64 flags; + __u64 ste_len; + __aligned_u64 ste_uptr; + __u64 event_len; + __aligned_u64 out_event_uptr; +}; + /** * struct iommu_hwpt_alloc - ioctl(IOMMU_HWPT_ALLOC) * @size: sizeof(struct iommu_hwpt_alloc) @@ -448,6 +476,8 @@ struct iommu_hwpt_intel_vtd { * +------------------------------+-------------------------------------+-----------+ * | IOMMU_HWPT_TYPE_VTD_S1 | struct iommu_hwpt_intel_vtd | HWPT | * +------------------------------+-------------------------------------+-----------+ + * | IOMMU_HWPT_TYPE_ARM_SMMUV3 | struct iommu_hwpt_arm_smmuv3 | IOAS/HWPT | + * +------------------------------+-------------------------------------------------+ */ struct iommu_hwpt_alloc { __u32 size; @@ -465,10 +495,12 @@ struct iommu_hwpt_alloc { /** * enum iommu_hw_info_type - IOMMU Hardware Info Types * @IOMMU_HW_INFO_TYPE_INTEL_VTD: Intel VT-d iommu info type + * @IOMMU_HW_INFO_TYPE_ARM_SMMUV3: ARM SMMUv3 iommu info type */ enum iommu_hw_info_type { IOMMU_HW_INFO_TYPE_NONE, IOMMU_HW_INFO_TYPE_INTEL_VTD, + IOMMU_HW_INFO_TYPE_ARM_SMMUV3, }; /** @@ -603,6 +635,31 @@ struct iommu_hwpt_invalidate_intel_vtd { __u64 inv_data_uptr; }; +/** + * struct iommu_hwpt_invalidate_arm_smmuv3 - ARM SMMUv3 cahce invalidation info + * @cmdq_uptr: User pointer to a user command queue + * @cmdq_cons_uptr: User pointer to the consumer index of a user command queue, + * allowing kernel to read and also update the consumer index + * for a successful call or a failure with a CERROR_ILL code. + * This pointer must point to a __u32 type of memory location. + * @cmdq_prod: Producer index of user command queues + * @cmdq_entry_size: Entry size of a user command queue + * @cmdq_log2size: Queue size as log2(entries). Refer to 6.3.25 SMMU_CMDQ_BASE + * @__reserved: Must be 0 + * + * Both the consumer index and the producer index should be in their raw forms, + * i.e. the raw values out of the SMMU_CMDQ_PROD and SMMU_CMDQ_CONS registers, + * which include the WRAP bits also instead of simply the two index values. + */ +struct iommu_hwpt_invalidate_arm_smmuv3 { + __aligned_u64 cmdq_uptr; + __aligned_u64 cmdq_cons_uptr; + __u32 cmdq_prod; + __u32 cmdq_entry_size; + __u32 cmdq_log2size; + __u32 __reserved; +}; + /** * struct iommu_hwpt_invalidate - ioctl(IOMMU_HWPT_INVALIDATE) * @size: sizeof(struct iommu_hwpt_invalidate) @@ -620,6 +677,8 @@ struct iommu_hwpt_invalidate_intel_vtd { * +------------------------------+----------------------------------------+ * | IOMMU_HWPT_TYPE_VTD_S1 | struct iommu_hwpt_invalidate_intel_vtd | * +------------------------------+----------------------------------------+ + * | IOMMU_HWPT_TYPE_ARM_SMMUV3 | struct iommu_hwpt_invalidate_arm_smmuv3| + * +------------------------------+----------------------------------------+ */ struct iommu_hwpt_invalidate { __u32 size;