From patchwork Tue Nov 22 07:39:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Tanwar X-Patchwork-Id: 24177 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2059332wrr; Mon, 21 Nov 2022 23:41:59 -0800 (PST) X-Google-Smtp-Source: AA0mqf5j4oBIZ3dIB5m6e5pj3PvI+A9XY3AlQZAsQm1Bug7+MH/QL5CnBGMf2Gtiq1jFEqveWT5d X-Received: by 2002:a05:6a00:4501:b0:56b:b049:6c6c with SMTP id cw1-20020a056a00450100b0056bb0496c6cmr6599960pfb.22.1669102918748; Mon, 21 Nov 2022 23:41:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669102918; cv=none; d=google.com; s=arc-20160816; b=0DKk6DlHOV7cgQA7VOVCOFaMJT9KvLAcvY8D6pO4ooIjiqWyJyXp8B+3AhZ8UWJLwz 3ayS0/7+VJEcgScS2LGyBraDrtBqTvy1CRo1s7hfMsdYBfsJkFLVJosDjCxUWsSl2SH2 lbvLpNcP2dh82kMQvAQEq3EbX1xFzD+fEJ9rfc7AY0oeJ+V64cOucNLX13L3MBvtyrJn Kf/YWMXlCzo+Irg0iOXXvRB6MTo871rTdnoUQgz77PGVxr4Bxe/fkN55NGQbjtZSUn87 WCoUmh1nuMT5VLKiugY/PisJBt87jO8u/YSfO3NbB8MLPJd/nfhcdN9GMNq8iT4oGhpd VvaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=uGSJ7DPtFsorciAkWhHmN4hRW1hAr3Y9mVSmMvM8cgs=; b=Rici0lwqVa7eOIHkMc83/FQD93y66HUqL+J122/IiM/TZGGG9Ne398I3AExUF651wB x0Ngz3G7Qfah8FqsbF1s1w5KwPjMpUJe7EQN5B5y6EaKTS9+JJ0+33TMReb12Llizuu2 7VLxExk1pIlHsr4+cFy5tiqnks4Lr3ZWp5b6xsu03cHojkStc/KEL4Rr2Covp0V071jB 7g41kMkQdkTzNPemv32FsmYkIJDi2N2g+p5jHBX9wU2qtvIDC4BGF7e6pSyfEXXkW3sA MNnpsryyy7lfwbFA1An+BytqD4ecpBPiANylj6q3I/50r5xX9NyZAGw+8ecjnZmLBCEp NLeQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@maxlinear.com header.s=selector header.b=OXwjCA8E; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=maxlinear.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id m4-20020a056a00080400b00563a93471c5si14856816pfk.101.2022.11.21.23.41.42; Mon, 21 Nov 2022 23:41:58 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@maxlinear.com header.s=selector header.b=OXwjCA8E; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=maxlinear.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232487AbiKVHkj (ORCPT + 99 others); Tue, 22 Nov 2022 02:40:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50016 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232448AbiKVHk2 (ORCPT ); Tue, 22 Nov 2022 02:40:28 -0500 Received: from us-smtp-delivery-115.mimecast.com (us-smtp-delivery-115.mimecast.com [170.10.133.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 093FC17589 for ; Mon, 21 Nov 2022 23:39:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maxlinear.com; s=selector; t=1669102765; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=uGSJ7DPtFsorciAkWhHmN4hRW1hAr3Y9mVSmMvM8cgs=; b=OXwjCA8EU08bfMp/IWSWlK4upsCRm/k6RIu1R08bvQCjppyapAmg+AoGCCIQ9/NEnJSruj IGqHtaieGnHWi+HRge5KmC84vPfNPlPxL8F1ehyAUTxhxhA8n9IbNeiq6s1MTKSFKRQfRV lksnnx3ozgi960jJK2Nc78YOFSKUo/fRMossnVAXB8QuZhS266tUBBsWL+CzhG+e2D92sl Xvk4wiAl8SFJB5kuaZDrp2g71JsPO7serhn4wO4CGZKAeP6MwJ43zvU9uaV7xJY73fFZwf ROYSsj3iKVRHgqZDANMVmajNkJ3WdE+FvSWtuetAySH1sFRry9skWMvH/tjeyQ== Received: from mail.maxlinear.com (174-47-1-84.static.ctl.one [174.47.1.84]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id us-mta-564-hiVtk4evPvGvvH9_C1TAOw-1; Tue, 22 Nov 2022 02:39:24 -0500 X-MC-Unique: hiVtk4evPvGvvH9_C1TAOw-1 Received: from sgsxdev001.isng.phoenix.local (10.226.81.111) by mail.maxlinear.com (10.23.38.119) with Microsoft SMTP Server id 15.1.2375.24; Mon, 21 Nov 2022 23:39:20 -0800 From: Rahul Tanwar To: , , , , , , CC: , , , , Rahul Tanwar Subject: [PATCH v3 2/4] x86/of: Introduce new optional bool property for lapic Date: Tue, 22 Nov 2022 15:39:08 +0800 Message-ID: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750181262416223662?= X-GMAIL-MSGID: =?utf-8?q?1750181262416223662?= Intel defines a few possible interrupt delivery modes. With respect to boot/init time, mainly two interrupt delivery modes are possible. PIC Mode - Legacy external 8259 compliant PIC interrupt controller. Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode. For ACPI or MPS spec compliant systems, it is figured out by some read only bit field/s available in their respective defined data structures. But for OF based systems, it is by default set to PIC mode. Presently, it is hardcoded to legacy PIC mode for OF based x86 systems with no option to choose the configuration between PIC mode & virtual wire mode. For this purpose, introduce a new boolean property for interrupt controller node of lapic which can allow it to be configured to virtual wire mode as well. Property name: 'intel,virtual-wire-mode' Type: Boolean If not present/not defined, interrupt delivery mode defaults to legacy PIC mode. If present/defined, interrupt delivery mode is set to virtual wire mode. Suggested-by: Andy Shevchenko Signed-off-by: Rahul Tanwar --- .../interrupt-controller/intel,ce4100-lapic.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml index d4b99bf7bf6e..087f849e31ef 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml @@ -35,6 +35,19 @@ properties: reg: maxItems: 1 + intel,virtual-wire-mode: + description: Intel defines a few possible interrupt delivery + modes. With respect to boot/init time, mainly two interrupt + delivery modes are possible. + PIC Mode - Legacy external 8259 compliant PIC interrupt controller. + Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode. + For ACPI or MPS spec compliant systems, it is figured out by some read + only bit field/s available in their respective defined data structures. + For OF based systems, it is by default set to PIC mode. + But if this optional boolean property is set, then the interrupt delivery + mode is configured to virtual wire compatibility mode. + type: boolean + required: - compatible - reg @@ -46,4 +59,5 @@ examples: lapic0: interrupt-controller@fee00000 { compatible = "intel,ce4100-lapic"; reg = <0xfee00000 0x1000>; + intel,virtual-wire-mode; };