diff mbox series

[03/22] KVM: x86: Support IBPB_BRTYPE and SBPB

Message ID a4d62162bcb501e50b0bb19b748702aa12260615.1692580085.git.jpoimboe@kernel.org
State New
Headers
Series SRSO fixes/cleanups |

Commit Message

Josh Poimboeuf Aug. 21, 2023, 1:19 a.m. UTC 
  The IBPB_BRTYPE and SBPB CPUID bits aren't set by HW.

From the AMD SRSO whitepaper:

  "Hypervisor software should synthesize the value of both the
  IBPB_BRTYPE and SBPB CPUID bits on these platforms for use by guest
  software."

These bits are already set during kernel boot.  Manually propagate them
to the guest.

Also, propagate PRED_CMD_SBPB writes.

Signed-off-by: Josh Poimboeuf <jpoimboe@kernel.org>
---
 arch/x86/kvm/cpuid.c | 4 ++++
 arch/x86/kvm/x86.c   | 9 +++++----
 2 files changed, 9 insertions(+), 4 deletions(-)

Comments

Josh Poimboeuf Aug. 24, 2023, 5:07 p.m. UTC | #1 
On Thu, Aug 24, 2023 at 09:39:03AM -0700, Sean Christopherson wrote:
> > Also, since you're clearly more qualified to write this patch than me,
> > can I nominate you to do so? :-)
> 
> Sorry, didn't mean to ghost you.  I can write the patch, but I won't get to it
> before next week some time.

No worries, I'll pull in your code (with a reserved_bit fix) for my v2.
diff mbox series

Patch

diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index d3432687c9e6..cdf703eec42d 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -729,6 +729,10 @@  void kvm_set_cpu_caps(void)
 		F(NULL_SEL_CLR_BASE) | F(AUTOIBRS) | 0 /* PrefetchCtlMsr */
 	);
 
+	if (cpu_feature_enabled(X86_FEATURE_SBPB))
+		kvm_cpu_cap_set(X86_FEATURE_SBPB);
+	if (cpu_feature_enabled(X86_FEATURE_IBPB_BRTYPE))
+		kvm_cpu_cap_set(X86_FEATURE_IBPB_BRTYPE);
 	if (cpu_feature_enabled(X86_FEATURE_SRSO_NO))
 		kvm_cpu_cap_set(X86_FEATURE_SRSO_NO);
 
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index c381770bcbf1..dd7472121142 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -3676,12 +3676,13 @@  int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 		if (!msr_info->host_initiated && !guest_has_pred_cmd_msr(vcpu))
 			return 1;
 
-		if (!boot_cpu_has(X86_FEATURE_IBPB) || (data & ~PRED_CMD_IBPB))
+		if (boot_cpu_has(X86_FEATURE_IBPB) && data == PRED_CMD_IBPB)
+			wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
+		else if (boot_cpu_has(X86_FEATURE_SBPB) && data == PRED_CMD_SBPB)
+			wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_SBPB);
+		else if (data)
 			return 1;
-		if (!data)
-			break;
 
-		wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
 		break;
 	case MSR_IA32_FLUSH_CMD:
 		if (!msr_info->host_initiated &&