diff mbox series

[RFC,04/43] x86/entry/64: Adapt assembly for PIE support

Message ID	a0b69f3fac1834c05f960b916cc6eb0004cdffbf.1682673543.git.houwenlong.hwl@antgroup.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; From: "Hou Wenlong" <houwenlong.hwl@antgroup.com> To: linux-kernel@vger.kernel.org Cc: "Thomas Garnier" <thgarnie@chromium.org>, "Lai Jiangshan" <jiangshan.ljs@antgroup.com>, "Kees Cook" <keescook@chromium.org>, "Hou Wenlong" <houwenlong.hwl@antgroup.com>, "Andy Lutomirski" <luto@kernel.org>, "Thomas Gleixner" <tglx@linutronix.de>, "Ingo Molnar" <mingo@redhat.com>, "Borislav Petkov" <bp@alien8.de>, "Dave Hansen" <dave.hansen@linux.intel.com>, <x86@kernel.org>, "H. Peter Anvin" <hpa@zytor.com> Subject: [PATCH RFC 04/43] x86/entry/64: Adapt assembly for PIE support Date: Fri, 28 Apr 2023 17:50:44 +0800 Message-Id: <a0b69f3fac1834c05f960b916cc6eb0004cdffbf.1682673543.git.houwenlong.hwl@antgroup.com> In-Reply-To: <cover.1682673542.git.houwenlong.hwl@antgroup.com> References: <cover.1682673542.git.houwenlong.hwl@antgroup.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	x86/pie: Make kernel image's virtual address flexible \| [RFC,00/43] x86/pie: Make kernel image's virtual address flexible [RFC,01/43] x86/crypto: Adapt assembly for PIE support [RFC,02/43] x86: Add macro to get symbol address for PIE support [RFC,03/43] x86: relocate_kernel - Adapt assembly for PIE support [RFC,04/43] x86/entry/64: Adapt assembly for PIE support [RFC,05/43] x86: pm-trace: Adapt assembly for PIE support [RFC,06/43] x86/CPU: Adapt assembly for PIE support [RFC,07/43] x86/acpi: Adapt assembly for PIE support [RFC,09/43] x86/power/64: Adapt assembly for PIE support [RFC,10/43] x86/alternatives: Adapt assembly for PIE support [RFC,11/43] x86/irq: Adapt assembly for PIE support [RFC,12/43] x86,rethook: Adapt assembly for PIE support [RFC,13/43] x86/paravirt: Use relative reference for original instruction [RFC,14/43] x86/Kconfig: Introduce new Kconfig for PIE kernel building [RFC,15/43] x86/PVH: Use fixed_percpu_data to set up GS base [RFC,17/43] x86/pie: Enable stack protector only if per-cpu stack canary is supported [RFC,19/43] x86/tools: Explicitly include autoconf.h for hostprogs [RFC,21/43] x86/ftrace: Adapt assembly for PIE support [RFC,22/43] x86/ftrace: Adapt ftrace nop patching for PIE support [RFC,23/43] x86/pie: Force hidden visibility for all symbol references [RFC,24/43] x86/boot/compressed: Adapt sed command to generate voffset.h when PIE is enabled [RFC,27/43] x86/relocs: Handle PIE relocations [RFC,28/43] KVM: x86: Adapt assembly for PIE support [RFC,29/43] x86/PVH: Adapt PVH booting for PIE support [RFC,31/43] x86/modules: Adapt module loading for PIE support [RFC,32/43] x86/boot/64: Use data relocation to get absloute address when PIE is enabled [RFC,33/43] objtool: Add validation for x86 PIE support [RFC,34/43] objtool: Adapt indirect call of __fentry__() for PIE support [RFC,35/43] x86/pie: Build the kernel as PIE [RFC,36/43] x86/vsyscall: Don't use set_fixmap() to map vsyscall page [RFC,37/43] x86/xen: Pin up to VSYSCALL_ADDR when vsyscall page is out of fixmap area [RFC,39/43] x86/fixmap: Unify FIXADDR_TOP [RFC,40/43] x86/boot: Fill kernel image puds dynamically [RFC,41/43] x86/mm: Sort address_markers array when X86 PIE is enabled

Commit Message

Hou Wenlong April 28, 2023, 9:50 a.m. UTC

  From: Thomas Garnier <thgarnie@chromium.org>

From: Thomas Garnier <thgarnie@chromium.org>

Change the assembly code to use only relative references of symbols for
the kernel to be PIE compatible.

Signed-off-by: Thomas Garnier <thgarnie@chromium.org>
Signed-off-by: Hou Wenlong <houwenlong.hwl@antgroup.com>
Cc: Lai Jiangshan <jiangshan.ljs@antgroup.com>
Cc: Kees Cook <keescook@chromium.org>
---
 arch/x86/entry/entry_64.S | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff mbox series

Patch

diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S
index 21dca946955e..6f2297ebb15f 100644
--- a/arch/x86/entry/entry_64.S
+++ b/arch/x86/entry/entry_64.S
@@ -1089,7 +1089,8 @@  SYM_CODE_START(error_entry)
 	movl	%ecx, %eax			/* zero extend */
 	cmpq	%rax, RIP+8(%rsp)
 	je	.Lbstep_iret
-	cmpq	$.Lgs_change, RIP+8(%rsp)
+	leaq	.Lgs_change(%rip), %rcx
+	cmpq	%rcx, RIP+8(%rsp)
 	jne	.Lerror_entry_done_lfence
 
 	/*
@@ -1302,10 +1303,10 @@  SYM_CODE_START(asm_exc_nmi)
 	 * resume the outer NMI.
 	 */
 
-	movq	$repeat_nmi, %rdx
+	leaq	repeat_nmi(%rip), %rdx
 	cmpq	8(%rsp), %rdx
 	ja	1f
-	movq	$end_repeat_nmi, %rdx
+	leaq	end_repeat_nmi(%rip), %rdx
 	cmpq	8(%rsp), %rdx
 	ja	nested_nmi_out
 1:
@@ -1359,7 +1360,8 @@  nested_nmi:
 	pushq	%rdx
 	pushfq
 	pushq	$__KERNEL_CS
-	pushq	$repeat_nmi
+	leaq	repeat_nmi(%rip), %rdx
+	pushq	%rdx
 
 	/* Put stack back */
 	addq	$(6*8), %rsp
@@ -1398,7 +1400,11 @@  first_nmi:
 	addq	$8, (%rsp)	/* Fix up RSP */
 	pushfq			/* RFLAGS */
 	pushq	$__KERNEL_CS	/* CS */
-	pushq	$1f		/* RIP */
+	pushq	$0		/* Space for RIP */
+	pushq	%rdx		/* Save RDX */
+	leaq	1f(%rip), %rdx	/* Put the address of 1f label into RDX */
+	movq	%rdx, 8(%rsp)   /* Store it in RIP field */
+	popq	%rdx		/* Restore RDX */
 	iretq			/* continues at repeat_nmi below */
 	UNWIND_HINT_IRET_REGS
 1: