diff mbox series

[v3,5/8] riscv: dts: sophgo: Separate compatible specific for cv1800b soc

Message ID IA1PR20MB49533FF6B39C2275FB8F25C4BBD5A@IA1PR20MB4953.namprd20.prod.outlook.com
State New
Headers
Series Add Huashan Pi board support |

Commit Message

Inochi Amaoto Oct. 18, 2023, 11:31 a.m. UTC 
  Move the cv1800b soc specific compatible out of the common file.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
---
 arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 18 ++++++++++++++++++
 arch/riscv/boot/dts/sophgo/cv18xx.dtsi  |  3 ---
 2 files changed, 18 insertions(+), 3 deletions(-)
 create mode 100644 arch/riscv/boot/dts/sophgo/cv1800b.dtsi

--
2.42.0
diff mbox series

Patch

diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
new file mode 100644
index 000000000000..165e9e320a8c
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
@@ -0,0 +1,18 @@ 
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ */
+
+#include "cv18xx.dtsi"
+
+/ {
+	compatible = "sophgo,cv1800b";
+};
+
+&plic {
+	compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
+};
+
+&clint {
+	compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
+};
diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
index df40e87ee063..55d4bc84faa0 100644
--- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
@@ -6,7 +6,6 @@ 
 #include <dt-bindings/interrupt-controller/irq.h>

 / {
-	compatible = "sophgo,cv1800b";
 	#address-cells = <1>;
 	#size-cells = <1>;

@@ -105,7 +104,6 @@  uart4: serial@41c0000 {
 		};

 		plic: interrupt-controller@70000000 {
-			compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
 			reg = <0x70000000 0x4000000>;
 			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
 			interrupt-controller;
@@ -115,7 +113,6 @@  plic: interrupt-controller@70000000 {
 		};

 		clint: timer@74000000 {
-			compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
 			reg = <0x74000000 0x10000>;
 			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
 		};