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Tue, 2 May 2023 08:35:58 -0500 From: Michal Simek To: , , , CC: Amit Kumar Mahapatra , Ashok Reddy Soma , Krzysztof Kozlowski , Laurent Pinchart , Parth Gajjar , "Rob Herring" , Vishal Sagar , , Subject: [PATCH 01/23] arm64: zynqmp: Describe TI phy as ethernet-phy-id Date: Tue, 2 May 2023 15:35:29 +0200 Message-ID: <9eefc40c727928e0c7b794a3a2e061ecf6ea230c.1683034376.git.michal.simek@amd.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E638:EE_|SJ0PR12MB8167:EE_ X-MS-Office365-Filtering-Correlation-Id: 5009ebc9-6b32-40b8-3277-08db4b122a82 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rKmO0Mb44MBVcvBlDvYFwqfJ6PCtR7OwQ/IIT2A1lQb2bOkICjnFeKgc2wA2B1J99ivBcUt3kZ7gOb6awXQalTNERTnwyxgZS8E9HRfBzYr2gzX1cNGgt1jOA9DoPmcPYUg19XlxXqw/ZW1sl6Wk/3XRhNaHBQOqrxaBGEBY49D8W1k/MfGPxEkI6l2cYN2mGWXOq8uaEv5JgueW9RdmeJPlMA/BQrNtcHW5jszDbgnxWolw806a2uxV3aBcTW5MIXoiGfIHusxLKOP7M3ci0WYjm9almyBBXaE4jMbJ6ndb51raIaL/SH1cwJNLuXi4Nz/xBa4+GGgBzArokkhrHwA/dOaA59XTZobRzy1NmdvQqKsJ7t+E7yguHxbRI0v7NZmePnmeLtP6qCzSg7JUgudoFokVKOJGGmazx7wGJJ9rAXrwr9FiGy/QYThr0R9tn6TedFS/VR5aEpKwl7b+CKKE43TNn2C1q5KiwXQ1CLygvlNCvt90n64/4i8mxsIhJCK1G/pJbGCahvtcatjXogqaKaaMm/YxCvzPFkPqs2up5CrDW3KCp3LflivV758JUiUMMrClLnZd1KeRVCk7R54Wmf/ki1oOaJr0rTK+V2o7hx5s9mFfZw91JQ4Bsx/OEAq50Tjqh5eDvCBeFEmmyQFTX/WquQfy/xYun1Z2dCbyQR7lZo779qPSVAgMrIH5aa/6jJDWaB0i2lyVq+wPld+pIRvIbRroefnpQT9QztvMoRb+CaIOU1IGpP/Q2Xkd X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(136003)(346002)(39860400002)(396003)(451199021)(46966006)(36840700001)(40470700004)(2616005)(83380400001)(478600001)(36860700001)(186003)(16526019)(4326008)(54906003)(70586007)(70206006)(110136005)(26005)(47076005)(426003)(6666004)(336012)(44832011)(316002)(8676002)(40460700003)(82740400003)(8936002)(7416002)(5660300002)(356005)(41300700001)(2906002)(40480700001)(81166007)(82310400005)(86362001)(36756003)(36900700001)(2101003);DIR:OUT;SFP:1101; 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Tristate setup can influce PHY address. That's why switch description with ethernet-phy-id compatible string which enable calling reset. PHY itself setups phy address after power up or reset. Phy reset is done via gpio. Signed-off-by: Michal Simek --- Checkpatch is reporting issue warning: DT compatible string "ethernet-phy-id2000.a231" appears un-documented but it should be fully aligned with Documentation/devicetree/bindings/net/ethernet-phy.yaml --- .../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 23 +++++++++++------ .../boot/dts/xilinx/zynqmp-zcu102-revB.dts | 25 +++++++++++-------- .../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 22 ++++++++++------ .../boot/dts/xilinx/zynqmp-zcu104-revC.dts | 22 ++++++++++------ .../boot/dts/xilinx/zynqmp-zcu106-revA.dts | 22 ++++++++++------ .../boot/dts/xilinx/zynqmp-zcu111-revA.dts | 22 ++++++++++------ 6 files changed, 90 insertions(+), 46 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 13c43324f1d2..c193579400cf 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2021, Xilinx, Inc. + * (C) Copyright 2015 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -200,13 +201,19 @@ &gem3 { phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@21 { - reg = <21>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; - /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@21 { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <21>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; + }; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts index f7d718ff116b..00b930f20718 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2021, Xilinx, Inc. + * (C) Copyright 2016 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -16,16 +17,20 @@ / { &gem3 { phy-handle = <&phyc>; - phyc: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; - /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ + mdio: mdio { + phyc: ethernet-phy@c { + #phy-cells = <0x1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; + }; + /* Cleanup from RevA */ + /delete-node/ ethernet-phy@21; }; - /* Cleanup from RevA */ - /delete-node/ ethernet-phy@21; }; /* Fix collision with u61 */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index 485585c491f4..11c1eaef9f53 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -109,12 +110,19 @@ &gem3 { phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; + }; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts index 44ec9edd2452..c06c138fa3e5 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -114,12 +115,19 @@ &gem3 { phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; + }; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 09773b7200f8..52cdec33f190 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016 - 2021, Xilinx, Inc. + * (C) Copyright 2016 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -212,12 +213,19 @@ &gem3 { phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + reg = <0xc>; + compatible = "ethernet-phy-id2000.a231"; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; + }; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index e0305dcbb010..699cc9ce7898 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -172,12 +173,19 @@ &gem3 { phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>; + }; }; };