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AJvYcCVwnzI0kHslCfgqRzueMqyyaEU7GYP4Z1tuyYLATZC1rZI1T9UwbFlkAgXlgB35vkN46cG7gO7FsmcOOrLe0CIdOnDOUQdUrwQuZ20eiZCVP0cbIRg7sHMmIGszwTr2IL1wXYobs8Gtox/H30tdrtcxI4H/lNY8bi0T3yfBDZnLoJB1HA== X-Gm-Message-State: AOJu0YwbHkpiUKyz0WldkAjyh9Lzhz53erjFc476C5JKySggEpb2qj8a nn07Y18mgHtr1wkY2LLnAtV0OO+UUZTv4RRrqtBxwGIhobNmcs0H X-Received: by 2002:a05:6870:b6a4:b0:21e:4a2a:f058 with SMTP id cy36-20020a056870b6a400b0021e4a2af058mr15934161oab.18.1708398618390; Mon, 19 Feb 2024 19:10:18 -0800 (PST) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id wh14-20020a056871a68e00b0021e80b769edsm1679994oab.8.2024.02.19.19.10.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Feb 2024 19:10:18 -0800 (PST) From: Chen Wang To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, palmer@dabbelt.com, paul.walmsley@sifive.com, richardcochran@gmail.com, robh+dt@kernel.org, sboyd@kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com, guoren@kernel.org, jszhang@kernel.org, inochiama@outlook.com, samuel.holland@sifive.com Cc: Chen Wang Subject: [PATCH v11 5/5] riscv: dts: add clock generator for Sophgo SG2042 SoC Date: Tue, 20 Feb 2024 11:10:11 +0800 Message-Id: <98b42a20f7f5a6938563b6a2ad839299ce3ab9fe.1708397315.git.unicorn_wang@outlook.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791385885700769278 X-GMAIL-MSGID: 1791385885700769278 From: Chen Wang Add clock generator node to device tree for SG2042, and enable clock for uart. Signed-off-by: Chen Wang Reviewed-by: Guo Ren --- .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 +++++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 48 +++++++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts index 49b4b9c2c101..80cb017974d8 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts @@ -14,6 +14,18 @@ chosen { }; }; +&cgi_main { + clock-frequency = <25000000>; +}; + +&cgi_dpll0 { + clock-frequency = <25000000>; +}; + +&cgi_dpll1 { + clock-frequency = <25000000>; +}; + &uart0 { status = "okay"; }; diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index ead1cc35d88b..e70c43e2ccbe 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -5,6 +5,9 @@ /dts-v1/; #include +#include +#include +#include #include "sg2042-cpus.dtsi" @@ -18,12 +21,54 @@ aliases { serial0 = &uart0; }; + cgi_main: oscillator0 { + compatible = "fixed-clock"; + clock-output-names = "cgi_main"; + #clock-cells = <0>; + }; + + cgi_dpll0: oscillator1 { + compatible = "fixed-clock"; + clock-output-names = "cgi_dpll0"; + #clock-cells = <0>; + }; + + cgi_dpll1: oscillator2 { + compatible = "fixed-clock"; + clock-output-names = "cgi_dpll1"; + #clock-cells = <0>; + }; + soc: soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; + pllclk: clock-controller@70300100c0 { + compatible = "sophgo,sg2042-pll"; + reg = <0x70 0x300100c0 0x0 0x40>; + clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>; + #clock-cells = <1>; + }; + + rpgate: clock-controller@7030010368 { + compatible = "sophgo,sg2042-rpgate"; + reg = <0x70 0x30010368 0x0 0x98>; + clocks = <&clkgen GATE_CLK_RP_CPU_NORMAL>; + #clock-cells = <1>; + }; + + clkgen: clock-controller@7030012000 { + compatible = "sophgo,sg2042-clkgen"; + reg = <0x70 0x30012000 0x0 0x1000>; + clocks = <&pllclk MPLL_CLK>, + <&pllclk FPLL_CLK>, + <&pllclk DPLL0_CLK>, + <&pllclk DPLL1_CLK>; + #clock-cells = <1>; + }; + clint_mswi: interrupt-controller@7094000000 { compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; reg = <0x00000070 0x94000000 0x00000000 0x00004000>; @@ -333,6 +378,9 @@ uart0: serial@7040000000 { interrupt-parent = <&intc>; interrupts = <112 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <500000000>; + clocks = <&clkgen GATE_CLK_UART_500M>, + <&clkgen GATE_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled";