Message ID | 8f95a33f3f28d97750afda64536de312772ce60b.1683688960.git.nicolinc@nvidia.com |
---|---|
State | New |
Headers |
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Tue, 9 May 2023 20:34:19 -0700 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Tue, 9 May 2023 20:34:18 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.986.37 via Frontend Transport; Tue, 9 May 2023 20:34:17 -0700 From: Nicolin Chen <nicolinc@nvidia.com> To: <jgg@nvidia.com>, <robin.murphy@arm.com>, <will@kernel.org> CC: <eric.auger@redhat.com>, <kevin.tian@intel.com>, <baolu.lu@linux.intel.com>, <joro@8bytes.org>, <shameerali.kolothum.thodi@huawei.com>, <jean-philippe@linaro.org>, <linux-arm-kernel@lists.infradead.org>, <iommu@lists.linux.dev>, <linux-kernel@vger.kernel.org>, <kvm@vger.kernel.org>, <alex.williamson@redhat.com>, <yi.l.liu@intel.com> Subject: [PATCH v2 08/17] iommu/arm-smmu-v3: Unset corresponding STE fields when s2_cfg is NULL Date: Tue, 9 May 2023 20:33:28 -0700 Message-ID: <8f95a33f3f28d97750afda64536de312772ce60b.1683688960.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <cover.1683688960.git.nicolinc@nvidia.com> References: <cover.1683688960.git.nicolinc@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT009:EE_|SJ0PR12MB6830:EE_ X-MS-Office365-Filtering-Correlation-Id: 63f1edcf-e6da-479f-e847-08db51077667 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Series |
Add Nested Translation Support for SMMUv3
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Commit Message
Nicolin Chen
May 10, 2023, 3:33 a.m. UTC
From: Eric Auger <eric.auger@redhat.com> Despite the spec does not seem to mention this, on some implementations, when the STE configuration switches from an S1+S2 cfg to an S1 only one, a C_BAD_STE error would happen if dst[3] (S2TTB) is not reset. Explicitly reset those two higher 64b fields, to prevent that. Note that this is not a bug at this moment, since a 2-stage translation setup is not yet enabled, until the following patches add its support. Reported-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Link: https://patchwork.kernel.org/cover/11449895/#23244457 Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Nicolin Chen <nicolinc@nvidia.com> --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index c57c70132c0b..792e8a788e2e 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1373,6 +1373,17 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, dst[3] = cpu_to_le64(s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK); val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S2_TRANS); + } else { + /* + * Unset dst[2] and dst[3] to clear stage-2 configurations. This was observed + * on a HiSilicon implementation where, if the SMMUv3 is configured with both + * stage-1 and stage-2 mode once, it is not possible to configure it back for + * stage-1 mode for the same device (stream id). The SMMUv3 implementation on + * these boards expects to set the S2TTB field in STE to zero when using S1, + * otherwise it reports C_BAD_STE error. + */ + dst[2] = 0; + dst[3] = 0; } if (master->ats_enabled)